IBM NetVista X40, Technical Information Manual

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Technical Information
IDE connectors
A52 Address/data 8 I/O B52 Address/data 8 I/O
A53 Address/data 7 I/O B53 Address/data 7 I/O
A54 +3.3 V dc N/A B54 +3.3 V dc N/A
A55 Address/data 5 I/O B55 Address/data 5 I/O
A56 Address/data 3 I/O B56 Address/data 3 I/O
A57 Ground N/A B57 Ground N/A
A58 Address/data 1 I/O B58 Address/data 1 I/O
A59 +5 V dc (I/O) N/A B59 +5 V dc (I/O) N/A
A60 ACK64# I/O B60 ACK64# I/O
A61 +5 V dc N/A B61 +5 V dc N/A
A62 +5 V dc N/A A62 +5 V dc N/A
Table 23. IDE connector pin assignments
Pin Signal I/O Pin Signal I/O
1 RESET O 21 NC N/A
2 Ground N/A 22 Ground N/A
3 Data bus bit 7 I/O 23 I/O write O
4 Data bus bit 8 I/O 24 NC N/A
5 Data bus bit 6 I/O 25 I/O read O
6 Data bus bit 9 I/O 26 Ground I
7 Data bus bit 5 I/O 27 I/O channel ready I
8 Data bus bit 10 I/O 28 ALE O
9 Data bus bit 4 I/O 29 NC N/A
10 Data bus bit 11 I/O 30 Ground N/A
11 Data bus bit 3 I/O 31 IRQ I
12 Data bus bit 12 I/O 32 CS16# I
13 Data bus bit 2 I/O 33 SA1 O
14 Data bus bit 13 I/O 34 PDIAG# I
Table 22. PCI connector pin assignments
Pin Signal I/O Pin Signal I/O
1
2
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