IBM MiEM78P468L Product Specification Download Page 54

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EM78P468N/EM78P468L

8-Bit Microcontroller

•

Product Specification (V1.5) 02.15.2007

(This specification is subject to change without further notice)

Binary Instruction

Hex

Mnemonic

Operation

Status

Affected

0 0110 00rr

rrrr 06rr

RRCA R

R(n)

→

A(n-1),

R(0)

→

C, C

→

A(7)

0 0110 01rr

rrrr 06rr

RRC R

R(n)

→

R(n-1),

R(0)

→

C, C

→

R(7)

0 0110 10rr

rrrr 06rr

RLCA R

R(n)

→

A(n+1),

R(7)

→

C, C

→

A(0)

0 0110 11rr

rrrr 06rr

RLC R

R(n)

→

R(n+1),

R(7)

→

(C), C

→

(R(0)

0 0111 00rr

rrrr 07rr

SWAPA R

R(0-3)

→

( A(4-7),

R(4-7)

→

( A(0-3)

None

0 0111 01rr

rrrr 07rr

SWAP

R(0-3)

→

( R(4-7)

None

0 0111 10rr

rrrr 07rr

JZA R

R+1

→

A, skip if zero

None

0 0111 11rr

rrrr 07rr

R+1

→

R, skip if zero

None

0 100b bbrr rrrr

0xxx BC

R, b 0

→

( R(b)

None

0 101b bbrr rrrr

0xxx BS

R, b 1

→

( R(b)

None

0 110b bbrr rrrr

0xxx JBC

R, b if

R(b)=0,

skip

None

0 111b bbrr rrrr

0xxx JBS

R, b if

R(b)=1,

skip

None

1 00kk kkkk

kkkk 1kkk

CALL k

PC+1

→

[SP],

(Page, k)

→

(PC)

None

1 01kk

kkkk

kkkk 1kkk

JMP k

(Page,

→

(PC)

None

1 1000

kkkk

kkkk 18kk

MOV A, k

→

None

1001

kkkk kkkk

19kk

A, k

A v k

→

1 1010

kkkk

kkkk 1Akk

AND A, k

→

1 1011

kkkk

kkkk 1Bkk

XOR A, k

⊕

→

1 1100

kkkk

kkkk 1Ckk

RETL k

→

A, [Top of Stack]

→

None

1 1101

kkkk

kkkk 1Dkk

SUB A, k

k-A

→

Z,C,DC

1 1111

kkkk

kkkk 1Fkk

ADD A, k

k+A

→

Z,C,DC

1 1110 1000

kkkk 1E8k

PAGE k

K->R5(6:4)

None

1 1110 1001

kkkk 1E9k

BANK k

K->R4(7:6)

None

Note:

This instruction is applicable to IOC50~IOF0, IOC61~IOCE1.

Summary of Contents for MiEM78P468L

Page 1: ...EM78P468N L 8 Bit Microcontroller Product Specification DOC VERSION 1 5 ELAN MICROELECTRONICS CORP February 2007...

Page 2: ...ication is furnished under a license or nondisclosure agreement and may be used or copied only in accordance with the terms of such agreement ELAN Microelectronics products are not intended for use in...

Page 3: ...1 14 RD SBPCR System Booster and PLL Control Register 12 6 1 15 RE IRCR IR and Port 5 Setting Control Register 13 6 1 16 RF ISR Interrupt Status Register 14 6 1 17 Address 10h 3Fh R10 R3F General Purp...

Page 4: ...6 2 Phase Lock Loop PLL Mode 30 6 6 3 Crystal Oscillator Ceramic Resonators Crystal 31 6 6 4 RC Oscillator Mode with Internal Capacitor 32 6 7 Power on Considerations 32 6 7 1 External Power on Reset...

Page 5: ...s Temperature 2 Removed the LVD function 2004 12 09 1 2 1 Added LQFP Package 2005 03 15 1 3 1 Combined EM78P468N with EM78P468L Specification 2 Deleted the wake up function from Idle mode by TCC time...

Page 6: ...Contents vi Product Specification V1 5 01 15 2007...

Page 7: ...ional tri state I O ports Operating Voltage and Temperature Range EM78P468N Commercial 2 3V 5 5 V at 0 C 70 C Industrial 2 5V 5 5 V at 40 C 85 C EM78P468L Commercial 2 1 V 5 5 V at 0 C 70 C Industrial...

Page 8: ...25 P8 1 SEG26 P8 2 P6 7 54 55 56 57 58 59 60 61 62 63 64 30 29 28 27 26 25 24 23 22 21 20 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 SEG28 P8 4 SEG27 P8 3 SEG11 1 2 1 3 1 4 1 5 1 6 31 32 3 3 3 4 3 5 3 6 3 7 3 8...

Page 9: ...agram ROM R3 Status Reg ACC Instruction Decoder Instruction Register ALU PC Interrupt Circuit 8 level stack 13 bit Interrupt Control Register Oscillation Generation RAM Mux R4 RC Crystal WDT PWM1 IR T...

Page 10: ...e pin status changes COM3 0 17 20 O LCD common output pin SEG0 SEG15 16 1 O LCD segment output pin SEG16 P7 0 SEG23 P7 7 64 57 O I O LCD segment output pin Can be shared with general purpose I O pin S...

Page 11: ...des when the pin status changes COM3 0 6 9 O LCD common output pin SEG11 SEG14 5 2 O LCD segment output pin SEG16 P7 0 SEG17 P7 1 SEG23 P7 7 1 44 38 O I O LCD segment output pin Can be shared with gen...

Page 12: ...uration structure generates 4K 13 bits on chip ROM addresses to the relative programming instruction codes The contents of R2 are all set to 0 s when a Reset condition occurs JMP instruction allows di...

Page 13: ...er PORT5 Port 5 IOCPAGE Control PORT6 Port6 I O data register PORT7 Port7 I O data register PORT8 Port8 I O data register LCDCR LCD control register LCD_ADDR LCD address LCD_DB LCD data buffer CNTER C...

Page 14: ...am counter to be changed e g MOV R2 A PS0 PS1 are loaded into the 11th and 12th bits of the program counter where it selects one of the available program memory pages Note that RET RETL RETI instructi...

Page 15: ...of Register Select Address 05h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R57 R56 R55 R54 IOCPAGE Bits 7 4 4 bits I O registers of Port 5 User can use the IOC50 register to define each bit either...

Page 16: ...CD bias select bit BS 0 1 2 bias BS 1 1 3 bias Bit 6 5 DS1 DS0 LCD duty select DS1 DS0 LCD Duty 0 0 1 2 duty 0 1 1 3 duty 1 1 4 duty Bit 4 LCDEN LCD enable bit LCDEN 0 LCD circuit disabled All common...

Page 17: ...30 1FH SEG31 Common COM3 COM2 COM1 COM0 6 1 12 RB LCD_DB LCD Data Buffer Address 0Bh Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCD_D3 LCD_D2 LCD_D1 LCD_D0 Bits 7 4 Not used Bits 3 0 LCD_D3 LCD_D...

Page 18: ...PLL mode code option select CLK2 CLK1 CLK0 Main clock Example Fs 32 768K 0 0 0 Fs 130 4 26 MHz 0 0 1 Fs 65 2 13 MHz 0 1 0 Fs 65 2 1 065 MHz 0 1 1 Fs 65 4 532 kHz 1 Fs 244 8 MHz Bit 3 IDLE Idle mode e...

Page 19: ...h Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 IRE HF LGP IROUTE TCCE EINT1 EINT0 Bit 7 IRE Infrared Remote Enable bit IRE 0 Disable the IR PWM function The state of P5 7 IROUT pin is determined by...

Page 20: ...rectional general I O pin EINT0 1 for external interrupt pin of INT0 the control bit of P5 4 Bit 4 of IOC50 must be set to 1 6 1 16 RF ISR Interrupt Status Register Address 0Fh Bit 7 Bit 6 Bit 5 Bit 4...

Page 21: ...5 x I O pin into high impedance input pin Bit 3 P8HS Switch to high nibble I O of Port 8 or to LCD segment output while sharing pins with SEGxx P8 x pins P8HS 0 select high nibble of Port 8 as normal...

Page 22: ...IOC7x 0 set the relative Port 7 x I O pins as output IOC7x 1 set the relative Port 7 x I O pin into high impedance input pin 6 2 5 IOC80 P8CR Port 8 I O Control Register Address 08h Bit 0 of R5 0 Bit...

Page 23: ...wn count timer with 8 bit prescaler used to preset the counter and read the preset value The prescaler is set by IOC91 register After an interrupt it will reload the preset value When IR output is ena...

Page 24: ...ister is set as low pulse width If the low pulse width timer clock source is FT then Low pulse time T F 1 value _ preset prescaler 6 2 12 IOCF0 IMR Interrupt Mask Register Address 0Fh Bit 0 of R5 0 Bi...

Page 25: ...Bit 3 Bit 2 Bit 1 Bit 0 INT_EDGE INT TS TE PSRE TCCP2 TCCP1 TCCP0 Bit 7 INT_EDGE INT_EDGE 0 Interrupt on the rising edge of P5 4 INT0 pin INT_EDGE 1 Interrupt on the falling edge of P5 4 INT0 pin Bit...

Page 26: ...WDTP0 Watchdog Timer prescaler bits The WDT clock source is sub oscillation frequency WDTP2 WDTP1 WDTP0 WDT Rate 0 0 0 1 1 0 0 1 1 2 0 1 0 1 4 0 1 1 1 8 1 0 0 1 16 1 0 1 1 32 1 1 0 1 64 1 1 1 1 128 6...

Page 27: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LPWTS LPWTP2 LPWTP1 LPWTP0 HPWTS HPWTP2 HPWTP1 HPWTP0 Bit 7 LPWTS low pulse width timer clock source select 0 1 Fs Fm Fs sub oscillator clock Fm main oscillator...

Page 28: ...63 OP62 OP61 OP60 Bit 7 Bit 0 The enable bits of Port 6 open drain function OD6x 0 disable pin of P6 x open drain function OD6x 1 enable pin of P6 x open drain function 6 2 20 IOCD1 P8PH Port 8 Pull H...

Page 29: ...he TCC signal source is from the internal instruction clock the TCC will be incremented by 1 at every instruction cycle without prescaler If the TCC signal source is from an external clock input the T...

Page 30: ...CC Setting Flowchart from External Input START TCC clock source External instruction cycle set clock source from external TCC pin set bit 4 of IOC71 to 1 set P5 6 TCC for TCC input Pin set bit 2 of RE...

Page 31: ...registers are both readable and writable The I O interface circuits are shown in Fig 6 5 Note Open drain pull high and pull down are not shown in the figure Fig 6 5 The Circuit of I O Port and I O Co...

Page 32: ...0 0 0 0 0x09 IOC90 RAM_ADDR Wake up from Pin Change P P P P P P P P Bit Name RAM_D7 RAM_D6 RAM_D5 RAM_D4 RAM_D3 RAM_D2 RAM_D1 RAM_D0 Power on U U U U U U U U RESET WDT P P P P P P P P 0x0A IOCA0 RAM_...

Page 33: ...7 OP66 OP65 OP64 OP63 OP62 OP61 OP60 Power on 0 0 0 0 0 0 0 0 RESET WDT 0 0 0 0 0 0 0 0 0x0C IOCC1 P6OD Wake up from Pin Change P P P P P P P P Bit Name PH87 PH86 PH85 PH84 PH83 PH82 PH81 PH80 Power o...

Page 34: ...0 0 0 0 RESET WDT 0 0 0 0 0 0 0 0 0xA RA LCD_ADDR Wake up from Pin Change P P P P P P P P Bit Name X X X X LCD_D 3 LCD_D 2 LCD_D 1 LCD_D 0 Power on U U U U U U U U RESET WDT U U U U P P P P 0xB RB LCD...

Page 35: ...1 Wake up interrupt next instruction Wake up interrupt next instruction Interrupt Interrupt Counter 1 IOCF0 Bit 3 1 Wake up interrupt next instruction Interrupt Interrupt Counter 2 IOCF0 Bit 4 1 Wake...

Page 36: ...rated in Crystal mode and ERIC mode Table 3 below shows how these three modes are defined Table 3 Oscillator Modes as defined by FSMD FMMD1 FMMD0 FSMD FMMD1 FMMD0 Main Clock Sub clock 0 0 0 RC type ER...

Page 37: ...generate oscillation Fig 6 8 depicts such circuit Table 5 provides the recommended values of C1 and C2 Since each resonator has its own attribute user should refer to its specification for appropriate...

Page 38: ...sc 5V 25 C Average Fosc 3V 25 C 51k 2 2221 MHz 2 1972 MHz 100k 1 1345 MHz 1 1203 MHz R OSCI 300k 381 36kHz 374 77kHz Xin 2 2M 32 768kHz 32 768kHz Note Measured from QFP packages with frequency drift o...

Page 39: ...r than 40K In this way the voltage at Pin RESET is held below 0 2V The diode D acts as a short circuit at power down The capacitor C is discharged rapidly and fully Rin the current limited resistor pr...

Page 40: ...terrupt request in flag bit IOCF0 is the interrupt mask register Global interrupt is enabled by ENI instruction and disabled by DISI instruction When one of the interrupts when enabled is generated it...

Page 41: ...de The LCD duty bias the number of segment the number of common and frame frequency are determined by the LCD controller register The basic structure contains a timing control that uses a subsystem cl...

Page 42: ...1 Fs 280 2 58 5 Fs 188 3 58 0 Fs 140 4 58 5 1 0 Fs 304 2 53 9 Fs 204 3 53 5 Fs 152 4 53 9 1 1 Fs 232 2 70 6 Fs 156 3 70 0 Fs 116 4 70 6 Note Fs sub oscillator frequency 6 9 2 RA LCD_ADDR LCD Address B...

Page 43: ...ster Frequency 0 0 Fs 0 1 Fs 4 1 0 Fs 8 1 1 Fs 16 The initial setting flowchart for LCD function IC RESET occur Set Port 7 snd Port 8 for general I O or LCD segment IOC50 it must be set to output port...

Page 44: ...cification is subject to change without further notice Boosting circuits connection for LCD voltage VDD VLCD2 2 VDD 3 VLCD3 1 VDD 3 GND VA VB External circuit for 1 3 Bias VDD VLCD2 VDD 2 VLCD3 VDD 2...

Page 45: ...D VDD VDD VLCD2 3 GND VLCD2 3 VDD SEG N COM1 ON OFF 1 2 bias 1 2 duty B type VLCD2 3 VLCD2 3 VLCD2 3 VLCD2 3 Fig 6 16 LCD Waveform for 1 2 Bias 1 2 Duty 1frame COM0 COM1 COM2 SEG N SEG N COM0 VDD GND...

Page 46: ...VDD VLCD2 VLCD3 GND VDD VLCD2 VLCD3 GND VDD VLCD3 GND VLCD3 VDD SEG N COM1 ON OFF 1 3 bias 1 3 duty B type VDD VLCD3 GND VLCD3 VDD Fig 6 18 LCD Waveform for 1 3 Bias 1 3 Duty 1frame COM0 COM1 COM2 SEG...

Page 47: ...Details on Fcarrier high pulse time and low pulse time are explained as follows If Counter 2 clock source is FT this clock source can be set by IOC91 then prescaler IOCC value preset ounter of decima...

Page 48: ...utput waveform of IROUT will keep on transmitting until high pulse width timer interrupt occurs Fig 6 24 LGP 0 HF 0 the IROUT waveform can not modulate Fcarrier waveform when in low pulse width time S...

Page 49: ...width low pulse width IR disable Always high level Fig 6 23 LGP 0 IROUT Pin Output Waveform Fcarrier low pulse width high pulse width IROUT start HF IRE high pulse width low pulse width IR disable Alw...

Page 50: ...0 preset value Enable IR RE HF 1 and IRE 1 Enable Counter 2 High pulse width timer and Low pulse width timer RC SET High pulse width timer Low pulse width timer clock source and prescaler IOCA1 Enable...

Page 51: ...S HLFS ENWDTB FSMD FMMD1 FMMD0 HLP PR2 PR1 PR0 Bits 12 10 Not used These bits are set to 1 all the time Bit 9 CYES Cycle select for JMP and CALL instructions CYES 0 only one instruction cycle JMP or C...

Page 52: ...ne single instruction cycle one instruction consists of 2 oscillator periods unless the program counter is changed by instruction MOV R2 A ADD R2 A or by instructions of arithmetic or logic operation...

Page 53: ...Interrupt None 0 0000 0001 0010 0012 RET Top of Stack PC None 0 0000 0001 0011 0013 RETI Top of Stack PC Enable Interrupt None 0 0000 0001 rrrr 001r IOR R IOCR A None 1 0 0000 01rr rrrr 00rr MOV R A...

Page 54: ...e 0 0111 11rr rrrr 07rr JZ R R 1 R skip if zero None 0 100b bbrr rrrr 0xxx BC R b 0 R b None 0 101b bbrr rrrr 0xxx BS R b 1 R b None 0 110b bbrr rrrr 0xxx JBC R b if R b 0 skip None 0 111b bbrr rrrr 0...

Page 55: ...am RESET Timing CLK 0 CLK RESET NOP Instruction 1 Executed Tdrh TCC Input Timing CLKS 0 CLK TCC Ttcc Tins AC Testing Input is driven at 2 4V for logic 1 and 0 4V for logic 0 Timing measurements are ma...

Page 56: ...otice 7 Absolute Maximum Ratings Rating Items Symbol Condition Min Max Unit Supply voltage VDD GND 0 3 7 0 V Input voltage VI Port 5 Port 8 GND 0 3 VDD 0 3 V Output voltage VO Port 5 Port 8 GND 0 3 VD...

Page 57: ...d Voltage Schmitt Trigger RESET 0 8 V VIHT2 Input High Threshold Voltage Schmitt Trigger TCC INT0 INT1 2 4 V VILT2 Input Low Threshold Voltage Schmitt Trigger TCC INT0 INT1 0 8 V IOH1 Output High Volt...

Page 58: ...Low Threshold Voltage Schmitt Trigger RESET 0 6 V VIHT2 Input High Threshold Voltage Schmitt Trigger TCC INT0 INT1 1 8 V VILT2 Input Low Threshold Voltage Schmitt Trigger TCC INT0 INT1 0 6 V IOH1 Out...

Page 59: ...Typ Max Unit Dclk Input CLK duty cycle 45 50 55 Crystal type 100 DC ns Tins Instruction cycle time CLKS 0 RC type 500 DC ns Ttcc TCC input period Tins 20 N ns Tdrh Device reset hold time Ta 25 C 11 3...

Page 60: ...accuracy In some graphs the data may be out of the specified warranted operating range Vih Vil RESET pins with schmitt inverter 0 0 5 1 1 5 2 2 5 2 2 5 3 3 5 4 4 5 5 5 5 Vdd Volt Vih Vil Volt Vih Max...

Page 61: ...5 3 3 5 4 4 5 5 5 5 Vdd Volt Vih Vil Volt Vih Max 40 to 85 Vih Typ 25 Vih Min 40 to 85 Vil Max 40 to 85 Vil Typ 25 Vil Min 40 to 85 Fig 8 3 Vih Vil of Port 7 and Port 8 vs VDD P5 7 Voh Ioh VDD 5V IROC...

Page 62: ...5 Min 85 P5 7 Voh Ioh VDD 3V IROCS 1 18 16 14 12 10 8 6 4 2 0 0 0 5 1 1 5 2 2 5 3 Voh Volt Ioh mA Typ 25 Min 85 Max 40 Fig 8 5 Port 5 7 Voh vs Ioh VDD 3V 5V IROCS Bit 7 of IOC61 1 P5 4 6 PORT 6 8 Voh...

Page 63: ...85 P5 7 Voh Ioh VDD 3V IROCS 0 0 5 10 15 20 25 30 35 0 0 5 1 1 5 2 2 5 3 Voh Volt Ioh mA Min 85 Typ 25 Max 40 Fig 8 7 Port 5 7 Vol vs Iol VDD 3V 5V IROCS Bit 7 of IOC61 0 P5 7 Voh Ioh VDD 5V IROCS 1 0...

Page 64: ...30 40 50 60 70 80 90 0 1 2 3 4 5 Voh Volt Ioh mA Min 85 Typ 25 Max 40 P5 4 5 6 PORT 6 7 8 Voh Ioh VDD 3V 0 5 10 15 20 25 30 35 40 0 0 5 1 1 5 2 2 5 3 Voh Volt Ioh mA Typ 25 Min 85 Max 40 Fig 8 9 Port...

Page 65: ...C Frequency R OSCI Pin 0 0 3 0 6 0 9 1 2 1 5 1 8 2 1 2 4 2 2 5 3 3 5 4 4 5 5 5 5 VDD Volt Frequency M Hz R 51 K R 100 K R 300 K Typical RC OSC Frequency Xin Pin 30 31 32 33 34 35 2 2 5 3 3 5 4 4 5 5 5...

Page 66: ...ions or modes for the Operating Current ICC1 to ICC4 These conditions are as follows ISB Sleep Mode Fm and Fs is stop all function are off ICC1 Idle Mode Fm Stop and Fs 32kHz two clocks CPU off LCD en...

Page 67: ...ical ICC3 vs Temerature 0 0 4 0 8 1 2 1 6 2 40 20 0 25 50 70 85 Temperature Current mA VDD 5V VDD 3V Fig 8 14 Typical Power Consumption on Normal Mode Operation Fm 4MHz Maximum ICC3 vs Temerature 0 0...

Page 68: ...er notice Typical ICC2 vs Temerature 0 5 10 15 20 25 30 40 20 0 25 50 70 85 Temperature Current uA VDD 5V VDD 3V Fig 8 16 Typical Power Consumption on Green Mode Operation Maximum ICC2 vs Temerature 0...

Page 69: ...t further notice Typical ICC1 vs Temerature 0 5 10 15 20 40 20 0 25 50 70 85 Temperature Current uA VDD 5V VDD 3V Fig 8 18 Typical Power Consumption on Idle Mode Operation Maximum ICC1 vs Temerature 0...

Page 70: ...ther notice Typical ISB vs Temerature 0 0 2 0 4 0 6 0 8 1 40 20 0 25 50 70 85 Temperature Current uA VDD 5V VDD 3V Fig 8 20 Typical Power Consumption on Sleep Mode Operation Maximun ISB vs Temerature...

Page 71: ...er Product Specification V1 5 02 15 2007 65 This specification is subject to change without further notice Fig 8 22 Operating Voltage under Temperature Range of 0 C to 70 C Fig 8 23 Operating Voltage...

Page 72: ...PANEL COM0 COM3 SEG0 SEG31 5 1 6 2 7 3 8 4 D 9 E A F B G C P6 0 P6 1 P6 2 P6 3 P6 4 P6 5 P6 6 P6 7 VDD IROUT EM78P468N Fig 9 1 IROUT Control External BJT Circuit to Drive Infrared Emitting Diodes LCD...

Page 73: ...QS NAQJ LQFP 64 7 mm 7 mm EM78P468NBQ LQFP 44 10 mm 10 mm EM78P468NBQS NBQJ LQFP 44 10 mm 10 mm EM78P468NCQ QFP 44 10 mm 10 mm EM78P468NCQS NCQJ QFP 44 10 mm 10 mm Note Green products do not contain h...

Page 74: ...ckage Information QFP 64 TITLE QFP 64 L 14 20 MM FOOTPRINT 5 0mm PACKAGE OUTLINE DIMENSION Unit mm Scale Free File QFP 64L Material Edtion A Sheet 1 of 1 A1 Symbal Min Normal Max A 3 40 A1 0 25 A2 2 5...

Page 75: ...in Normal Max A 1 60 A1 0 05 0 15 A2 1 35 1 40 1 45 D 8 90 9 00 9 10 D1 6 90 7 00 7 10 E 8 90 9 00 9 10 E1 6 900 7 00 7 100 e c 0 09 0 20 c1 0 09 0 16 b 0 13 0 18 0 23 b1 0 13 0 16 0 19 L 0 45 0 60 0...

Page 76: ...hout further notice QFP 44 TITLE QFP 44L 10 10 MM FOOTPRINT 3 2mm PACKAGE OUTLINE DIMENSION Unit mm Scale Free File QFP44 Material Edtion A Sheet 1 of 1 c Symbal A A1 A2 b c E1 E L L1 e Min Normal Max...

Page 77: ...DWRT is used to program the EM78P468N L IC s The connector of DWTR are select by CON4 EM78P451 and the software is selected by EM78P468N L Program Pin Name IC Pin Name L QFP 64 Pin Number L QFP 44 Pi...

Page 78: ...llator Crystal mode Suboscillator Mainoscillator GND GND R OSCI OSCO GND GND Xin Xout Xin R OSCI VDD VDD Crystal Crystal JP5 Mode 2 Main oscillator PLL mode Sub oscillator Crystal mode Suboscillator M...

Page 79: ...de Suboscillator Mainoscillator GND GND R OSCI OSCO GND GND Xin Xout Xin R OSCI VDD VDD Crystal RC JP5 Mode 5 Main oscillator PLL mode Sub oscillator RC mode Suboscillator Mainoscillator GND GND R OSC...

Page 80: ...14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 VLCD2 RESET R OSCI VDD Xout P5 5 INT1 SEG30 P8 6 P5 7 IROUT P6 1 P6 3 P6 5 P6 7 SEG28 P8 4 SEG26 P8 2 SEG24 P8 0 SEG22 P7 6 SEG2...

Page 81: ...100 pressure 2 atm TD endurance 96 hrs High temperature High humidity test TA 85 C RH 85 TD endurance 168 500 hrs High temperature storage life TA 150 C TD endurance 500 1000 hrs High temperature oper...

Page 82: ...ion33 6 8 Interrupt 34 6 9 LCD Driver 35 6 9 1 R9 LCDCR LCD Control Register 35 6 9 2 RA LCD_ADDR LCD Address 36 6 9 3 RB LCD_DB LCD Data Buffer 36 6 9 4 RD SBPCR System Booster and PLL Control Regist...

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