IBM JAGUAR V 386 System Manual Download | Manualshive

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TECHNICAL INFORMATION
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I/O Channel (C-Side)

I/O Pin

Signal Name

I/O

C1

SBHE

I/O

C2

LA23

I/O

C3

LA22

I/O

C4

LA21

I/O

C5

LA20

I/O

C6

LA19

I/O

C7

LA18

I/O

C8

LA17

I/O

C9

-MEMR

I/O

C10

-MEMW

I/O

C11

SD8

I/O

C12

SD9

I/O

C13

SD10

I/O

C14

SD11

I/O

C15

SD12

I/O

C16

SD13

I/O

C17

SD14

I/O

C18

SD15

I/O

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Summary of Contents for JAGUAR V 386

Page 1: ...JAGUAR V 386 System Manual ...

Page 2: ... this manual is for information only and is subject to change without notice REVISION 1 0 IBM IBM PC XT AT PC DOS MS DOS OS 2 INTEL WEITEK PHOENIX ARE THE TRADEMARKS OR REGISTERED TRADEMARKS OF THEIR RESPECTIVE OWNERS ...

Page 3: ...the receiver Move the computer away from the receiver Plug the power cord of computer into a different outlet so that computer and receiver are on different branch circuits Ensure that card slot covers are in place when no card is installed Ensure that card mounting screws attachment connector screws and ground wires are tightly secured If peripherals are used with this system it is suggested to u...

Page 4: ...er make sure that all the connectors memory modules and add on cards are secured 3 After power is on please wait for a minute The system BIOS are going through a self test during this period and nothing is shown on the screen After the self test the system BIOS will initialize the display adaptor and show messages 4 The SIMM sockets are fragile device Do not force the SIMM modules into the sockets...

Page 5: ...ormation for hardware and software engineers In this manual there are 4 chapters Chapter 1 contains a brief introduction and specification of OCTEK JAGUAR V 386DX motherboard In the Chapter 2 the functions of OCTEK JAGUAR V 386DX are explained It also outlines many advanced features of the CPU and the system architecture Chapter 3 explains the installation of coprocessor DRAM modules and jumpers S...

Page 6: ...emory System 2 8 System Functions 2 10 Chapter 3 INSTALLING COMPONENTS 3 1 Installing Math Coprocessor 3 1 Installing RAM Modules 3 3 Installing External Battery 3 5 Configuration of Memory 3 6 DRAM Configuration 3 7 Control of System Speed 3 8 Reset CMOS Setup 3 8 Information System Board Jumper Setting 3 9 System Board Connectors 3 10 ...

Page 7: ...ck and CMOS 4 8 RAM CMOS RAM Address Map 4 9 Real Time Clock Information 4 10 System Expansion Bus 4 11 APPENDIX A OPERATION MAINTENANCE A 1 Static Electricity A 1 Keeping the System Cool A 1 Cleaning the Golden Finger A 2 Cleaning the Motherboard A 2 APPENDIX B TROUBLESHOOTING B 1 System Unstable B 1 Main Memory Error B 1 APPENDIX C SYSTEM BOARD LAYOUT C 1 ...

Page 8: ...be fetched by CPU from the high speed cache memory without wait state Furthermore access to the main memory is accelerated because the cache controller and the memory controller are integrated together and operate concurrently Thus the overhead of accessing the main memory is minimized Aimed at supporting advanced CAD CAM applications OCTEK JAGUAR V 386DX supports INTEL 80387 or compatible The tot...

Page 9: ...THIS PAGE IS INTENTIONALLY LEFT BLANK ...

Page 10: ...bo normal speed Software hardware selectable I O Slot Compatible to standard AT bus Two 8 bit and Four 16 bit slots Programmable AT bus speed Support back to back I O recovery option to allow slow peripheral device Cache Memory Built in 8KB Cache Memory 2 way set associative with copy back cache controller Two block of Non cacheable regions control ...

Page 11: ... Page mode with programmable wait state for different DRAM configuration System Support Functions 8 Channel DMA Direct Memory Access 16 level interrupt 3 programmable timers CMOS RAM for system configuration Real time clock with battery backup Other Features On board POWERGOOD generation External battery connector Hardware turbo switch Hardware reset switch ...

Page 12: ...rotected mode provides access to the sophisticated memory management paging and privilege capabilities of the processor Furthermore new mechanism allows switching between Real mode and Protected mode at high speed operation The Protected mode of 80386 is fully compatible with 80286 All privilege level and I O protection system are supported New system control instructions memory paging I O permiss...

Page 13: ..._____________________ processor control These instructions are used in protected mode New operation systems and software can make use of these instructions for their advanced features such as concurrent operation and virtual memory ...

Page 14: ...ating point operations which are actually utilized by applications must be accomplished through software routines To overcome this obstacle external Math coprocessor is necessary The Math coprocessor contains complex hardware and large data registers for floating point numeric operations 80387 is upward object code compatible from 80287 and 8087 but runs 6 to 11 times faster than 80287 used in AT ...

Page 15: ...ance system in terms of price and performance The frequently used data code instructions are kept in the high speed cache memory Therefore most of the memory operations are carried out in the cache memory instead of the slow speed main memory The cache controller of OCTEK JAGUAR V 386DX is integrated into the chipset which will simplify the system design and reduce the chip count Furthermore built...

Page 16: ...is needed in most write operations In a copy back cache system the amount of write operation to main memory is minimized The CPU writes the data to the cache memory if the data on the same location is already in the cache memory The main memory is not updated yet and the operation completes in a single cycle So it implies that writing to the same location need not initiate a main memory write oper...

Page 17: ...n run at full speed To enhance the system performance shadow RAM mode is supported In shadow RAM mode system BIOS and video BIOS contained in low speed memory such as EPROM and ROM are copied into DRAM Improvement is significant because access to DRAM is much faster than ROM Hidden Refresh In the original PC AT design the CPU suspends its operation during memory refresh The memory refresh cycle ta...

Page 18: ...ill not stop its operation and the memory refresh operation is transparent to the CPU access The chipset will monitor the whole system If the CPU is accessing the main memory the memory refresh operation is postponed and will be carried out when there is no access to main memory Special refresh mechanism is implemented to reduce the period of memory refresh operation ...

Page 19: ...r Real time clock Clock and ready generation I O channel control All system functions are 100 compatible to AT standard I O channel of OCTEK JAGUAR V 386DX is designed to be compatible with standard AT bus All the expansion cards conformed to the standard AT bus can be used in OCTEK JAGUAR V 386DX without problem ...

Page 20: ... installing or replacing any component INSTALLING MATH COPROCESSOR Math coprocessor 80387 is PGA device and it has 68 pins To install Math coprocessor be sure to line up pin 1 of the Math coprocessor with pin 1 of the socket as shown below Make sure that the coprocessor is firmly inserted into the socket ...

Page 21: ...ns are straight The pins are very fragile Once these pins are bent the coprocessor may be damaged Check whether the system BIOS can find the coprocessor after reset The system BIOS will display a list of devices on the motherboard after self test If the coprocessor is installed it should show the type of coprocessor ...

Page 22: ...ted into position where the locking latches will secure it If the module edge is not completely inserted into the socket it cannot be pivoted to be in vertical position and should be dragged out and inserted again Do not force the module into the SIMM socket It will damage the locking latches The modules should be locked by the locking latches of the sockets firmly Please check carefully before tu...

Page 23: ...INSTALLING COMPONENTS __________________________________ ...

Page 24: ... stored in CMOS RAM an external battery is needed to provide power after the system is turned off The connector P8 for the battery is located beside the keyboard connector on the rear of the board A 3 6V battery is used Turn off the power before install the battery The location of the connector P8 is shown below ...

Page 25: ...next page There are totally two banks of DRAM The memory size is detected automatically by system BIOS This detection is performed during memory test and the size is indicated after reset No jumper is needed to be set for the memory size and DRAM type To determine what DRAM speed rating to be used is depended on the system speed and wait state The highest performance is accomplished by using zero ...

Page 26: ...Improper setting may cause the system malfunction In this case reset the CMOS setup using JP3 Then reset the system and go through the system setup again DRAM CONFIGURATION Bank 1 SIMM 1 4 Bank 0 SIMM 5 8 Total Memory 1 X 256K 1M 2 256K 256K 2M 3 X 1M 4M 4 1M 256K 5M 5 1M 1M 8M 6 X 4M 16M 7 4M 1M 20M 8 4M 4M 32M ...

Page 27: ...t speed Whenever the system speed is set to slow by turbo switch it cannot be changed by keyboard and vice versa RESET CMOS SETUP INFORMATION Sometimes the improper setting of system setup may make the system malfunction In this case turn off the power and disconnect the external battery Then place a jumper on JP3 2 3 for a while The internal CMOS status register will be cleared Then remove the ju...

Page 28: ...ONENTS __________________________________ SYSTEM BOARD JUMPER SETTING There is a option which allow user to select by hardware switches Display Selection JP1 1 2 CGA EGA VGA 2 3 Monochrome Display Note factory setting ...

Page 29: ... the system unit Connector Function P1 Hardware reset connector P2 Speaker connector P3 Turbo switch connector P4 Turbo LED connector P5 Power LED Ext Lock connector P6 P7 Power supply connector P8 External battery connector KB1 Keyboard connector Pin assignments of the connectors are illustrated as follows P 1 Hardware Reset Connector Pin Assignment 1 Selection Pin 2 Ground ...

Page 30: ..._____________________________ P 2 Speaker Connector Pin Assignment 1 Data out 2 5 Vdc 3 Ground 4 5 Vdc P 3 Turbo Switch Connector Pin Assignment 1 Selection Pin 2 Ground P 4 Turbo LED Connector Pin Assignment 1 5 Vdc 2 LED signal ...

Page 31: ...5 Power LED Ext Lock Connector Pin Assignment 1 5 Vdc 2 Key 3 Ground 4 Keyboard inhibit 5 Ground P6 P7 Power Supply Connector Pin Assignment 1 POWERGOOD 2 5 Vdc 3 12 Vdc 4 12 Vdc 5 Ground 6 Ground Pin Assignment 1 Ground 2 Ground 3 5 Vdc 4 5 Vdc 5 5 Vdc 6 5 Vdc ...

Page 32: ...INSTALLING COMPONENTS __________________________________ ...

Page 33: ...NENTS __________________________________ P 8 External Battery Connector Pin Assignment 1 Vdc 2 not used 3 Ground 4 Ground KB 1 Keyboard Connector Pin Assignment 1 Keyboard clock 2 Keyboard data 3 Spare 4 Ground 5 5 Vdc ...

Page 34: ...INSTALLING COMPONENTS __________________________________ THIS PAGE IS INTENTIONALLY LEFT BLANK ...

Page 35: ...AR V 386DX MEMORY MAPPING Address Range Function 000000 7FFFFF 000K 512K System Board Memory 512K 080000 09FFFF 512K 640K System Board Memory 128K 0A0000 0BFFFF 640K 768K Display Buffer 128K 0C0000 0DFFFF 768K 896K Adaptor ROM Shadow RAM 128K 0E0000 0EFFFF 896K 960K System ROM Shadow RAM 64K 0F0000 0FFFFF 960K 1024K System BIOS ROM Shadow RAM 64K 100000 7FFFFF 1024K 8192K System Memory 800000 FFFF...

Page 36: ...S HEX DEVICE 000 01F DMA Controller 1 8237 020 03F Interrupt Controller 1 8259 Master 040 05F Timer 8254 060 06F Keyboard Controller 070 07F Real Time Clock NMI non maskable interrupt mask 080 09F DMA Page Register 74LS612 0A0 0BF Interrupt Controller 2 8259 0C0 0DF DMA Controller 2 8237 0F0 Clear Math Coprocessor Busy 0F1 Reset Math Coprocessor 0F8 0FF Math Coprocessor Port ...

Page 37: ...isk 200 207 Game I O 278 27F Parallel Printer Port 2 2F8 2FF Serial Port 2 300 31F Prototype Card 360 36F Reserved 378 37F Parallel Printer Port 1 380 38F SDLC bisynchronous 2 3A0 3AF Bisynchronous 1 3B0 3BF Monochrome Display and Printer Adapter 3C0 3CF Reserved 3D0 3DF Color Graphics Monitor Adapter 3F0 3F7 Diskette Controller 3F8 3FF Serial Port 1 ...

Page 38: ... has three programmable timer counters controlled by chipset and they are defined as channels 0 through 2 Channel 0 System Timer Gate 0 Tied on Clk in 0 1 190 Mhz OSC Clk out 0 8259 IRQ 0 Channel 1 Refresh Request Generator Gate 1 Tied on Clk in 1 1 190 Mhz OSC Clk out 1 Request Refresh Cycle ...

Page 39: ...PI bit Clk in 2 1 190 Mhz OSC Clk out 2 Used to drive the speaker Note Channel 1 is programmed to generate a 15 micro second period signal The 8254 Timer Counters are treated by system programs as an arrangement of four programmable external I O ports Three are treated as counters and the fourth is a control register for mode programming ...

Page 40: ...roprocessor NMI Parity or I O Channel Check Interrupt Controllers CTLR 1 CTLR 2 IRQ0 Timer Output 0 IRQ1 Keyboard Output Buffer Full IRQ2 Interrupt from CTLR 2 IRQ8 Real time Clock Interrupt IRQ9 Software Redirected to INT 0AH IRQ2 IRQ10 Reserved IRQ11 Reserved IRQ12 Reserved IRQ13 Coprocessor IRQ14 Fixed Disk Controller IRQ15 Reserved IRQ3 Serial Port 2 IRQ4 Serial Port 1 IRQ5 Parallel Port 2 IRQ...

Page 41: ...TECHNICAL INFORMATION __________________________________ ...

Page 42: ...CESS DMA OCTEK JAGUAR V 386DX supports seven DMA channels Channel Function 0 Spare 8 bit transfer 1 SDLC 8 bit transfer 2 Floppy Disk 8 bit transfer 3 Spare 8 bit transfer 4 Cascade for DMA Controller 1 5 Spare 16 bit transfer 6 Spare 16 bit transfer 7 Spare 16 bit transfer ...

Page 43: ...nel 2 0081 DMA Channel 3 0082 DMA Channel 5 008B DMA Channel 6 0089 DMA Channel 7 008A Refresh 008F REAL TIME CLOCK AND CMOS RAM Real time clock and CMOS RAM are contained on board Real time clock provides the system date and time CMOS RAM stores system information Both are backed up by battery and will not lose information after power off The following page shows the CMOS RAM Address Map ...

Page 44: ...drive type byte drives A and B 11 Reserved 12 Fixed disk type byte drives C and D 13 Reserved 14 Equipment byte 15 Low base memory byte 16 High base memory byte 17 Low expansion memory byte 18 High expansion memory byte 19 2D Reserved 2E 2F 2 byte CMOS checksum 30 Low expansion memory byte 31 High expansion memory byte 32 Date century byte 33 Information flags set during power on 34 3F Reserved ...

Page 45: ... real time clock bytes and specifies their addresses Byte Function Address 0 Seconds 00 1 Second alarm 01 2 Minutes 02 3 Minute alarm 03 4 Hours 04 5 Hour alarm 05 6 Day of week 06 7 Date of month 07 8 Month 08 9 Year 09 10 Status Register A 0A 11 Status Register B 0B 12 Status Register C 0C 13 Status Register D 0D ...

Page 46: ...M EXPANSION BUS OCTEK JAGUAR V 386DX provides four 16 bit and two 8 bit slots The I O channel supports I O address space from hex 100 to hex 3FF Selection of data access either 8 or 16 bit 24 bit memory addresses 16MB Interrupts DMA channels Memory refresh signal ...

Page 47: ...TECHNICAL INFORMATION __________________________________ The following figure shows the pin numbering for I O channel connectors JA1 to JA6 ...

Page 48: ...TECHNICAL INFORMATION __________________________________ The following figure shows the pin numbering for I O channel connectors JB2 JB5 ...

Page 49: ... Side I O Pin Signal Name I O A1 I O CH CK I A2 SD7 I O A3 SD6 I O A4 SD5 I O A5 SD4 I O A6 SD3 I O A7 SD2 I O A8 SD1 I O A9 SD0 I O A10 I O CH RDY I A11 AEN O A12 SA19 I O A13 SA18 I O A14 SA17 I O A15 SA16 I O A16 SA15 I O A17 SA14 I O A18 SA13 I O A19 SA12 I O A20 SA11 I O A21 SA10 I O A22 SA9 I O A23 SA8 I O A24 SA7 I O A25 SA6 I O A26 SA5 I O ...

Page 50: ...TECHNICAL INFORMATION __________________________________ A27 SA4 I O A28 SA3 I O A29 SA2 I O A30 SA1 I O A31 SA0 I O ...

Page 51: ... B3 5 Vdc Power B4 IRQ9 I B5 5 Vdc Power B6 DRQ2 I B7 12 Vdc Power B8 0WS I B9 12 Vdc Power B10 GND Ground B11 SMEMW O B12 SMEMR O B13 IOW I O B14 IOR I O B15 DACK3 I B16 DRQ3 O B17 DACK1 I B18 DRQ1 O B19 Refresh I O B20 CLK O B21 IRQ7 I B22 IRQ6 I B23 IRQ5 I B24 IRQ4 I B25 IRQ3 I B26 DACK2 O B27 T C O B28 BALE O B29 5 Vdc Power ...

Page 52: ...TECHNICAL INFORMATION __________________________________ B30 OSC O B31 GND Ground ...

Page 53: ... Channel C Side I O Pin Signal Name I O C1 SBHE I O C2 LA23 I O C3 LA22 I O C4 LA21 I O C5 LA20 I O C6 LA19 I O C7 LA18 I O C8 LA17 I O C9 MEMR I O C10 MEMW I O C11 SD8 I O C12 SD9 I O C13 SD10 I O C14 SD11 I O C15 SD12 I O C16 SD13 I O C17 SD14 I O C18 SD15 I O ...

Page 54: ...I O Channel D Side I O Pin Signal Name I O D1 MEM CS16 I D2 I O CS16 I D3 IRQ10 I D4 IRQ11 I D5 IRQ12 I D6 IRQ15 I D7 IRQ14 I D8 DACK0 O D9 DRQ0 I D10 DACK5 O D11 DRQ5 I D12 DACK6 O D13 DRQ6 I D14 DACK7 O D15 DRQ7 I D16 5 Vdc Power D17 MASTER I D18 GND Ground ...

Page 55: ...TECHNICAL INFORMATION __________________________________ THIS PAGE IS INTENTIONALLY LEFT BLANK ...

Page 56: ...r Hold the cards by their edges KEEPING THE SYSTEM COOL The motherboard contains many high speed components and they will generate heat during operation Other add on cards and hard disk drive can also produce a lot of heat The temperature inside the computer system may be very high In order to keep the system running stably the temperature must be kept at a low level A easy way to do this is to ke...

Page 57: ...card may not work properly Use a pencil eraser to clean the golden finger if dirt is found CLEANING THE MOTHERBOARD The computer system should be kept clean Dust and dirt is harmful to electronic devices To prevent dust from accumulating on the mother board installing all mounting plates on the rear of the case Regularly examine your system and if necessary vacuum the interior of the system with a...

Page 58: ... the number of wait state MAIN MEMORY ERROR After power up the monitor remains blank and there are beep sounds indicating a main memory failure In this case turn off the power and remove all SIMM modules Carefully place the modules back to the sockets and make sure that all the modules are locked by the locking latches firmly In some other cases the total memory found by the BIOS is different from...

Page 59: ...THIS PAGE IS INTENTIONALLY LEFT BLANK ...

Page 60: ...Appendix C System Board Layout _______________________________ ...

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