IBM JAGUAR V 386, System Manual

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GENERAL FEATURES
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CACHE MEMORY
The system performance can not simply be
improved by increasing the clock rate of the system.
The performance depends on many factors, such as
system architecture and memory configuration.
A cache memory system with low cost DRAM as
main memory and high speed SRAM as cache memory
becomes the only choice for high performance system in
terms of price and performance. The frequently used
data code instructions are kept in the high speed cache
memory. Therefore, most of the memory operations are
carried out in the cache memory instead of the slow
speed main memory.
The cache controller of OCTEK JAGUAR V-386DX
is integrated into the chipset, which will simplify the
system design and reduce the chip count. Furthermore,
built-in 8KB SRAM as unified cache support up to 16MB
byte cacheable memory. In this cacheable range, it is
integrated two non-cacheable area which flexible for
different system configuration.