IBM eServer OpenPower 720, Technical Overview And Introduction

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OpenPower 720 Technical Overview and Introduction
next cycle. This allows substantial power saving with no performance impact. In every cycle,
the dynamic power management logic determines whether a local clock buffer that drives a
set of latches can be clock gated in the next cycle.
In addition to the switching power, leakage power has become a performance limiter. To
reduce leakage power, the POWER5 chip uses transistors with low threshold voltage only in
critical paths. The POWER5 chip also has a low-power mode, enabled when the system
software instructs the hardware to execute both threads at the lowest available priority. In low
power mode, instructions dispatch once every 32 cycles at most, further reducing switching
power. The POWER5 chip uses this mode only when there is no ready task to run on either
thread.
2.1.3 POWER chip evolution
The OpenPower system complies with the RS/6000 platform architecture, which is an
evolution of the PowerPC Common Hardware Reference Platform (CHRP) specifications.
Figure 2-3 shows the POWER evolution.
Figure 2-3 POWER chip evolution
2.1.4 CMOS, copper, and SOI technology
The POWER5 processor design is a result of a close collaboration between
IBM Systems and
Technology Group
and
IBM Microelectronics Technologies
that enables IBM
Sserver
OpenPower systems to give customers improved performance, reduced power
32bit
64bit
Note: Not all
processor speeds
available on all
m odels
PO W ER4
1.0 to 1.3
G Hz
PO W ER4+
1.2 to 1.9 G Hz
RS64-IV
600 / 750
pSeries p620, p660,
and p680
604e
332 /
375
p615, p630,
p650, p655, p670
and p690
Pow er3-II
333 / 375 /
450
M odels 270, B80, and
PO W ER3 SP Nodes
RS64
125
S70
RS64-II
262.5
S7A
RS64-II
340
H70
RS64-III
450
F80, H80, M 80, S80
Pow er3
200+
SP Nodes
+ SO I =
SO I
Copper =
F50
p630, p650, p655,
p670, and p690
1.2 to
1.9 GHz
Core
1.2 to
1.9 GHz
Core
Shared L2 Shared L2
Distributed Sw itch
0.13 microns
2002-3
– Larger L2
– More LPARs
– High-speed Switch
Shared L2
Distributed Switch
0.18 microns
2001
POWER4™
– Distributed Switch
– Shared L2
– LPAR
– Autonomic computing
– Chip multiprocessing
1.0 to
1.3 GHz
Core
1.0 to
1.3 GHz
Core
Shared L2 Shared L2
Distributed Switch
0.18 microns
2001
POWER4™
– Distributed Switch
– Shared L2
– LPAR
– Autonomic computing
– Chip multiprocessing
1.0 to
1.3 GHz
Core
1.0 to
1.3 GHz
Core
S h a r e d L 2
D i s t r i b u t e d S w i t c h
0 . 1 3 m i c r o n s
2 0 0 4
P O W E R 5
T M
– L a r g e r L 2 a n d L 3 c a c h e s
– M i c r o - p a r t i t i o n i n g
– E n h a n c e d D i s t r i b u t e d S w i t c h
– E n h a n c e d c o r e p a r a l l e l i s m
– I m p r o v e d f l o a t i n g - p o i n t
– p e r f o r m a n c e
– F a s t e r m e m o r y e n v i r o n m e n t
Me
m C
tl
1 . 5 t o
1 . 9 G H z
C o r e
1 . 5 t o
1 . 9 G H z
C o r e
S h a r e d L 2 S h a r e d L 2
D i s t r i b u t e d S w i t c h
0 . 1 3 m i c r o n s
2 0 0 4
P O W E R 5
T M
– L a r g e r L 2 a n d L 3 c a c h e s
– M i c r o - p a r t i t i o n i n g
– E n h a n c e d D i s t r i b u t e d S w i t c h
– E n h a n c e d c o r e p a r a l l e l i s m
– I m p r o v e d f l o a t i n g - p o i n t
– p e r f o r m a n c e
– F a s t e r m e m o r y e n v i r o n m e n t
Me
m C
tl
1 . 5 t o
1 . 9 G H z
C o r e
1 . 5 t o
1 . 9 G H z
C o r e