IBM DTTA-351010 - Deskstar 10.1 GB Hard Drive Specifications Download Page 77

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The register contains valid data only when D R Q = 1 in the Status Register.

9.6 Device Control Register

ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿

D e v i c e C o n t r o l R e g i s t e r

ÃÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄ´

³ Ä ³ Ä ³ Ä ³ Ä ³

S R S T

³Ä

I E N

ÀÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÙ

Figure 57. Device Control Register

Bit Definitions

SRST (RST)

Software Reset. The device is held reset when R S T = 1 .

Setting R S T = 0 re-enables

the device.

The host must set R S T = 1 and wait for at least 5 microseconds before setting
R S T = 0 , to ensure that the device recognizes the reset.

-IEN

Interrupt Enable. When - I E N = 0 , and the device is selected, device interrupts to the
host will be enabled. When - I E N = 1 , or the device is not selected, device interrupts
to the host will be disabled.

9.7 Drive Address Register

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D r i v e A d d r e s s R e g i s t e r

ÃÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄ´

H I Z

³Ä

W T G

³ Ä

H 3

³ Ä

H 2

³ Ä

H 1

³ Ä

H 0

³Ä

D S 1

³Ä

D S 0

ÀÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÙ

Figure 58. Drive Address Register

This register contains the inverted drive select and head select addresses of the currently selected drive.

Bit Definitions

HIZ

High Impedance. This bit is not drived and will always be in a high impedance state.

-WTG

-Write Gate. This bit is 0 when writing to the disk device is in progress.

-H3,-H2,-H1,-H0

-Head Select. These four bits are the one's complement of the binary coded address
of the currently selected head. -H0 is the least significant.

-DS1

-Drive Select 1.

Drive select bit for device 1, active low.

D S 1 = 0 when device 1

(slave) is selected and active.

-DS0

-Drive Select 0.

Drive select bit for device 0, active low.

D S 0 = 0 when device 0

(master) is selected and active.

9.8 Device/Head Register

Registers

Summary of Contents for DTTA-351010 - Deskstar 10.1 GB Hard Drive

Page 1: ...OEM HARD DISK DRIVE SPECIFICATIONS for DTTA 3xxxxx 16 8GB 3 2GB 3 5 Inch Hard Disk Drive with ATA Interface Revision 2 0 S00K 0286 02...

Page 2: ......

Page 3: ...OEM HARD DISK DRIVE SPECIFICATIONS for DTTA 3xxxxx 16 8GB 3 2GB 3 5 Inch Hard Disk Drive with ATA Interface Revision 2 0 S00K 0286 02...

Page 4: ...is publication may contain reference to or information about IBM products machines and programs programming or services that are not announced in your country Such references or infor mation must not...

Page 5: ...15 5 0 Physical Format 17 5 1 Shipped Format 17 6 0 Specification 19 6 1 Electrical interface specification 19 6 1 1 Connectors 19 6 1 2 Signal Definition 20 6 1 3 Interface Logic Signal Levels 23 6...

Page 6: ...C Tick Mark 58 6 12 Safety 59 6 12 1 Underwriters Lab UL Approval 59 6 12 2 Canadian Standards Authority CSA Approval 59 6 12 3 IEC Compliance 59 6 12 4 German Safety Mark 59 6 12 5 Flammability 59 6...

Page 7: ...ord 80 10 7 4 Operation example 81 10 7 5 Command Table 84 10 8 Protected Area Function 86 10 8 1 Example for operation In LBA mode 86 10 9 Write Cache Function 87 10 10 Reassign Function 87 10 10 1 A...

Page 8: ...Multiple C6h 145 12 30 Sleep E6h 99h 146 12 31 S M A R T Function Set B0h 147 12 31 2 Device Attributes Data Structure 150 12 31 3 Device Attribute Thresholds Data Structure 154 12 31 4 Error Reportin...

Page 9: ...pm Note The specifications are subject to change without notice 1 1 Glossary Word Meaning Kbpi 1 000 Bit Per Inch Mbps 1 000 000 Bit per second GB 1 000 000 000 bytes MB 1 000 000 bytes KB 1 000 bytes...

Page 10: ...2 OEM Specifications for DTTA 3xxxxx...

Page 11: ...bytes Write Cache Queued feature support On The Fly correction 12 Bytes Automatic Error Recovery procedures for read and write commands Self Diagnostics on Power on and resident diagnostics Data Trand...

Page 12: ...4 OEM Specifications for DTTA 3xxxxx...

Page 13: ...Part 1 Functional Specification Copyright IBM Corp 1998 5...

Page 14: ...6 OEM Specifications for DTTA 3xxxxx...

Page 15: ...s DTTA 351680 16 9 16383 16 15 63 33 022 080 16 907 304 960 DTTA 351350 13 5 16383 16 15 63 26 414 640 13 524 295 680 DTTA 351290 12 9 16383 16 15 63 25 385 472 12 997 361 664 DTTA 351010 10 1 16383 1...

Page 16: ...3 Ultra DMA 33 Data Buffer Size KB 464 464 Rotational Speed RPM 5400 7200 Average Latency msec 5 56 4 17 Recording Density Kbpi 196 1 max 178 1 max Track Density TPI 13 700 13 700 Areal Density Gb sq...

Page 17: ...ommand when the requested data is not in the buffer exclude Physical seek time Latency time Figure 3 Command Overhead Note The above table gives an average time 3 3 2 Mechanical Positioning 3 3 2 1 Av...

Page 18: ...nward measured seek time for a n track seek Tn out Outward measured seek time for a n track seek 3 3 2 2 Full Stroke Seek Without Command Overhead Including Settling Figure 5 Full Stroke Seek Time Ful...

Page 19: ...nd outward 3 3 2 6 Average Latency Figure 9 Latency Time 3 3 3 Drive Ready Time Figure 10 Drive Ready Time Ready The condition in which the drive is able to perform a media access command e g read wri...

Page 20: ...nder 512 B of Surface per cylinder 1 Head Switch Time C Cylinder Change Time D of Surface One Revolution Time Instantaneous Buffer Host Transfer Rate Mbyte sec defines the maximum data transfer rate o...

Page 21: ...ency sec D Sustained Disk Buffer Transfer Rate byte sec E Buffer Host Transfer Rate byte sec DRQ Data ReQuest interval sec 3 3 5 2 Random Access The above table gives the time required to execute a to...

Page 22: ...or hard reset can change the mode to standby Notes 1 Upon Power down or Spindle stopped a head locking mechanism will secure the heads in the ID parking position 3 3 6 1 Mode Transition Time Figure 13...

Page 23: ...ata in the write cache have been flushed onto the disk Checking just before power off is recommended to prevent data loss To confirm successful completion of Software Reset To confirm successful compl...

Page 24: ...16 OEM Specifications for DTTA 3xxxxx...

Page 25: ...r data areas All pushes generated by defects are absorbed by spare tracks of inner zone N N 1 N 2 N 3 Defect Defect A A Skip Skip Defects are skipped without any constraint such as track or cylinder b...

Page 26: ...18 OEM Specifications for DTTA 3xxxxx...

Page 27: ...mate with AMP part 1 480424 0 using AMP pins part 350078 4 strip or part 61173 4 loose piece or their equivalents Pin assignments are shown below Figure 14 Power Connector Pin Assignments 6 1 1 2 AT S...

Page 28: ...0 GND Figure 15 Table of signals Notes 1 O designates an output from the Drive 2 I designates an input to the Drive 3 I O designates an input output common 4 OC designates Open Collector or Open Drain...

Page 29: ...6 bit wide data word This signal is an Open Drain output with 24 mA sink capability and an external resistor is needed to pull this line to 5 volts DASP This is a time multiplexed signal which indicat...

Page 30: ...is a 3 state line with 24mA sink capability and internally pulled down to GND through 10 k resistor HDMARDY Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive HDMA...

Page 31: ...se an Ultra DMA data in transfer Note The termination resistors at the device side are implemented as follows Device Termination implemented on HDD side 33 ohm for DD0 thru DD15 DMARQ INTRQ 82 ohm for...

Page 32: ...6 2 1 Reset Timings HDD reset timing RESET T0 BUSY XXXXXXX T1 PARAMETER DESCRIPTION Min Max usec sec T0 RESET low width 25 T1 RESET high to not BUSY 31 Figure 17 System Reset timing 24 OEM Specificati...

Page 33: ...IOR DIOW active 25 T2 DIOR DIOW pulse width 70 T2I DIOR DIOW recovery 25 T3 DD00 15 setup to DIOW high 20 T4 DIOW high to DD00 15 hold 10 T5 DD00 15 setup to DIOR high 20 T6 DIOR high to DD00 15 hold...

Page 34: ...rs and read multiple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows In case that a host reads the status register only before the secto...

Page 35: ...TF READ DATA TG TH WRITE DATA nsec PARAMETER DESCRIPTION MIN MAX Note T0 Cycle time 240 TC DMACK active to DMARQ inactive 80 TD HIOR HIOW pulse width 120 TE HIOR data access 60 TF HIOR data hold 5 TG...

Page 36: ...DESCRIPTION MIN MAX Note T0 Cycle time 120 TD HIOR HIOW pulse width 70 TE HIOR data setup 20 TF HIOR data hold 5 TG HIOW data setup 20 TH HIOW data hold 10 TI DMACK to HIOR HIOW setup 0 TJ HIOR HIOW...

Page 37: ...evice drives DB nsec MODE0 MODE1 MODE2 PARAMETER DESCRIPTION MIN MAX MIN MAX MIN MAX Tui Unlimited interlock time 0 0 0 Tack Setup time before DMACK assertion 20 20 20 Tenv Envelope time 20 70 20 70 2...

Page 38: ...IPTION MIN MAX MIN MAX MIN MAX Tsr Strobe to ready response time 50 30 20 Trfs Ready to final strobe time 75 60 50 Note When a host does not meet Tsr it should be ready to receive 2 more strobes after...

Page 39: ...IN MAX Trfs Ready to final strobe time 75 60 50 Trp Ready to pause time 160 125 100 Tli Limited interlock time 0 150 0 150 0 150 Taz Output release time 10 10 10 Tzah Output enable time 20 20 20 Tmli...

Page 40: ...IN MAX Tss Time from strobe to stop assertion 50 50 50 Tli Limited interlock time 0 150 0 150 0 150 Taz Output release time 10 10 10 Tzah Output enable time 20 20 20 Tmli Interlock time 20 20 20 Tds D...

Page 41: ...ON MIN MAX MIN MAX MIN MAX Tui Unlimited interlock time 0 0 0 Tack Setup time before DMACK assertion 20 20 20 Tenv Envelope time 20 70 20 70 20 70 Tzrdy Wait time before driving DSTROBE 0 0 0 Tli Limi...

Page 42: ...IPTION MIN MAX MIN MAX MIN MAX Tsr Strobe to ready response time 50 30 20 Trfs Ready to final strobe time 75 60 50 Note When a device does not meet Tsr it shall be ready to receive 2 more strobes afte...

Page 43: ...N MIN MAX MIN MAX MIN MAX Trfs Ready to final strobe time 75 60 50 Trp Ready to pause time 160 125 100 Tli Limited interlock time 0 150 0 150 0 150 Tmli Interlock time 20 20 20 Tds Data setup time at...

Page 44: ...CRIPTION MIN MAX MIN MAX MIN MAX Tss Time from strobe to stop assertion 50 50 50 Tli Limited interlock time 0 150 0 150 0 150 Tmli Interlock time 20 20 20 Tds Data setup time at device side 15 10 7 Td...

Page 45: ...0 1 1 0 0 Cylinder low Reg Cylinder low Reg 0 1 1 0 1 Cylinder high Reg Cylinder high Reg 0 1 1 1 0 Drive Head Reg Drive Head Reg 0 1 1 1 1 Status Reg Command Reg Control Block Registers 1 0 1 1 0 Al...

Page 46: ...in Assignment Pin number A through I are prepared for jumper setting I G E C A H F D B Figure 30 Jumper Pin Assignment 6 3 3 Jumper Function Device 0 Device 1 Cable Select and Device 0 Forcing Device...

Page 47: ...D B Forcing DEVICE 1 PRESENT Figure 31 Jumper Block Setting Position Notes 1 All other setting patterns are reserved Do not make other setting 2 When CABLE SELECT is specified AT interface signal 28 C...

Page 48: ...ENT Figure 32 Jumper Block Setting Position Notes 1 All other setting patterns are reserved Do not make other setting 2 When CABLE SELECT is specified AT interface signal 28 CSEL is referred to determ...

Page 49: ...H F D B Figure 33 Jumper Block Setting Position Notes 1 All other setting patterns are reserved Do not make other setting 2 When CABLE SELECT is specified AT interface signal 28 CSEL is referred to de...

Page 50: ...ure 34 Jumper Block Setting Position Notes 1 All other setting patterns are reserved Do not make other setting 2 When CABLE SELECT is specified AT interface signal 28 CSEL is referred to determin the...

Page 51: ...de 300 to 3048 m Non Operating Conditions Temperature 40 to 65 C Relative Humidity 5 to 95 R H non condensing Maximum Wet Bulb Temperature 35 C non condensing Maximum Temperature Gradient 15 C Hour Al...

Page 52: ...5Volts 12Volts Total W Pop Mean Std Dev Pop Mean Std Dev Idle Average 0 29 0 02 0 45 0 1 6 9 Idle ripple peak to peak 0 25 0 04 0 7 0 15 Seek peak 0 55 0 02 1 7 0 2 Seek average 1 0 33 0 02 0 7 0 1 1...

Page 53: ...system frame which has no electrical level difference at the four screws position and has less than 300 millivolts peak to peak level difference to the file power connector ground Figure 39 Power Sup...

Page 54: ...0 350320 Figure 41 Typical Current Wave Form of 12V at Start Up of DTTA 351010 350840 350640 350430 350320 6 5 1 2 DTTA 351680 351350 351290 Figure 42 Typical Current Wave Form of 12V at Start Up of D...

Page 55: ...6 5 1 3 DTTA 371440 371290 371010 Figure 43 Typical Current Wave Form of 12V at Start Up of DTTA 371440 371290 371010 Specification 47...

Page 56: ...mplementation On The Fly correction performed as a part of read channel function recovers up to 12 symbols of error in 1 sector 1 symbol is 8 bits 6 6 4 Cable Noise Interference To avoid any degradati...

Page 57: ...5 hard disk drive form factor Figure 45 Physical Dimension and Weight DTTA 371440 DTTA 371290 DTTA 371010 DTTA 351680 DTTA 351350 DTTA 351290 DTTA 351010 DTTA 350840 DTTA 350640 DTTA 350430 DTTA 35032...

Page 58: ...Figure 46 Mechanical Dimension 50 OEM Specifications for DTTA 3xxxxx...

Page 59: ...6 7 3 Connector Locations Figure 47 Connector Locations Specification 51...

Page 60: ...6 7 4 Hole Locations The Figure 48 on page 52 shows the outline of DTTA 3xxxxx which includes the hole locations Figure 48 Mounting Positions and the Tappings 52 OEM Specifications for DTTA 3xxxxx...

Page 61: ...ol Type Electrical Screw Driver should be used Mechnical Latch Type Electrical Screw Driver is not recommended because of possibility of mechanical shock higher than specification value which may caus...

Page 62: ...RMS Overall RMS root mean square level of vertical vibration is 0 56G RMS Note The specified levels are measured at the mounting points 6 8 1 2 Swept Sine Vibration The hard disk drive will meet the...

Page 63: ...vel are applied to the drive ten pulses for each direction and for all three axes There must be a minimum of 30 seconds delay between shock pulses The input level is applied to a base plate where the...

Page 64: ...ive subsystem are measured under the following conditions Idle mode Powered on disks spinning track following unit ready to receive and respond to control line commands Operating mode Continuous rando...

Page 65: ...e meter above the drive surface Random operation mode is simulated with 40 seek and 60 idle in time 6 9 2 2 Sound Pressure Level The hard disk drives meet the following sound pressure level Figure 53...

Page 66: ...meet the worldwide EMC requirements listed below IBM will provide technical support to assist users in complying with the EMC requirements United States Federal Communications Commission FCC Rules an...

Page 67: ...6 12 5 Flammability Printed Circuit boards used in this product are made of material with a UL recognized flammability rating of V 1 or better The flammability rating is marked or etched on the board...

Page 68: ...60 OEM Specifications for DTTA 3xxxxx...

Page 69: ...Part 2 ATA Interface Specification Copyright IBM Corp 1998 61...

Page 70: ...62 OEM Specifications for DTTA 3xxxxx...

Page 71: ...of Information technology AT Attachment with Packet Interface Extension ATA ATAPI 4 Revision 17 dated on 30 October 1997 with certain limitations described in 8 0 Deviations From Standard on page 65 7...

Page 72: ...64 OEM Specifications for DTTA 3xxxxx...

Page 73: ...Power Mode Check Power Mode command returns FFh to Sector Count Register when the device is in Idle mode This command does not support 80h as the return value Hard Reset Hard reset response is not th...

Page 74: ...66 OEM Specifications for DTTA 3xxxxx...

Page 75: ...gh A N 1 0 1 2 LBA bits 16 23 2 LBA bits 16 23 A N 1 1 0 Device Head Device Head A N 1 1 0 2 LBA bits 24 27 2 LBA bits 24 27 A N 1 1 1 Status Command A A x x x Invalid address Invalid address 1 imped...

Page 76: ...cylinder number In LBA Mode this register contains Bits 16 23 At the end of the command this register is updated to reflect the current LBA Bits 16 23 The cylinder number may be from zero to the numbe...

Page 77: ...ed 9 7 Drive Address Register Drive Address Register 7 6 5 4 3 2 1 0 HIZ WTG H3 H2 H1 H0 DS1 DS0 Figure 58 Drive Address Register This register contains the inverted drive select and head select addre...

Page 78: ...7 6 5 4 3 2 1 0 ICRCE UNC 0 IDNF 0 ABRT TK0NF AMNF Figure 60 Error Register This register contains status from the last command executed by the device or a diagnostic code At the completion of any com...

Page 79: ...ferred in order to complete the request The contents of the register are defined otherwise on some commands These definitions are given in the command descriptions 9 12 Sector Number Register This reg...

Page 80: ...just before a seek begins When an error occurs this bit is not changed until the Status Register is read by the host at which time the bit again indicates the current seek complete status When the dev...

Page 81: ...set is shown in Figure 62 POR hard soft reset reset Aborting Host interface o o Aborting Device operation 1 1 Initialization of hardware o x x Internal diagnostic o x x Spinning spindle o x x Initiali...

Page 82: ...error 03h Sector buffer error 04h ECC circuitry error 05h Controller microprocessor error 8xh Device 1 failed Figure 64 Diagnostic Codes The meaning of the Error Register diagnostic codes resulting fr...

Page 83: ...reset and the EXECUTE DEVICE DIAGNOSTIC command the Device 0 Error register is shown in Figure 65 Device 1 PDIAG Device 0 Error Present Asserted Passed Register Yes Yes Yes 01h Yes Yes No 0xh Yes No Y...

Page 84: ...linearly mapped with the first LBA addressed sector sector 0 being the same sector as the first logical CHS addressed sector cylinder 0 head 0 sector 1 Irrespective of the logical CHS translation mod...

Page 85: ...l be cleared and INTRQ negated by a Status reg ister read or a write to the Command register When the device is ready to continue the processing of a bus released command and BSY or DRQ is set to one...

Page 86: ...s The idle command also sets the standby timer count and starts the standby timer The Standby and Standby Immediate commands move a device to standby mode immediately from the active or idle modes The...

Page 87: ...te values Attribute values are used to represent the relative reliability of individual performance or calibration attri butes The valid range of attribute values is from 1 to 253 decimal Higher attri...

Page 88: ...or a security erase unit command Device Unlocked mode The device enables all commands If a password is not set this mode is entered after power on otherwise it is entered by a security unlock or a se...

Page 89: ...he end users must set the master password even if only single level password protection is required 10 7 4 Operation example 10 7 4 1 Master Password setting The system manufacturer dealer can set a n...

Page 90: ...cess Non media access command 1 command 1 Password Erase Unit Match Password N Match N Y Y Complete Reject Complete Erase Unit V V V V Enter Device Lock function Unlock mode Disable V Normal operation...

Page 91: ...Master Password V Normal operation but data lost Figure 69 Password Lost 10 7 4 5 Attempt limit for SECURITY UNLOCK command The SECURITY UNLOCK command has an attempt limit The purpose of this attemp...

Page 92: ...r s w retry Command aborted Executable Executable Read Verify Sector s w o retry Command aborted Executable Executable Read Verify Sector s w retry Command aborted Executable Executable Recalibrate Ex...

Page 93: ...Command aborted Executable Executable Write DMA Queued Command aborted Executable Executable Write Long w o retry Command aborted Executable Executable Write Long w retry Command aborted Executable Ex...

Page 94: ...mer usable device size 6 292 242 432 byte 6 2GB Customer usable sector count 12 289 536 BB8600h LBA range for protected area BB8600h to C1ACFFh 1 Shipping HDDs from HDD manufacturer When the HDDs are...

Page 95: ...responsibility to write the data subsequently onto the disk While writing data after completed acknowledgment of a write command soft reset or hard reset does not affect its operation But power off te...

Page 96: ...ration a sequence of media verification is performed automatically When the result of this verification meets the criteria this sector is reallocated Recovered read errors When a read operation for a...

Page 97: ...r responding Interrupts are cleared when the host reads the Status Register issues a reset or writes to the Command Register Figure 128 on page 171 shows the device timeout values 11 1 PIO Data In Com...

Page 98: ...ill set BSY 0 ERR 1 and DRQ 1 The device will then store the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The errored locati...

Page 99: ...data including ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In respon...

Page 100: ...ands involves no data transfer 1 The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head Registers 2 The host writes the command code to the Command...

Page 101: ...nd Register 4 The device sets DMARQ when it is ready to transfer any part of the data 5 Host transfers the data using the DMA transfer protocol currently in effect 6 When all of the data has been tran...

Page 102: ...the device 3 Bus Release If the device is not ready for data transfer REL is set a The device generates an interrupt if release interrupt is enabled b The host may issue another command or wait for s...

Page 103: ...1 1 0 0 0 1 1 1 1 Read Long retry 22 0 0 1 0 0 0 1 0 1 Read Long no retry 23 0 0 1 0 0 0 1 1 1 Read Multiple C4 1 1 0 0 0 1 0 0 3 Read Native Max LBA CYL F8 1 1 1 1 1 0 0 0 1 Read Sectors retry 20 0...

Page 104: ...0 0 1 0 3 Standby 96 1 0 0 1 0 1 1 0 3 Standby Immediate E0 1 1 1 0 0 0 0 0 3 Standby Immediate 94 1 0 0 1 0 1 0 0 2 Write Buffer E8 1 1 1 0 1 0 0 0 4 Write DMA retry CA 1 1 0 0 1 0 1 0 4 Write DMA no...

Page 105: ...t Transfer Mode EF 03 34 bytes of ECC apply on Read Write Long EF 44 Disable read look ahead feature EF 55 Enable release interrupt EF 5D Disable reverting to power on defaults EF 66 Disable write cac...

Page 106: ...he Option Bit of the Sector Count Register should be specified This bit is used by Set Max LBA CYL command V Valid Indicates that the bit is part of an output parameter and should be specified x Indic...

Page 107: ...gister Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V Figure 74 Check Power Mode Command E5h 98h The Check Power M...

Page 108: ...Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR V V V V V V V V 0 V 0 0 0 Figure 75 Execute Device Diagnostic Command 90h The...

Page 109: ...High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 1 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ...

Page 110: ...f data is not verified with read operation whether the sector of data is initialized correctly Any data previously stored on the track will be lost The host may transfer a sector of data containing a...

Page 111: ...cifies current LBA address bits 8 15 Low 16 23 High H In LBA mode this register specifies current LBA address bits 24 27 L 1 Error The Error Register An Abort error ABT 1 will be returned under the fo...

Page 112: ...1 1 D Device Head Command 1 1 1 0 1 1 0 0 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V...

Page 113: ...of removable cylinders 03 00xxH Number of heads in default translate mode 04 0 Reserved 05 0 Reserved 06 003FH Number of sectors per track in default translate mode 07 0000H Number of bytes of sector...

Page 114: ...ors per track 57 58 xxxxH Current capacity in sectors Word 57 specifies the low word of the capacity 59 0xxxH Current Multiple setting bit assignments 15 9 0 Reserved 8 1 Multiple Sector Setting is Va...

Page 115: ...on 17 82 74EBH Command set supported 15 0 Reserved 14 1 NOP command 13 1 READ BUFFER command 12 1 WRITE BUFFER command 11 0 Reserved 10 1 Host Protected Area feature set 9 0 DEVICE RESET command 8 0 S...

Page 116: ...NLOAD MICROCODE command 87 4000H Command set feature default 15 14 01 Word 87 is valid 13 0 0 Reserved 88 0x07H Ultra DMA transfer modes 15 8 0x Current active Ultra DMA transfer mode 15 11 Reserved 0...

Page 117: ...nable Disable 1 Enable 0 Capability 1 Support 129 xxxxH Current Set Feature Option Bit assignments 15 4 Reserved 3 Auto reassign 1 Enable 2 Reverting 1 Enable 1 Read Look ahead 1 Enable 0 Write Cache...

Page 118: ...nter Idle mode immediately and set auto power down timeout parameter standby timer And then the timer starts counting down When the Idle mode is entered the device is spun up to operating speed If the...

Page 119: ...d the drive will enter Standby mode automatically if the timeout interval expires with no drive access from the host The timeout interval will be reinitialized if there is a drive access before the ti...

Page 120: ...er Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 V Figure 85 Idle Immediate Command E1h 95h The Idle Immediate co...

Page 121: ...track and the number of heads minus 1 per cylinder Words 54 58 in Identify Device Information reflects these parame ters The parameters remain in effect until following events Another Initialize Devi...

Page 122: ...tial value Command 0 0 0 0 0 0 0 0 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V...

Page 123: ...r 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V Figure 88 Read Buffer Command E4h The Read Buffer command transfers a sector of d...

Page 124: ...om the device to the host The sectors are transferred through the Data Register 16 bits at a time The host initializes a slave DMA channel prior to issuing the command The data transfers are qualified...

Page 125: ...rred This will be zero unless an unre coverable error occurs Sector Number The sector number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder Hig...

Page 126: ...MA Queued Command C7h This command executes in a similar manner to a READ DMA command The device may perform a bus release or it may execute the data transfer without performing a bus release if the d...

Page 127: ...the device performs a bus release This bit is set to one when the device is ready to transfer data Input Parameters From The Device On Command Complete Sector Count bits 7 3 Tag contain the Tag of th...

Page 128: ...ta and ECC bytes from the device to the host After 512 bytes of data have been transferred the device will keep setting D R Q 1 to indicate that the device is ready to transfer the ECC bytes to the ho...

Page 129: ...nder High Low The cylinder number of the transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the transferred sector L 0 In LBA mode...

Page 130: ...ore sectors of data from disk media then transfers the data from the device to the host The sectors are transferred through the Data Register 16 bits at a time Command execution is identical to the Re...

Page 131: ...f the last transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contain...

Page 132: ...AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V Figure 93 Read Native Max LBA CYL F8h This command returns the native max LBA CYL of HDD which is not effected by Set Max LBA CYL command I...

Page 133: ...Sectors command reads one or more sectors of data from disk media then transfers the data from the device to the host The sectors are transferred through the Data Register 16 bits at a time If an unco...

Page 134: ...ast transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains curre...

Page 135: ...ectors verifies one or more sectors on the device No data is transferred to the host The difference of Read Sectors command and Read Verify Sectors command is whether the data is trans ferred to the h...

Page 136: ...st transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains curren...

Page 137: ...der High Device Head 1 1 D Device Head Command 0 0 0 1 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0...

Page 138: ...st including information specified in Figure 98 Then the device checks the transferred password If the User Password or Master Password matches the given password the device disables the security mode...

Page 139: ...rror Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 V Figure 99 Security Erase Prepare Command F3h The Se...

Page 140: ...initializes all user data sectors then disables the device lock function Note that the Security Erase Unit command initializes from LBA 0 to Native MAX LBA Host MAX LBA set by Initialize Drive Paramet...

Page 141: ...ted The secu rity erase prepare command should be completed immediately prior to the Security Erase Unit command If the device receives a Security Erase Unit command without a prior Security Erase Pre...

Page 142: ...4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V Figure 102 Security Freeze Lock Command F5h The Security Freeze Lock Command allows the device to enter f...

Page 143: ...ty Set Password Command F1h The Security Set Password command enables security mode feature device lock function and sets the master password or the user password The security mode feature device lock...

Page 144: ...Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will...

Page 145: ...and is com pleted the device will be in device lock mode The password has not been changed yet The Security Unlock command requests to transfer a single sector of data from the host including informa...

Page 146: ...ates that device regards Password as Master Password The user can detect if the attempt to unlock the device has failed due to a mismatched password as this is the only reason that an abort error will...

Page 147: ...Command 7xh The Seek command initiates a seek to the designated track and selects the designated head The device need not be formatted for a seek to execute properly Output Parameters To The Device S...

Page 148: ...Command A2h The Service command is used to provide data transfer and or status of a command that was previously bus released Output Parameters To The Device D selected device Input Parameters From Th...

Page 149: ...EFh The Set Feature command is to establish the following parameters which affect the execution of certain fea tures as shown in below table ABT will be set to 1 in the Error Register if the Feature...

Page 150: ...00 nnn nnn 000 001 010 Note 2 If the number of auto reassigned sector reaches the device s reassignment capacity the write cache function will be automatically disabled Although the device still accep...

Page 151: ...sses beyond that LBA CYL are rejected with setting ABORT bit in status register Identify device command returns the LBA CYL which is set via this command as a default value Read Native Max LBA CYL com...

Page 152: ...meters From The Device Sector Number In LBA mode this register contains max LBA bits 0 7 which is set L 1 In CHS mode this register contains max sector number L 0 Cylinder High Low In LBA mode this re...

Page 153: ...0 0 V 0 0 0 V 0 0 V Figure 111 Set Multiple Command C6h The Set Multiple command enables the device to perform Read and Write Multiple commands and estab lishes the block size for these commands The...

Page 154: ...0 0 1 1 0 Status See Below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 V Figure 112 Sleep Comman...

Page 155: ...Attribute Values Attribute Thresholds and other low level subcommands that can be used for logging and reporting purposes and to accommodate special user needs The S M A R T Function Set command has s...

Page 156: ...F1h written by the host into the device s Sector Count Register before issuing the SMART Enable Disable Attribute Autosave subcommand will cause this feature to be enabled Any other non zero value wr...

Page 157: ...eceipt of the SMART Disable Operations subcommand from the host the device disables S M A R T capabilities and functions and then saves any updated Attribute Values to the Attribute Data sector After...

Page 158: ...ection status 1 16Ah 1 2 Total segments required for 1 16Bh 1 01h off line data collection Total time in seconds to 2 16Ch 1 2 complete next segment Current segment pointer 1 16Eh 1 2 Off line data co...

Page 159: ...ll attributes prior to any data collection FDh maximum value FEh value is not valid FFh invalid for attribute value not to be used Vendor Specific 8 04h binary Total Bytes 12 Figure 115 Individual Att...

Page 160: ...hem into normalized values which the host can then compare with the Threshold values A Threshold is the excursion limit for a normalized Attribute Value In normalizing the raw data the device will per...

Page 161: ...indicating the next segment to execute as an off line data collection activity This varies from 00h to the total number of segments The current segment pointer will be 00h if the off line data collect...

Page 162: ...ttribute Values Description Bytes Offset Format Value Data Structure Revision Number 2 00h binary 0005h 1st Attribute Threshold 12 02h 1 2 30th Attribute Threshold 12 15Eh 1 2 Reserved 18 16Ah 3 Vendo...

Page 163: ...Bytes 12 Figure 118 Individual Threshold Data Structure 12 31 3 3 Attribute ID Numbers Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures 12 31 3 4 Attribute...

Page 164: ...n a S M A R T disabled state The device is unable to read its Attribute Values or 10h Attribute Thresholds data structure 51h or 40h The device is unable to write to its Attribute Values 51h 10h data...

Page 165: ...uses the device to enter the Standby Mode immediately and set auto power down timeout parameter standby timer When the Standby mode is entered the drive is spun down but the interface remains active I...

Page 166: ...255 21 minutes 15 seconds When the automatic power down sequence is enabled the drive will enter Standby mode automatically if the timeout interval expires with no drive access from the host The timeo...

Page 167: ...6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 V 0 V Figure 121 Standby Immediate Command E0h 94h The Standby Immediate command causes the device to en...

Page 168: ...egister Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V Figure 122 Write Buffer Command E8h The Write Buffer comman...

Page 169: ...host to the device then the data is written to the disk media The sectors of data are transferred through the Data Register 16 bits at a time The host initializes a slave DMA channel prior to issuing...

Page 170: ...equested sectors not transferred This will be zero unless an unre coverable error occurs Sector Number The sector number of the last transferred sector L 0 In LBA mode this register contains current L...

Page 171: ...Write DMA Queued Command CCh This command executes in a similar manner to a WRITE DMA command The device may perform a bus release or it may execute the data transfer without performing a bus release...

Page 172: ...vice performs a bus release This bit is set to one when the device is ready to transfer data Input Parameters From The Device On Command Complete Sector Count bits 7 3 Tag contain the Tag of the compl...

Page 173: ...the ECC bytes are written to the disk media After 512 bytes of data have been transferred the device will keep setting D R Q 1 to indicate that the device is ready to receive the ECC bytes from the h...

Page 174: ...its 8 15 Low 16 23 High L 1 H The head number of the sector to be transferred L 0 In LBA mode this register contains current LBA bits 24 27 L 1 The file internally uses 34 bytes of ECC on all data rea...

Page 175: ...sfers one or more sectors from the host to the device the the data is written to the disk media Command execution is identical to the Write Sectors command except that an interrupt is generated for ea...

Page 176: ...ast transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains curre...

Page 177: ...ors from the host to the device then the data is written to the disk media The sectors are transferred through the Data Register 16 bits at a time If an uncorrectable error occurs the write will be te...

Page 178: ...ast transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains curre...

Page 179: ...Signal Status Register 31 sec Hard Reset Asserted BSY 0 and RDY 1 Data In Device Busy After OUT to Command Status Register 400 ns Command Command Code Out Register BSY 1 Interrupt DRQ For Status Regi...

Page 180: ...atus Register 400 ns Transfer Command Code Out Register BSY 1 Command Figure 129 Timeout Values Continued Command category is referred to 11 0 Command Protocol on page 89 The abbreviations ns us ms an...

Page 181: ...Obsolete 34h 3Bh Reserved Reserved Reserved 3Ch WRITE VERIFY No Obsolete 3Dh 3Fh Reserved Reserved Reserved 40h READ VERIFY SECTOR S w retry Yes Mandatory 41h READ VERIFY SECTOR S w o retry Yes Mandat...

Page 182: ...D BUFFER Yes Optional E5h CHECK POWER MODE 1 Yes Optional 2 E6h SLEEP 1 Yes Optional 2 E7h FLUSH CACHE Yes Optional E8h WRITE BUFFER Yes Optional E9h WRITE SAME No Retired EAh EBh Reserved Reserved Re...

Page 183: ...tes ECC Yes Obsolete 54h Set cache segments No Obsolete 55h Disable read look ahead feature Yes Optional 5Dh Enable release interrupt Yes Optional 5Eh Enable SERVICE interrupt No Optional 66h Disable...

Page 184: ...176 OEM Specifications for DTTA 3xxxxx...

Page 185: ...able Password F6h 130 Security Erase Prepare F3h 131 Security Erase Unit F4h 132 Security Freeze Lock F5h 134 Security Set Password F1h 135 Security Unlock F2h 137 Seek 7xh 139 Service A2h 140 Set Fea...

Page 186: ...Sector Number Register 71 Status Register 71 Register Initialization 74 Reset Diagnostic and Reset considerations 74 Register Initialization 74 RST 69 S S M A R T Function 79 Attribute thresholds 79...

Page 187: ...meout Parameter 110 157 Timeout Values 171 TK0NF 70 U UNC 70 V V 98 W Write Buffer 90 160 Write Cache 87 Write DMA 92 161 Write DMA Queued 93 163 Write Long 90 165 Write Multiple 90 167 Write Sectors...

Page 188: ...Published in Japan S00K 0286 02...

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