IBM DTTA-350320 Specifications Download Page 39

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Figure 23. Ultra D M A cycle timings (Host terminating Read)

Specification

Summary of Contents for DTTA-350320

Page 1: ...OEM HARD DISK DRIVE SPECIFICATIONS for DTTA 3xxxxx 16 8GB 3 2GB 3 5 Inch Hard Disk Drive with ATA Interface Revision 2 0 S00K 0286 02 ...

Page 2: ......

Page 3: ...OEM HARD DISK DRIVE SPECIFICATIONS for DTTA 3xxxxx 16 8GB 3 2GB 3 5 Inch Hard Disk Drive with ATA Interface Revision 2 0 S00K 0286 02 ...

Page 4: ...his publication may contain reference to or information about IBM products machines and programs programming or services that are not announced in your country Such references or infor mation must not be construed to mean that IBM intends to announce such IBM products programming or services in your country Technical information about this product is available by contacting with local IBM represen...

Page 5: ...s 15 5 0 Physical Format 17 5 1 Shipped Format 17 6 0 Specification 19 6 1 Electrical interface specification 19 6 1 1 Connectors 19 6 1 2 Signal Definition 20 6 1 3 Interface Logic Signal Levels 23 6 2 Signal Timings 24 6 2 1 Reset Timings 24 6 2 2 PIO Timings 25 6 2 3 DMA Timings 27 6 2 4 Ultra DMA Timings 29 6 2 5 Addressing of HDD Registers 37 6 2 6 Cabling 37 6 3 Jumper Settings 38 6 3 1 Loca...

Page 6: ... C Tick Mark 58 6 12 Safety 59 6 12 1 Underwriters Lab UL Approval 59 6 12 2 Canadian Standards Authority CSA Approval 59 6 12 3 IEC Compliance 59 6 12 4 German Safety Mark 59 6 12 5 Flammability 59 6 12 6 Secondary Circuit Protection 59 6 13 Packaging 59 Part 2 ATA Interface Specification 61 7 0 General 63 7 1 Introduction 63 7 2 Terminology 63 8 0 Deviations From Standard 65 9 0 Registers 67 9 1...

Page 7: ...word 80 10 7 4 Operation example 81 10 7 5 Command Table 84 10 8 Protected Area Function 86 10 8 1 Example for operation In LBA mode 86 10 9 Write Cache Function 87 10 10 Reassign Function 87 10 10 1 Auto Reassign Function 88 10 11 Automatic Drive Maintenance ADM 88 11 0 Command Protocol 89 11 1 PIO Data In Commands 89 11 2 PIO Data Out Commands 90 11 3 Non Data Commands 91 11 4 DMA Commands 92 11...

Page 8: ... Multiple C6h 145 12 30 Sleep E6h 99h 146 12 31 S M A R T Function Set B0h 147 12 31 2 Device Attributes Data Structure 150 12 31 3 Device Attribute Thresholds Data Structure 154 12 31 4 Error Reporting 155 12 32 Standby E2h 96h 157 12 33 Standby Immediate E0h 94h 159 12 34 Write Buffer E8h 160 12 35 Write DMA CAh CBh 161 12 36 Write DMA Queued CCh 163 12 37 Write Long 32h 33h 165 12 38 Write Mult...

Page 9: ...rpm Note The specifications are subject to change without notice 1 1 Glossary Word Meaning Kbpi 1 000 Bit Per Inch Mbps 1 000 000 Bit per second GB 1 000 000 000 bytes MB 1 000 000 bytes KB 1 000 bytes 32 KB 32 x 1 024 bytes 64 KB 64 x 1 024 bytes Mb sq in 1 000 000 bits per square inch MLC Machine Level Control S M A R T Self Monitoring and Analysis Reporting Technology 1 2 General Caution The dr...

Page 10: ...2 OEM Specifications for DTTA 3xxxxx ...

Page 11: ...Kbytes Write Cache Queued feature support On The Fly correction 12 Bytes Automatic Error Recovery procedures for read and write commands Self Diagnostics on Power on and resident diagnostics Data Trandfer PIO Mode 4 16 6 MB sec Ultra DMA 33 33 3 MB sec CHS and LBA mode Transparent Defect Management with ADR Automatic Defect Reallocation Power Saving modes S M A R T function support Seculity functi...

Page 12: ...4 OEM Specifications for DTTA 3xxxxx ...

Page 13: ...Part 1 Functional Specification Copyright IBM Corp 1998 5 ...

Page 14: ...6 OEM Specifications for DTTA 3xxxxx ...

Page 15: ...es DTTA 351680 16 9 16383 16 15 63 33 022 080 16 907 304 960 DTTA 351350 13 5 16383 16 15 63 26 414 640 13 524 295 680 DTTA 351290 12 9 16383 16 15 63 25 385 472 12 997 361 664 DTTA 351010 10 1 16383 16 15 63 19 807 200 10 141 286 400 DTTA 350840 8 4 16383 16 15 63 16 514 064 8 455 200 768 DTTA 350640 6 4 12592 13431 16 15 63 12 692 736 6 498 680 832 DTTA 350430 4 3 8400 8960 16 15 63 8 467 200 4 ...

Page 16: ... 3 Ultra DMA 33 Data Buffer Size KB 464 464 Rotational Speed RPM 5400 7200 Average Latency msec 5 56 4 17 Recording Density Kbpi 196 1 max 178 1 max Track Density TPI 13 700 13 700 Areal Density Gb sq in 2 687 max 2 440 max Number of Zone 8 8 Number of Data Disks 5 4 3 3 2 2 1 5 5 4 Number of Data Heads 10 8 6 5 4 3 2 10 9 7 Servo Method Embeded Sector Servo Embeded Sector Servo 8 OEM Specificatio...

Page 17: ...command when the requested data is not in the buffer exclude Physical seek time Latency time Figure 3 Command Overhead Note The above table gives an average time 3 3 2 Mechanical Positioning 3 3 2 1 Average Seek Time Without Command Overhead Including Settling Figure 4 Mechanical Positioning Performance Typical and Max are given throughout the performance specification by Typical Average of the dr...

Page 18: ...eek Length 1 to max Tn in Inward measured seek time for a n track seek Tn out Outward measured seek time for a n track seek 3 3 2 2 Full Stroke Seek Without Command Overhead Including Settling Figure 5 Full Stroke Seek Time Full stroke seek is measured as the average of 1000 full stroke seeks with a random head switch from both directions inward and outward 3 3 2 3 Head Switch Time Head Skew Figur...

Page 19: ...and outward 3 3 2 6 Average Latency Figure 9 Latency Time 3 3 3 Drive Ready Time Figure 10 Drive Ready Time Ready The condition in which the drive is able to perform a media access command e g read write immediately Power On This includes the time required for the internal self diagnostics Note Max Power On to ready Time is the maximum time period Device 0 waits up to for Device 1 to assert PDIAG ...

Page 20: ...inder 512 B of Surface per cylinder 1 Head Switch Time C Cylinder Change Time D of Surface One Revolution Time Instantaneous Buffer Host Transfer Rate Mbyte sec defines the maximum data transfer rate on AT Bus It also depends on the speed of the host The measurement method is given in 3 3 5 Throughput on page 13 Description DTTA 35xxxx DTTA 37xxxx Disk Buffer Transfer Zone 0 Instantaneous typical ...

Page 21: ...tency sec D Sustained DiskÄBuffer Transfer Rate byte sec E BufferÄHost Transfer Rate byte sec DRQ Data ReQuest interval sec 3 3 5 2 Random Access The above table gives the time required to execute a total of 1000x read commands which access a random LBA T A B C 512 D 512 E DRQ 4096 where T Calculated Time sec A Command Process Time Command overhead sec B Average Seek Time sec C Latency sec D Avera...

Page 22: ... or hard reset can change the mode to standby Notes 1 Upon Power down or Spindle stopped a head locking mechanism will secure the heads in the ID parking position 3 3 6 1 Mode Transition Time Figure 13 Mode Transition Time Note The actual spin down time will exist however the command will be processed immediately From To DTTA 371440 DTTA 371290 DTTA 371010 DTTA 351680 DTTA 351350 DTTA 351290 DTTA ...

Page 23: ...data in the write cache have been flushed onto the disk Checking just before power off is recommended to prevent data loss To confirm successful completion of Software Reset To confirm successful completion of Flush Cache command To confirm successful completion of Check Power Mode command 4 3 Equipment Status Equipment status is available to the host system any time the drive is not ready to read...

Page 24: ...16 OEM Specifications for DTTA 3xxxxx ...

Page 25: ... tracks of inner zone Ä Ä ÂÄÄÄÄÄÄÂÄÄÄÄÄÄÂÄÄÄÄÄÄÂÄÄÄÄÄÄÂÄÄÄÄÄÄÂÄÄÄÄÄÄÂ Ä Ä N N 1 N 2 N 3 Defect Defect Ä Ä ÁÄÄÄÄÄÄÁÄÄÄÄÄÄÁÄÄÄÄÄÄÁÄÄÄÄÄÄÁÄÄÄÄÄÄÁÄÄÄÄÄÄÁ Ä Ä A A ÀÄÄÄÄÄÄÄÄÄÄÄÄÙ ÀÄÄÄÄÄÄÄÄÄÄÄÄÙ Skip Skip Defects are skipped without any constraint such as track or cylinder boundary The calculation from LBA to physical is done automatically by internal table Note There is possibility to reallocate sectors...

Page 26: ...18 OEM Specifications for DTTA 3xxxxx ...

Page 27: ... mate with AMP part 1 480424 0 using AMP pins part 350078 4 strip or part 61173 4 loose piece or their equivalents Pin assignments are shown below Figure 14 Power Connector Pin Assignments 6 1 1 2 AT Signal Connector The AT signal connector is a 40 pin connector Pin 1 2 3 4 Voltage 12 V GND GND 5 V Copyright IBM Corp 1998 19 ...

Page 28: ... Notes 1 O designates an output from the Drive 2 I designates an input to the Drive 3 I O designates an input output common 4 OC designates Open Collector or Open Drain output 5 The signal lines marked with are redefined during the Ultra DMA protocol to provide special func tions These lines change from the conventional to special definitions at the moment the Host decides to allow a DMA burst if ...

Page 29: ...6 bit wide data word This signal is an Open Drain output with 24 mA sink capability and an external resistor is needed to pull this line to 5 volts DASP This is a time multiplexed signal which indicates that a drive is active or that device 1 is present This signal is driven by Open Drain driver and internally pulled up to 5 volts through a 10kΩ resistor During Power On initialization or after RES...

Page 30: ... is a 3 state line with 24mA sink capability and internally pulled down to GND through 10 kΩ resistor HDMARDY Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive HDMARDY is a flow control signal for Ultra DMA data in bursts This signal is held asserted by the host to indicate to the device that the host is ready to receive Ultra DMA data in transfers The host may...

Page 31: ...an Ultra DMA data in transfer Note The termination resistors at the device side are implemented as follows Device Termination implemented on HDD side 33 ohm for DD0 thru DD15 DMARQ INTRQ 82 ohm for CS0 CS1 DA00 DA01 DA02 DIOR DIOW DMACK 22 ohm for IORDY 6 1 3 Interface Logic Signal Levels The interface logic signal has the following electrical specifications Inputs Input High Voltage Ä 2 0 V min I...

Page 34: ...ors and read multiple operations the interval from the end of negation of the DRQ bit until setting of the next DRQ bit is as follows In case that a host reads the status register only before the sector or block transfer DRQ interval DRQ interval 5 2µsec In case that a host reads the status register after or both before and after the sector or block transfer DRQ interval 14 4µsec 26 OEM Specificat...

Page 45: ...eg 0 1 1 0 0 Cylinder low Reg Cylinder low Reg 0 1 1 0 1 Cylinder high Reg Cylinder high Reg 0 1 1 1 0 Drive Head Reg Drive Head Reg 0 1 1 1 1 Status Reg Command Reg ÃÄÄÄÄÄÅÄÄÄÄÄÅÄÄÄÄÅÄÄÄÄÅÄÄÄÄÅÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Control Block Registers ÃÄÄÄÄÄÅÄÄÄÄÄÅÄÄÄÄÅÄÄÄÄÅÄÄÄÄÅÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÂÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ 1 0 1 1 0 Alt Status Reg Device control Reg 1 0 1 1 1 Drive address Re...

Page 51: ...ude 300 to 3048 m Non Operating Conditions Temperature 40 to 65 C Relative Humidity 5 to 95 R H non condensing Maximum Wet Bulb Temperature 35 C non condensing Maximum Temperature Gradient 15 C Hour Altitude 300 to 12 000 m Note The system has to provide sufficient ventilation to maintain a surface temperature below 60 C at the center of the top cover of the drive Non operating condition should no...

Page 52: ...s 5Volts 12Volts Total W Pop Mean Std Dev Pop Mean Std Dev Idle Average 0 29 0 02 0 45 0 1 6 9 Idle ripple peak to peak 0 25 0 04 0 7 0 15 Seek peak 0 55 0 02 1 7 0 2 Seek average 1 0 33 0 02 0 7 0 1 10 1 Start up max 0 7 0 02 2 0 1 RND R W peak 0 8 0 15 0 75 0 1 RND R W average 2 0 42 0 15 0 65 0 1 9 9 Standby Sleep average 0 165 0 01 0 0045 0 001 0 9 Figure 38 Power Supply Current of DTTA 351680...

Page 53: ...r system frame which has no electrical level difference at the four screws position and has less than 300 millivolts peak to peak level difference to the file power connector ground Figure 39 Power Supply Current of DTTA 351010 350840 350640 350430 350320 All values in Amps 5Volts 12Volts Total W Pop Mean Std Dev Pop Mean Std Dev Idle Average 0 29 0 02 0 16 0 05 3 4 Idle ripple peak to peak 0 22 0...

Page 54: ...30 350320 Figure 41 Typical Current Wave Form of 12V at Start Up of DTTA 351010 350840 350640 350430 350320 6 5 1 2 DTTA 351680 351350 351290 Figure 42 Typical Current Wave Form of 12V at Start Up of DTTA 351680 351350 351290 46 OEM Specifications for DTTA 3xxxxx ...

Page 55: ...6 5 1 3 DTTA 371440 371290 371010 Figure 43 Typical Current Wave Form of 12V at Start Up of DTTA 371440 371290 371010 Specification 47 ...

Page 56: ...implementation On The Fly correction performed as a part of read channel function recovers up to 12 symbols of error in 1 sector 1 symbol is 8 bits 6 6 4 Cable Noise Interference To avoid any degradation of performance throughput or error when the interface cable is routed on top or comes in contact with the HDA assembly the drive must be grounded electrically to the system frame by four screws Th...

Page 57: ... 5 hard disk drive form factor Figure 45 Physical Dimension and Weight DTTA 371440 DTTA 371290 DTTA 371010 DTTA 351680 DTTA 351350 DTTA 351290 DTTA 351010 DTTA 350840 DTTA 350640 DTTA 350430 DTTA 350320 Height mm 25 4 0 4 25 4 0 4 25 4 0 4 Width mm 101 6 0 4 101 6 0 4 101 6 0 4 Length mm 146 0 0 6 146 0 0 6 146 0 0 6 Weight gram 630 Max 630 Max 530 Max Specification 49 ...

Page 58: ...Figure 46 Mechanical Dimension 50 OEM Specifications for DTTA 3xxxxx ...

Page 59: ...6 7 3 Connector Locations Figure 47 Connector Locations Specification 51 ...

Page 60: ...6 7 4 Hole Locations The Figure 48 on page 52 shows the outline of DTTA 3xxxxx which includes the hole locations Figure 48 Mounting Positions and the Tappings 52 OEM Specifications for DTTA 3xxxxx ...

Page 61: ...rol Type Electrical Screw Driver should be used Mechnical Latch Type Electrical Screw Driver is not recommended because of possibility of mechanical shock higher than specification value which may cause HDD damage The system is responsible for mounting the drive securely enough to prevent from excessive motion or vibration of the drive at seek operation or spindle rotation using appropriate screws...

Page 62: ...G RMS Overall RMS root mean square level of vertical vibration is 0 56G RMS Note The specified levels are measured at the mounting points 6 8 1 2 Swept Sine Vibration The hard disk drive will meet the criteria shown below while operating in respective conditions No errors 0 5 G 0 peak 5 300 5 Hz sine wave 0 5 oct min sweep rate with 3 minutes dwells at 2 major resonances No data loss 1 G 0 peak 5 ...

Page 63: ...evel are applied to the drive ten pulses for each direction and for all three axes There must be a minimum of 30 seconds delay between shock pulses The input level is applied to a base plate where the drive is attached with four screws 6 8 4 Non Operating Shock The drive withstands the following half sine shock pulse No data loss with 75G 11ms No data loss with 175G 2ms The shocks are applied for ...

Page 64: ...rive subsystem are measured under the following conditions Idle mode Powered on disks spinning track following unit ready to receive and respond to control line commands Operating mode Continuous random cylinder selection and seek operation of actuator with a delay for a time period achieving the required seek rate Ns according to the following formula Ns 0 4 Tt Tl where Ns average seek rate in se...

Page 65: ...ne meter above the drive surface Random operation mode is simulated with 40 seek and 60 idle in time 6 9 2 2 Sound Pressure Level The hard disk drives meet the following sound pressure level Figure 53 Sound Pressure Level of DTTA 35xxxx Mode Mean Max Idle on Track 33 dBA 37 dBA Random Operation 38 dBA 41 dBA Figure 54 Sound Pressure Level of DTTA 37xxxx Mode Mean Max Idle on Track 34 dBA 38 dBA Ra...

Page 66: ...l meet the worldwide EMC requirements listed below IBM will provide technical support to assist users in complying with the EMC requirements United States Federal Communications Commission FCC Rules and Regulations Class B Part 15 European Economic Community EEC directive number 76 889 related to the control of radio fre quency interference and the Verband Deutscher Elektrotechniker VDE requiremen...

Page 67: ...1 6 12 5 Flammability Printed Circuit boards used in this product are made of material with a UL recognized flammability rating of V 1 or better The flammability rating is marked or etched on the board All other parts not considered electrical components are made of material with a UL recognized flammability rating of V 1 or better except minor mechanical parts 6 12 6 Secondary Circuit Protection ...

Page 68: ...60 OEM Specifications for DTTA 3xxxxx ...

Page 69: ...Part 2 ATA Interface Specification Copyright IBM Corp 1998 61 ...

Page 70: ...62 OEM Specifications for DTTA 3xxxxx ...

Page 71: ... of Information technology AT Attachment with Packet Interface Extension ATA ATAPI 4 Revision 17 dated on 30 October 1997 with certain limitations described in 8 0 Deviations From Standard on page 65 7 2 Terminology Device Device indicates DTTA 3xxxxx Host Host indicates the system that the device is attached to Copyright IBM Corp 1998 63 ...

Page 72: ...64 OEM Specifications for DTTA 3xxxxx ...

Page 73: ...k Power Mode Check Power Mode command returns FFh to Sector Count Register when the device is in Idle mode This command does not support 80h as the return value Hard Reset Hard reset response is not the same as that of power on reset Refer to section 10 1 Reset Response on page 73 for detail Copyright IBM Corp 1998 65 ...

Page 74: ...66 OEM Specifications for DTTA 3xxxxx ...

Page 75: ...ount A N 0 1 1 Sector Number Sector Number A N 0 1 1 2 LBA bits 0Ä 7 2 LBA bits 0Ä 7 A N 1 0 0 Cylinder Low Cylinder Low A N 1 0 0 2 LBA bits 8Ä15 2 LBA bits 8Ä15 A N 1 0 1 Cylinder High Cylinder High A N 1 0 1 2 LBA bits 16Ä23 2 LBA bits 16Ä23 A N 1 1 0 Device Head Device Head A N 1 1 0 2 LBA bits 24Ä27 2 LBA bits 24Ä27 A N 1 1 1 Status Command ÃÄÄÄÄÄÄÅÄÄÄÄÄÄÅÄÄÄÄÄÅÄÄÄÄÄÅÄÄÄÄÄÅÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ...

Page 76: ... At the end of the command this register is updated to reflect the current cylinder number In LBA Mode this register contains Bits 16 23 At the end of the command this register is updated to reflect the current LBA Bits 16 23 The cylinder number may be from zero to the number of cylinders minus one 9 4 Cylinder Low Register This register contains the low order bits of the starting cylinder address...

Page 77: ...bled 9 7 Drive Address Register ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Drive Address Register ÃÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄ 7 6 5 4 3 2 1 0 HIZ ÄWTG ÄH3 ÄH2 ÄH1 ÄH0 ÄDS1 ÄDS0 ÀÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÙ Figure 58 Drive Address Register This register contains the inverted drive select and head select addresses of the currently selected drive Bit De...

Page 78: ...ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Error Register ÃÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄÂÄÄÄÄÄ 7 6 5 4 3 2 1 0 ICRCE UNC 0 IDNF 0 ABRT TK0NF AMNF ÀÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÁÄÄÄÄÄÙ Figure 60 Error Register This register contains status from the last command executed by the device or a diagnostic code At the completion of any command except Execute Device Diagnostic the contents o...

Page 79: ...defined otherwise on some commands These definitions are given in the command descriptions 9 12 Sector Number Register This register contains the starting sector number for any disk data access for the subsequent command The sector number is from one to the maximum number of sectors per track In LBA mode this register contains Bits 0 7 At the end of the command this register is updated to reflect ...

Page 80: ... just before a seek begins When an error occurs this bit is not changed until the Status Register is read by the host at which time the bit again indicates the current seek complete status When the device enters into or is in Standby mode or Sleep mode this bit is set by device in spite of not spinning up SERV SRV Service SRV is set to one when the device is ready to transfer data after it release...

Page 81: ...reset reset ÃÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÅÄÄÄÄÄÅÄÄÄÄÄÅÄÄÄÄÄ Aborting Host interface Ä o o Aborting Device operation Ä 1 1 Initialization of hardware o x x Internal diagnostic o x x Spinning spindle o x x Initialization of registers 2 o o o DASP handshake o o x PDIAG handshake o o o Reverting programmed parameters to default o 3 3 Ä Number of CHS set by Initialize Device Parameter Ä M...

Page 84: ...e linearly mapped with the first LBA addressed sector sector 0 being the same sector as the first logical CHS addressed sector cylinder 0 head 0 sector 1 Irrespective of the logical CHS translation mode currently in effect the LBA address of a given logical sector does not change The following is always true LBA cylinder heads_per_cylinder heads sectors_per_track sector 1 where heads_per_cylinder ...

Page 85: ...ll be cleared and INTRQ negated by a Status reg ister read or a write to the Command register When the device is ready to continue the processing of a bus released command and BSY or DRQ is set to one i e the device is processing another command on the bus the device requests service by setting SERV to one SERV shall remain set until all commands ready for service have been serviced At command com...

Page 86: ...es The idle command also sets the standby timer count and starts the standby timer The Standby and Standby Immediate commands move a device to standby mode immediately from the active or idle modes The standby command also sets the standby timer count The Sleep command moves a device to sleep mode The device s interface becomes inactive at the com pletion of the sleep command A reset is required t...

Page 87: ... being used and the identity of these attributes is vendor specific and proprietary 10 6 2 Attribute values Attribute values are used to represent the relative reliability of individual performance or calibration attri butes The valid range of attribute values is from 1 to 253 decimal Higher attribute values indicate that the analysis algorithms being used by the device are predicting a lower prob...

Page 88: ...d or a security erase unit command Device Unlocked mode The device enables all commands If a password is not set this mode is entered after power on otherwise it is entered by a security unlock or a security erase unit command Device Frozen mode The device enables all commands except those which can update the device lock function set change password The device enters this mode via a Security Free...

Page 89: ...e end users must set the master password even if only single level password protection is required 10 7 4 Operation example 10 7 4 1 Master Password setting The system manufacturer dealer can set a new Master Password from default Master Password using the Security Set Password command without enabling the Device Lock Function 10 7 4 2 User Password setting When a User Password is set the device w...

Page 90: ...Erase Prepare Media access NonÄmedia access command 1 command 1 Password Erase Unit ÀÄ Match Password ÄÄÄÄÄÄ N Match N Y Y Complete Reject Complete Erase Unit V V V V ÀÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÙ Enter Device Lock function Unlock mode Disable V ÀÄÄÄÄ Normal operation All commands are available V Freeze Lock command V Enter Device Frozen mode Normal Operation except Set Password Disable Pa...

Page 91: ...d with Master Password V Normal operation but data lost Figure 69 Password Lost 10 7 4 5 Attempt limit for SECURITY UNLOCK command The SECURITY UNLOCK command has an attempt limit The purpose of this attempt limit is to prevent that someone attempts to unlock the drive by using various passwords many times The device counts the password mismatch If the password does not match the device counts it ...

Page 92: ...or s w retry Command aborted Executable Executable Read Verify Sector s w o retry Command aborted Executable Executable Read Verify Sector s w retry Command aborted Executable Executable Recalibrate Executable Executable Executable Security Disable Password Command aborted Executable Command aborted Security Erase Prepare Executable Executable Executable Security Erase Unit Executable Executable C...

Page 93: ... Command aborted Executable Executable Write DMA Queued Command aborted Executable Executable Write Long w o retry Command aborted Executable Executable Write Long w retry Command aborted Executable Executable Write Multiple Command aborted Executable Executable Write Sector s w o retry Command aborted Executable Executable Write Sector s w retry Command aborted Executable Executable Write Verify ...

Page 94: ...omer usable device size 6 292 242 432 byte 6 2GB Customer usable sector count 12 289 536 BB8600h LBA range for protected area BB8600h to C1ACFFh 1 Shipping HDDs from HDD manufacturer When the HDDs are shipped from HDD manufacturer the device has been tested to have usable capacity of 6 4GB besides flagged media defects not to be visible by system 2 Preparing HDDs at system manufacturer Special uti...

Page 95: ... responsibility to write the data subsequently onto the disk While writing data after completed acknowledgment of a write command soft reset or hard reset does not affect its operation But power off terminates writing operation immediately and unwritten data are to be lost Soft reset Check Power Mode and Flush Cache commands during writing the cached data are executed after the completion of writi...

Page 96: ...eration a sequence of media verification is performed automatically When the result of this verification meets the criteria this sector is reallocated Recovered read errors When a read operation for a sector failed once then recovered at the specific ERP step this sector of data is reallocated automatically A media verification sequence may be run prior to the relocation according to the pre defin...

Page 97: ...er responding Interrupts are cleared when the host reads the Status Register issues a reset or writes to the Command Register Figure 128 on page 171 shows the device timeout values 11 1 PIO Data In Commands These commands are Identify Device Read Buffer Read Long Read Multiple Read Sectors SMART Read Attribute Values SMART Read Attribute Thresholds Execution includes the transfer of one or more 51...

Page 98: ...will set BSY 0 ERR 1 and DRQ 1 The device will then store the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The errored location will be reported with CHS mode or LBA mode the mode is decided by mode select bit bit 6 of Device Head register on issuing the command If an Uncorrectable Data Error UNC 1 occurs the defective dat...

Page 99: ...f data including ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In response to the interrupt the host reads the Status Register f The device clears the interrupt in response to the Status Register being read The Write Multiple command transfers one block of data for each ...

Page 100: ...mands involves no data transfer 1 The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head Registers 2 The host writes the command code to the Command Register 3 The device sets BSY 1 4 When the device has finished processing the command it sets BSY 0 and interrupts the host 5 In response to the interrupt the host reads the Status Register 6 The d...

Page 101: ...and Register 4 The device sets DMARQ when it is ready to transfer any part of the data 5 Host transfers the data using the DMA transfer protocol currently in effect 6 When all of the data has been transferred the device generates an interrupt to the host 7 Host resets the slave DMA channel 8 Host reads the Status Register and optionally the Error Register 11 5 DMA Queued Commands These commands ar...

Page 102: ...m the device 3 Bus Release If the device is not ready for data transfer REL is set a The device generates an interrupt if release interrupt is enabled b The host may issue another command or wait for service request from the device 94 OEM Specifications for DTTA 3xxxxx ...

Page 103: ... 0 1 0 0 1 5 Read DMA Queued C7 1 1 0 0 0 1 1 1 1 Read Long retry 22 0 0 1 0 0 0 1 0 1 Read Long no retry 23 0 0 1 0 0 0 1 1 1 Read Multiple C4 1 1 0 0 0 1 0 0 3 Read Native Max LBA CYL F8 1 1 1 1 1 0 0 0 1 Read Sectors retry 20 0 0 1 0 0 0 0 0 1 Read Sectors no retry 21 0 0 1 0 0 0 0 1 3 Read Verify Sectors retry 40 0 1 0 0 0 0 0 0 3 Read Verify Sectors no retry 41 0 1 0 0 0 0 0 1 3 Recalibrate 1...

Page 104: ... 1 0 1 1 0 0 0 0 3 Standby E2 1 1 1 0 0 0 1 0 3 Standby 96 1 0 0 1 0 1 1 0 3 Standby Immediate E0 1 1 1 0 0 0 0 0 3 Standby Immediate 94 1 0 0 1 0 1 0 0 2 Write Buffer E8 1 1 1 0 1 0 0 0 4 Write DMA retry CA 1 1 0 0 1 0 1 0 4 Write DMA no retry CB 1 1 0 0 1 0 1 1 5 Write DMA Queued CC 1 1 0 0 1 1 0 0 2 Write Long retry 32 0 0 1 1 0 0 1 0 2 Write Long no retry 33 0 0 1 1 0 0 1 1 2 Write Multiple C5...

Page 105: ...ÄÄÄÄ ÄÄÄÄÄÄÄÄ ÄÄÄÄÄÄÄÄÄÄ Set Features Enable Write Cache EF 02 Set Transfer Mode EF 03 34 bytes of ECC apply on Read Write Long EF 44 Disable read lookÄahead feature EF 55 Enable release interrupt EF 5D Disable reverting to power on defaults EF 66 Disable write cache EF 82 Enable read lookÄahead feature EF AA 4 bytes of ECC apply on Read Wrtie Long EF BB Enable reverting to power on defaults EF CC...

Page 106: ...the Option Bit of the Sector Count Register should be specified This bit is used by Set Max LBA CYL command V Valid Indicates that the bit is part of an output parameter and should be specified x Indicates that the hex character is not used Indicates that the bit is not used Input Registers 0 Indicates that the bit is always set to 0 1 Indicates that the bit is always set to 1 H Head number Indica...

Page 110: ... Register Status Register ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ 0 0 0 V 0 V 0 0 0 V V V Ä 0 Ä V ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ Figure 77 Format Track Command 50h The Format Track...

Page 111: ...ecifies current LBA address bits 8 15 Low 16 23 High H In LBA mode this register specifies current LBA address bits 24 27 L 1 Error The Error Register An Abort error ABT 1 will be returned under the following condition No spare data sector to be assigned In LBA mode this command formats a single logical track including the specified LBA Command Descriptions 103 ...

Page 113: ...s in default translate mode 02 0 Number of removable cylinders 03 00xxH Number of heads in default translate mode 04 0 Reserved 05 0 Reserved 06 003FH Number of sectors per track in default translate mode 07 0000H Number of bytes of sector gap 08 0000H Number of bytes in sync field 09 0000H Reserved 10Ä19 XXXX Serial number in ASCII 0 not specified 20 0003H Controller type 0003 dual ported multipl...

Page 114: ...eads 56 xxxxH Number of current sectors per track 57Ä58 xxxxH Current capacity in sectors Word 57 specifies the low word of the capacity 59 0xxxH Current Multiple setting bit assignments 15Ä 9 0 Reserved 8 1 Multiple Sector Setting is Valid 7Ä 0 xxh Current setting for number of sectors 60Ä61 xxxxH Total Number of User Addressable Sectors Word 60 specifies the low word of the number 62 xx07H Singl...

Page 115: ...r 15Ä 0 11 ATA ATAPIÄ4 X3T13 1153D revision 17 82 74EBH Command set supported 15 0 Reserved 14 1 NOP command 13 1 READ BUFFER command 12 1 WRITE BUFFER command 11 0 Reserved 10 1 Host Protected Area feature set 9 0 DEVICE RESET command 8 0 SERVICE interrupt 7 1 RELEASE interrupt 6 1 LOOK AHEAD 5 1 WRITE CACHE 4 0 PACKET Command feature set 3 1 Power management feature set 2 0 Removable feature set...

Page 116: ...ture set 1 READ WRITE DMA QUEUED 0 DOWNLOAD MICROCODE command 87 4000H Command set feature default 15Ä14 01 Word 87 is valid 13Ä 0 0 Reserved 88 0x07H Ultra DMA transfer modes 15Ä 8 0x Current active Ultra DMA transfer mode 15Ä11 Reserved 0 10 Mode 2 1 Active 0 Not Active 9 Mode 1 1 Active 0 Not Active 8 Mode 0 1 Active 0 Not Active 7Ä 0 07 Ultra DMA transfer mode supported 7Ä 3 Reserved 0 2 Mode ...

Page 117: ...ed 3 Freeze 1 Frozen 2 Lock 1 Locked 1 Enable Disable 1 Enable 0 Capability 1 Support 129 xxxxH Current Set Feature Option Bit assignments 15Ä 4 Reserved 3 Auto reassign 1 Enable 2 Reverting 1 Enable 1 Read LookÄahead 1 Enable 0 Write Cache 1 Enable 130Ä159 xxxxH Reserved 160Ä255 0000H Reserved ÀÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ Figure 83 Identify device...

Page 119: ...ed the drive will enter Standby mode automatically if the timeout interval expires with no drive access from the host The timeout interval will be reinitialized if there is a drive access before the timeout interval expires Command Descriptions 111 ...

Page 124: ...ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Error Register Status Register ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ V 0 0 V 0 V 0 V 0 V 0 V Ä 0 Ä V ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄ...

Page 125: ...erred This will be zero unless an unre coverable error occurs Sector Number The sector number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the sector to be transferred L 0 In LBA m...

Page 127: ...n the device performs a bus release This bit is set to one when the device is ready to transfer data Input Parameters From The Device On Command Complete Sector Count bits 7 3 Tag contain the Tag of the completed command bit 2 REL is cleared to zero bit 1 I O is set to one bit 0 C D is set to one Sector Number Cylinder High Low H sector address of unrecoverable error applicable only when unrecov e...

Page 128: ...ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Error Register Status Register ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ 0 0 0 V 0 V 0 V 0 V 0 V Ä 0 Ä V ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁ...

Page 129: ...inder High Low The cylinder number of the transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 It should be noted that the device internally uses 34 bytes of ECC data on all data written or read from the disk The 4 byte mode of operation is pro...

Page 131: ...of the last transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 Command Descriptions 123 ...

Page 134: ...last transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 126 OEM Specifications for DTTA 3xxxxx ...

Page 136: ...ast transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 128 OEM Specifications for DTTA 3xxxxx ...

Page 138: ...ÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ 0 0 0 0 0 V 0 0 0 V 0 V Ä 0 Ä V ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ Figure 97 Security Disable Password Command F6h The Security Disable Password command disables the security mode f...

Page 140: ...ÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Error Register Status Register ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ 0 0 0 V 0 V 0 0 0 V 0 V Ä 0 Ä V ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄ...

Page 141: ...ated The secu rity erase prepare command should be completed immediately prior to the Security Erase Unit command If the device receives a Security Erase Unit command without a prior Security Erase Prepare command the device aborts the security erase unit command This command disables the security mode feature device lock function however the master password is still stored internally within the d...

Page 144: ...sword The text of the password all 32 bytes are always significant The setting of the Identifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will be enabled from the next power on The file may then be unlocked by either the user password or the p...

Page 145: ...ÄÄ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Error Register Status Register ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ 0 V 0 0 0 V 0 0 0 V 0 Ä Ä 0 Ä V ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ Figure 105...

Page 146: ...nlock Information Identifier Zero indicates that device regards Password as User Password One indicates that device regards Password as Master Password The user can detect if the attempt to unlock the device has failed due to a mismatched password as this is the only reason that an abort error will be returned by the file AFTER the password information has been sent to the device If an abort error...

Page 150: ...000 nnn nnn 000 001 010 Note 2 If the number of auto reassigned sector reaches the device s reassignment capacity the write cache function will be automatically disabled Although the device still accepts the Set Features command with Feature register 02h without error but the write cache function will remains disabled For current write cache function status please refer to Identify Device Informat...

Page 151: ...ÄÄÄÄÄÄÄ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Error Register Status Register ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ 0 0 0 0 0 V 0 0 0 V 0 Ä Ä 0 Ä V ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ Figur...

Page 152: ...ameters From The Device Sector Number In LBA mode this register contains max LBA bits 0 7 which is set L 1 In CHS mode this register contains max sector number L 0 Cylinder High Low In LBA mode this register contains max LBA bits 8 15 Low 16 23 High which is set L 1 In CHS mode this register contains max cylinder number which is set L 0 H In LBA mode this register contains max LBA bits 24 27 which...

Page 156: ...f F1h written by the host into the device s Sector Count Register before issuing the SMART Enable Disable Attribute Autosave subcommand will cause this feature to be enabled Any other non zero value written by the host into this register before issuing the SMART Enable Disable Attribute Autosave subcommand will not change the current Autosave status but the device will respond with the error code ...

Page 157: ...receipt of the SMART Disable Operations subcommand from the host the device disables S M A R T capabilities and functions and then saves any updated Attribute Values to the Attribute Data sector After receipt of the device of the SMART Disable Operations subcommand from the host all other S M A R T subcommands with the exception of SMART Enable Operations are disabled and invalid and will be abort...

Page 160: ...d bits Always 0 ÀÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ Figure 116 Status Flag Definitions 12 31 2 2 3 Normalized Values The device will perform conversion of the raw Attribute Values to trans form them into normalized values which the host can then compare with the Threshold values A Threshold is the excursion limit for a normalized Attribute Value In norma...

Page 161: ... indicating the next segment to execute as an off line data collection activity This varies from 00h to the total number of segments The current segment pointer will be 00h if the off line data collection has not been started If the off line data collection is aborted by a command or an error i e the status is 05h or 06h this byte will point to the aborted segment If the all segments complete this...

Page 166: ... 255 21 minutes 15 seconds When the automatic power down sequence is enabled the drive will enter Standby mode automatically if the timeout interval expires with no drive access from the host The timeout interval will be reinitialized if there is a drive access before the timeout interval expires 158 OEM Specifications for DTTA 3xxxxx ...

Page 169: ...ÄÄÄÄÄÁÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Error Register Status Register ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ 0 0 0 V 0 V 0 0 0 V V V Ä 0 Ä V ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄ...

Page 170: ...requested sectors not transferred This will be zero unless an unre coverable error occurs Sector Number The sector number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the last tran...

Page 172: ...evice performs a bus release This bit is set to one when the device is ready to transfer data Input Parameters From The Device On Command Complete Sector Count bits 7 3 Tag contain the Tag of the completed command bit 2 REL is cleared to zero bit 1 I O is set to one bit 0 C D is set to one Sector Number Cylinder High Low H sector address of unrecoverable error applicable only when unrecov erable e...

Page 173: ...ÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ Error Register Status Register ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ ÃÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄÂÄÄÄ 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ ÃÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄÅÄÄÄ 0 0 0 V 0 V 0 0 0 V V V Ä 0 Ä V ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ ÀÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÁÄÄÄÙ Figure 125 Writ...

Page 174: ...bits 8 15 Low 16 23 High L 1 H The head number of the sector to be transferred L 0 In LBA mode this register contains current LBA bits 24 27 L 1 The file internally uses 34 bytes of ECC on all data read or writes The 4 byte mode of operation is pro vided via an emulation technique As a consequence of this emulation it is recommended that 34 byte ECC mode is used for all tests to confirm the operat...

Page 176: ...last transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 168 OEM Specifications for DTTA 3xxxxx ...

Page 178: ...last transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder High Low The cylinder number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 8 15 Low 16 23 High L 1 H The head number of the last transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 170 OEM Specifications for DTTA 3xxxxx ...

Page 181: ...bsolete 33h WRITE LONG w o retry Yes Obsolete 34hÄ3Bh Reserved Reserved Reserved 3Ch WRITE VERIFY No Obsolete 3DhÄ3Fh Reserved Reserved Reserved 40h READ VERIFY SECTOR S w retry Yes Mandatory 41h READ VERIFY SECTOR S w o retry Yes Mandatory 42hÄ4Fh Reserved Reserved Reserved 50h FORMAT TRACK Yes Obsolete 51hÄ5Fh Reserved Reserved Reserved 60hÄ6Fh Reserved Reserved Reserved 70h SEEK Yes Mandatory 7...

Page 182: ...l Ä 2 E3h IDLE 1 Yes Optional Ä 2 E4h READ BUFFER Yes Optional E5h CHECK POWER MODE 1 Yes Optional Ä 2 E6h SLEEP 1 Yes Optional Ä 2 E7h FLUSH CACHE Yes Optional E8h WRITE BUFFER Yes Optional E9h WRITE SAME No Retired EAhÄEBh Reserved Reserved Reserved ECh IDENTIFY DEVICE Yes Mandatory EDh MEDIA EJECT No Optional Ä 5 EEh IDENTIFY DEVICE DMA No Obsolete EFh SET FEATURES Yes Optional F0h Vendor speci...

Page 183: ...try No Obsolete 44h Set vendor specific bytes ECC Yes Obsolete 54h Set cache segments No Obsolete 55h Disable read lookÄahead feature Yes Optional 5Dh Enable release interrupt Yes Optional 5Eh Enable SERVICE interrupt No Optional 66h Disable reverting to power on defaults Yes Optional 77h Disable ECC No Obsolete 81h Disable 8 bit data transfers No Retired 82h Disable write cache Yes Mandatory 84h ...

Page 184: ...176 OEM Specifications for DTTA 3xxxxx ...

Page 185: ...sable Password F6h 130 Security Erase Prepare F3h 131 Security Erase Unit F4h 132 Security Freeze Lock F5h 134 Security Set Password F1h 135 Security Unlock F2h 137 Seek 7xh 139 Service A2h 140 Set Features EFh 141 Set Max LBA CYL F9h 143 Set Multiple C6h 145 Sleep E6h 99h 146 Standby E2h 96h 157 Standby Immediate E0h 94h 159 Command continued Write Buffer E8h 160 Write DMA CAh CBh 161 Write DMA Q...

Page 186: ...1 Sector Number Register 71 Status Register 71 Register Initialization 74 Reset Diagnostic and Reset considerations 74 Register Initialization 74 RST 69 S S M A R T Function 79 Attribute thresholds 79 Attribute values 79 Attributes 79 S M A R T commands 79 Threshold exceeded condition 79 S M A R T Function Set 147 Sector Addressing Mode 75 LBA Addressing Mode 76 Logical CHS Addressing Mode 75 Secu...

Page 187: ...imeout Parameter 110 157 Timeout Values 171 TK0NF 70 U UNC 70 V V 98 W Write Buffer 90 160 Write Cache 87 Write DMA 92 161 Write DMA Queued 93 163 Write Long 90 165 Write Multiple 90 167 Write Sectors 90 169 WTG 69 X x 98 Index 179 ...

Page 188: ...Published in Japan S00K 0286 02 ...

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