IBM 8286-41A, Manual

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v PCIe3 USB controller
The two PCIe3 switches follow:
v PCIe3 Switch 1 that provides PCIe buses from Processor Module 1, Chip-0.
v PCIe3 Switch 2 that provides PCIe buses from Processor Module 1, Chip-1.
Table 7 lists the features provided by the PCIe3 switches.
Table 7. PCIe generation 3 switches in the system.
Features provided PCIe3 Switch 1 PCIe3 Switch 2
Lanes and ports 32-lane, 8-ports PCIe Gen3 48-lane, 12-ports PCIe Gen3
With integrated 8.0 gigatransfers per second (GTps)
Serializer/Deserializer (SerDes) speed negotiation, for each
port
Lane and polarity reversal Supported Supported
All ports support concurrent maintenance through
I2C bus Yes Yes
End-to-end cyclic redundancy check (CRC) and
Poison bit error checking Supported Supported
Data path parity Supported Supported
Memory error correction Supported Supported
Advanced error reporting Supported Supported
Aggregate full duplex bandwidth 512 GT/s 768 GT/s
Designate any port as the Upstream port Yes Yes
27x27 mm, 676-pin FCBGA package Yes Yes
Power consumption
v Nominal: 6 watts
v Maximum: 12 watts
v Nominal: 8 watts
v Maximum: 12 watts
Figure 2 on page 21 and Figure 3 on page 21 shows the rear view of the system with the location codes
for the PCIe adapter slots.
Table 8 on page 21 lists the PCIe adapter slot locations and details for the 8286-41A and 8286-42A system.
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Power Systems: PCIe adapter placement for the 8247-42L, 8286-41A, or 8286-42A