IBM 7944E2U User Manual Download Page 6

Page: 6 / 21

Leadership enterprise server with significantly lower cost of ownership in a highly available and
expandable, rack-dense, 1U dual-socket server

Please see the Legal Information section for important notices and information.

servers. For example, the Xeon 5500 and 5600 series processors

integrate the memory

controller inside the processor

, resulting in two memory controllers in a 2-socket system. Each

memory controller has three memory channels. Depending on the type of memory, population of
memory, and processor model, the memory may be clocked at

1333MHz

1066MHz

800MHz

Note:

If only one processor is installed, only the first nine DIMM slots can be used. Adding a

second processor not only doubles the amount of memory available for use, but also doubles the
number of memory controllers, thus doubling the system memory bandwidth. If you add a second
processor, but no additional memory for the second processor, the second processor would have
to access the memory from the first processor “remotely,” resulting in longer latencies and lower
performance. The latency to access remote memory is almost

75% higher

than local memory

access. So, the goal should be to always populate both processors with memory.

The

55xx,

5640, and

56xx processor models support up to 1333MHz memory clock speed.

With new single-rank and dual-rank RDIMMs and UDIMMs,

L5640

and

X56

xx processors support

2 DIMMs per channel (2DPC) at 1333MHz;

X55

xx processors can support 2DPC at 1333MHz via

the special bid process, otherwise 2DPC will drop the memory access rate to 1066MHz. The

x-and-up and

56xx models support a maximum of

1066MHz

clock speed (and thus

memory access rate), and the

x models support

800MHz

clock speed.

Using 1333MHz memory (where supported) versus 1066MHz offers up to

better

performance, while 1066MHz memory produces up to

28%

better performance than

800MHz

memory. Xeon 5550/5600 Series processors access memory with almost

50% lower latency

than the earlier 5400 Series processors. That can result in faster processing of latency-sensitive
workloads.

Regardless of memory

speed

, the Xeon 5500/5600 platform represents a significant improvement

in memory

bandwidth

over the previous Xeon 5400 platform. At 1333MHz, the improvement is

almost

500%

over the previous generation. This huge improvement is mainly due to the dual

integrated memory controllers and faster DDR3 1333MHz memory. Throughput at 800MHz is

gigabytes per second

(GBps); at 1066MHz it’s

32GBps

; and at 1333MHz it’s

35GBps

. This

improvement translates into improved application performance and scalability.

Memory interleaving refers to how physical memory is interleaved across the physical DIMMs. A
balanced system provides the best interleaving. A Xeon 5500/5600 processor-based system is
balanced when all memory channels on a socket have the same amount of memory.

The 5500 and 5600 Series processors support single-, dual-, and quad-rank memory. A memory
rank is simply a segment of memory that is addressed by a specific address bit.

•

A typical memory DIMM description is 4GB 2Rx4 DIMM

•

The 2R designator is the rank count for this particular DIMM (2R = dual-rank)

•

The x4 designator is the data width of the rank

It is important to ensure that DIMMs with the appropriate number of ranks are populated in each
channel for optimal performance. Whenever possible,

use dual-rank DIMMs

in the system. Dual-

rank DIMMs offer better interleaving and hence better performance than single-rank DIMMs. For
instance, a system populated with six 2GB

dual

-rank DIMMs outperforms a system populated