© Copyright IBM Corp. 2001, 2002
9
Chapter 2.
Architecture and technical
overview
The following sections provide more detailed information about the architecture of the Models
6C1 and 6E1. Figure 2-1 shows the high level system block diagram of both models.
Figure 2-1 Model 6C1 and 6E1 - high-level system block diagram
2
Integrated Service
Processor
PCI Bridge
PCI Bridge
External
Ultra3-SCSI
10/100
Ethernet
3rd serial
port
Super
I/O
ISA Bridge
2 PCI Slots
32 bit
33 MHz
5v
2 PCI Slots
64-bit
50 MHz
3.3v
System Planar
Data
Addr/Cntl
Memory Data Bus
Memory
Address
6xx Data Bus
6xx Address Bus
Memory
512 MB - 8 GB
Processor Card
POWER3-II
333 MHz,
375 MHz, or
450 MHz
4 MB L2
w/ 375 MHz
8 MB L2
w/ 450 MHz
Processor Card
POW ER3-II
4 MB L2
w/ 375 MHz
8 MB L2
w/ 450 MHz
SCSI Controller
Internal
Ultra3-SCSI
10/100
Ethernet
IDE
CD-
ROM
1 PCI Slots
64 bit
33 MHz
5v
16 Bytes @ 93.75 MHz w/ 375 MHz
16 Bytes @ 90.00 MHz w/ 450 MHz
16 Bytes @ 93.75 MHz w/ 375 MHz
16 Bytes @ 90.00 MHz w/ 450 MHz
6xx-MX Bus
66 MHz
250 MHz
w/ 375 MHz
225 MHz
w/ 450 MHz
250 MHz
w/ 375 MHz
225 MHz
w/ 450 MHz
4 MB L2
w/ 333 MHz
4 MB L2
w/ 333 MHz
333 MHz,
375 MHz, or
450 MHz
166.5 MHz
w/ 333 MHz
166.5 MHz
w/ 333 MHz
16 Bytes @ 95.14 MHz w/ 333 MHz
16 Bytes @ 95.14 MHz w/ 333 MHz
