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IBASE Technology MB835, User Manual

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IBASE Technology MB835 User Manual Download Page 21

INSTALLATION 

 
J15, J1, J2: COM2, COM3, COM4 Serial Port 

 

 
 

 

Pin #

Signal Name 

1 

DCD, Data carrier detect 

2 

RXD, Receive data 

3 

TXD, Transmit data 

4 

DTR, Data terminal ready 

5 Ground 
6 

DSR, Data set ready 

7 

RTS, Request to send 

8 

CTS, Clear to send 

9 

RI, Ring indicator 

 

J16: PCIE X4 Slot For IBP835 Gigabit LAN Add-on Card 
 
FAN1, FAN2, FAN3: CPU Fan & System Fan Power 
Connectors 

FAN1, FAN2, FAN3 is a 3-pin header for system fans. The fan must be 
a 12V (500mA). 

 

 

Pin #

Signal Name 

1 Ground 
2 +12V 
3 Rotation 

detection

 
DIMM0, DIMM1: DDR2 DIMM Socket 

 

MB835 supports two DDR2 DIMM sockets for a maximum memory of 
2GB, DDR2 400/533/667/800. 

Note:  
Used 600MHz processor will support DDR2 400/533/667MHz  
Used 1200MHz & 1066MHz processors will support DDR2 
400/533/667/800MHz.

 

 
 

(x1: One DIMM, x2: Two DIMM, DS: Double Side, SS: Single Side)  

 

 DIMM0 

DIMM1

x1 SS Memory Modules 

9

 X 

x1 DS Memory Modules 

9

 X 

x2 SS Memory Modules 

9

 

9

 

 

J1: PCIE X4 Slot (Signal only support PCIE X1) 

 

PCI1: PCI Slot 

 

                              MB835 User’s Manual 

17 

Summary of Contents for MB835

Page 1: ...MB835 Intel EP80579 Motherboard USER S MANUAL Version 1 0 ...

Page 2: ...al Business Machines Corporation Intel and Intel EP80579 Integrated Processor are registered trademarks of Intel Corporation Microsoft Windows is a registered trademark of Microsoft Corporation Winbond is a registered trademark of Winbond Electronics Corporation All other product names or trademarks are properties of their respective owners ...

Page 3: ...oduction 1 Product Description 1 Checklist 2 MB835 Specifications 3 Board Dimensions 5 Installations 7 Setting the Jumpers 8 Connectors on MB835 12 BIOS Setup 19 Drivers Installation 39 Appendix 41 Bypass and WDT 41 Watchdog Timer Configuration 43 ...

Page 4: ...iv MB835 User s Manual This page is intentionally left blank ...

Page 5: ...sor This low power IA 32 core is based on 90 nm process technology featuring 256 Kbyte L2 cache and 400 533 MHz quad pumped internal front side bus FSB With two DDR2 DIMM sockets on board the board supports up to 2GB of DDR2 system memory It integrates three Gigabit Ethernet MAC interfaces The MAC fully implements the IEEE 802 3z Carrier Sense Multiple Access with Collision Detection CSMA CD metho...

Page 6: ...anual Checklist Your ECX810 package should include the items listed below The MB835 Mother board This User s Manual 1 CD containing chipset drivers and flash memory utility Optional cables for Keyboard mouse Serial port Serial ATA ...

Page 7: ...rom PEX8112 PCI bus must be 32bit 66Mhz USB Intel EP80579 build in 2X USB2 0 host controller with 1x USB stack connector on edge connector SATA Intel EP80579 build in 2X SATA controller with 2XSATA onboard 7 pin shrouded vertical connector Compact flash PATA Jmicron JM368 PCIe to PATA bridge Connect from PCIeX1 bus of PEX8509 downstream Connect to onboard CF type II socket support UDMA mode LPC I ...

Page 8: ...f M B Connect to 4x Intel 82574L GbE Ethernet controller 4x onboard Intel 82574L GbE optional 2x GbE Connect from PCIeX1 bus of PEX8509 downstream Connect to RJ45 on edge connector Edge connector 4x RJ45 with LED connector Model ID835 Riser Card Form Factor Custom size Expansion slot M B side 1x PCI and 1x PCIeX1 slot connect from M B Expansion slot Top PCI slot for additional card Bottom PCIeX4 s...

Page 9: ...INSTALLATION Board Dimensions MB835 User s Manual 5 ...

Page 10: ...INSTALLATION 6 MB835 User s Manual This page is intentionally left blank ...

Page 11: ...ser s Manual 7 Installations This section provides information on how to use the jumpers and connectors on the MB835 in order to set up a workable system The topics covered are Setting the Jumpers 8 Connectors on MB835 12 ...

Page 12: ...plier if you have doubts about the best configuration for your needs The following lists the connectors on MB835 and their respective functions Jumper Locations on MB835 9 JP1 Clear CMOS Setting 10 JP2 AT Emulation ATX Power Selection 10 JP3 CF Card Master Slave Selection 10 JP4 JP5 Watchdog Timer LAN1 LAN2 Bypass Settings 11 JP6 JP7 Watchdog Timer LAN3 LAN4 Bypass Settings 11 ...

Page 13: ...ations on MB835 Page JP1 Clear CMOS Setting 10 JP2 AT Emulation ATX Power Selection 10 JP3 CF Card Master Slave Selection 10 JP4 JP5 Watchdog Timer LAN1 LAN2 Bypass Settings 11 JP6 JP7 Watchdog Timer LAN3 LAN4 Bypass Settings 11 MB835 User s Manual 9 ...

Page 14: ...ation ATX Power Selection JP2 Power Select AT Emulation ATX Note AT Emulation does not require pressing the power button to turn on the system plugging the AC power will turn on the system JP3 CF Card Master Slave Selection JP3 CF Card Setting Master Slave 10 MB835 User s Manual ...

Page 15: ...by SIO GPIO27 JP4 Pin 1 2 3 4 Closed JP5 Pin 1 2 Closed Default System will reboot upon the time out of watchdog timer JP6 JP7 Watchdog Timer LAN3 LAN4 Bypass Settings JP6 JP7 Setting Function JP7 Pin 1 2 3 4 Open JP6 Pin 1 2 Closed System will bypass LANs upon the time out of watchdog timer JP7 Pin 1 2 3 4 Open JP6 Pin 2 3 Closed System LANs bypass function controlled by SIO GPIO28 JP7 Pin 1 2 3 ...

Page 16: ...RJ45 RS 232 port 15 CN7 USB0 Port Connector 15 CN8 RJ45 Gigabit LAN Connectors 15 J5 SPI Pin Header Debug Only 15 J6 TDM T1 E1 Connector 15 J8 PCIE_1 PCI Slot and PCIE X1 slot for ID835 add on card 16 J10 Mini PCI Connector 16 J11 LPC 80 Port Pin Header Debug Use Only 16 J13 PS 2 Keyboard and Mouse Connector 16 J14 USB1 Connector 16 J15 J1 J2 COM2 COM3 COM4 Serial Port 17 J16 PCIE X4 Slot For IBP8...

Page 17: ...or 15 CN8 RJ45 Gigabit LAN Connectors 15 J5 SPI Pin Header Debug Only 15 J6 TDM T1 E1 Connector 15 J8 PCIE_1 PCI Slot And PCIE X1 Slot For ID835 Add on Card 16 J10 Mini PCI Connector 16 J11 LPC 80 Port Pin Header Debug Use Only 16 J13 PS 2 Keyboard and Mouse Connector 16 J14 USB1 Connector 16 J15 J1 J2 COM2 COM3 COM4 Serial Port 17 J16 PCIE X4 Slot For IBP835 Gigabit Lan Add on Card 17 FAN1 FAN2 F...

Page 18: ...lash Connector CN5 Front Side Bridge Board to ID370 Signal Name Pin Pin Signal Name PWR SW 1 2 GND Reset SW 3 4 GND Speaker 5 6 VCC VCC 7 8 VCC GND PWR LED 9 10 Pull up to VCC HDD LED 11 12 Pull up to VCC RELAY LED 13 14 Pull up to VCC GND 15 16 GND GND 17 18 GND GPO0 19 20 GPI0 GPO1 21 22 GPI1 GPO2 23 24 GPI2 GPO3 25 26 GPI3 GPO4 27 28 GPI4 GPO5 29 30 GPI5 GPO6 31 32 GPI6 GPO7 33 34 GPI7 VCC 35 3...

Page 19: ...conjunction with the four Intel 82574L Gigabit Ethernet controllers on the board J5 SPI Pin Header Debug Only J6 TDM T1 E1 Connector J6 The TDM interface for support up to 12 T1 E1 links Signal Name Pin Pin Signal Name 3 3V 1 2 Ground RX_CLK0 3 4 RX_CLK2 TX_CLK0 5 6 TX_CLK2 RX_FRAME0 7 8 RX_FRAME2 TX_FRAME0 9 10 TX_FRAME2 RX_DATA_IN0 11 12 RX_DATA_IN2 TX_DATA_OUT0 13 14 TX_DATA_OUT2 RX_CLK1 15 16 ...

Page 20: ...FRAME_N LAD2 5 6 3 3V LAD3 7 8 GND CLK33 9 10 Cut Pin J13 PS 2 Keyboard and Mouse Connector J13 a 10 pin header has functions for both keyboard and mouse Signal Name Pin Pin Signal Name N C 10 5 N C KB clock 9 4 Mouse clock KB data 8 3 Mouse data Vcc 7 2 Vcc Ground 6 1 Ground J14 USB1 Connector Signal Name Pin Pin Signal Name VCC 1 2 NC USB2 3 4 NC USB2 5 6 NC Ground 7 8 NC 16 MB835 User s Manual ...

Page 21: ...3 pin header for system fans The fan must be a 12V 500mA Pin Signal Name 1 Ground 2 12V 3 Rotation detection DIMM0 DIMM1 DDR2 DIMM Socket MB835 supports two DDR2 DIMM sockets for a maximum memory of 2GB DDR2 400 533 667 800 Note Used 600MHz processor will support DDR2 400 533 667MHz Used 1200MHz 1066MHz processors will support DDR2 400 533 667 800MHz x1 One DIMM x2 Two DIMM DS Double Side SS Singl...

Page 22: ...CONNECTOR LOCATIONS ON IBP835 CN1 RJ45 Gigabit LAN Connectors These four LAN LAN1 2 3 4 connectors are used in conjunction with the four Intel 82574L Gigabit Ethernet controllers on the board 18 MB835 User s Manual ...

Page 23: ...are as follows BIOS Introduction 20 BIOS Setup 20 Standard CMOS Setup 22 Advanced BIOS Features 25 Advanced Chipset Features 28 Integrated Peripherals 29 Power Management Setup 32 PNP PCI Configurations 35 PC Health Status 36 Frequency Voltage Control 37 Load Fail Safe Defaults 38 Load Optimized Defaults 38 Set Supervisor User Password 38 Save Exit Setup 38 Exit Without Saving 38 ...

Page 24: ...S is immediately activated Pressing the Del key immediately allows you to enter the Setup utility If you are a little bit late pressing the Del key POST Power On Self Test will continue with its test routines thus preventing you from invoking the Setup If you still wish to enter Setup restart the system by pressing the Reset button or simultaneously pressing the Ctrl Alt and Delete keys You can al...

Page 25: ...displays the control keys for this menu At the bottom of the Main Menu just below the control keys section there is another section which displays information on the currently highlighted item in the list Note If the system cannot boot after making and saving system changes with Setup the Award BIOS supports an override to the CMOS settings that resets your system to its default Warning It is stro...

Page 26: ...s Date mm dd yy Tue Jul 1 2008 Item Help Time hh mm ss 12 00 00 Menu Level IDE Channel 0 Master None Change the day month Year and century IDE Channel 0 Slave None IDE Channel 1 Master None IDE Channel 1 Slave None Video EGA VGA Halt On All Errors Base Memory 640K Extended Memory 1046528K Total Memory 1047552K At the bottom of the menu are the control keys for use on this menu If you need any help...

Page 27: ...ndary channels for connecting up to two IDE hard disks or other IDE devices Press Enter to configure the hard disk The selections include Auto Manual and None Select Manual to define the drive information manually You will be asked to enter the following items Capacity Capacity size of the hard disk drive Cylinder Number of cylinders Head Number of read write heads Precomp Write precompensation La...

Page 28: ...or not the system will halt if an error is detected during power up No errors The system boot will not be halted for any error that may be detected All errors Whenever the BIOS detects a non fatal error the system will stop and you will be prompted All But Keyboard The system boot will not be halted for a keyboard error it will stop for all other errors All But Diskette The system boot will not be...

Page 29: ...re Press Enter to configure the settings relevant to CPU Feature Hard Disk Boot Priority With the field there is the option to choose aside from the hard disks connected Bootable add in Cards which refers to other external devices Virus Warning If this option is enabled an alarm message will be displayed when trying to write on the boot sector or on the partition table on the disk CPU L1 and L2 Ca...

Page 30: ...ill generate only one instance When enabled you can set the two typematic controls listed next By default this field is set to Disabled Typematic Rate Chars Sec When the typematic rate is enabled the system registers repeated keystrokes speeds Settings are from 6 to 30 characters per second Typematic Delay Msec When the typematic rate is enabled this item allows you to set the time interval for di...

Page 31: ... multiple PCI bus configurations and improve future expandability The default setting is 1 4 OS Select for DRAM 64MB This option allows the system to access greater than 64MB of DRAM memory when used with OS 2 that depends on certain BIOS calls to access memory The default setting is Non OS 2 Small Logo EPA Show The EPA logo appears at the right side of the monitor screen when the system is boot u...

Page 32: ...lows caching of the system BIOS ROM at F000h FFFFFh resulting in better system performance However if any program writes to this memory area a system error may result Video BIOS Cacheable The Setting Enabled allows caching of the video BIOS ROM at C0000h F7FFFh resulting in better video performance However if any program writes to this memory area a system error may result Memory Hole At 15M 16M I...

Page 33: ...nsfer access On Chip Primary PCI IDE Enabled Enabled Menu Level IDE Primary Master PIO Auto IDE Primary Slave PIO Auto IDE Primary Master UDMA Auto IDE Primary Slave UDMA Auto On Chip Secondary PCI IDE Enabled IDE Secondary Master PIO Auto IDE Secondary Slave PIO Auto IDE Secondary Master UDMA Auto IDE Secondary Slave UDMA Auto On Chip Serial ATA Setting On Chip Serial ATA IDE Phoenix AwardBIOS CM...

Page 34: ...ansfer to or from the disk drive PIO Programmed Input Output allows the BIOS to communicate with the controller and CPU directly The system supports five modes numbered from 0 default to 4 which primarily differ in timing When Auto is selected the BIOS will select the best available mode IDE Primary Secondary Master Slave UDMA These fields allow your system to improve disk I O throughput to 33Mb s...

Page 35: ...N This field sets certain keys also known as hot keys on the keyboard that can be used as a switch to power on the system Onboard Serial Port ICH Serial Port These fields allow you to select the onboard serial and parallel ports and their addresses The default values for these ports are Onboard Serial Port 1 3F8 IRQ4 Onboard Serial Port 2 2F8 IRQ3 ICH Serial Port 1 3E8 IRQ5 ICH Serial Port 2 2E8 I...

Page 36: ... Alarm 0 Time hh mm ss Alarm 0 0 0 Reload Global Timer Events Primary IDE 0 Disabled Primary IDE 1 Disabled Secondary IDE 0 Disabled Secondary IDE 1 Disabled FDD COM LPT Port Disabled PCI PIRQ A D Disabled ACPI Function Enable this function to support ACPI Advance Configuration and Power Interface Power Management This field allows you to select the type of power saving management modes There are ...

Page 37: ...RQ used by the Modem By default the setting is 3 Suspend Mode When enabled and after the set time of system inactivity all devices except the CPU will be shut off HDD Power Down When enabled and after the set time of system inactivity the hard disk drive will be powered down while all other devices remain active Soft Off by PWRBTN This field defines the power off mode when using an ATX power suppl...

Page 38: ... Timer Events The HDD FDD COM LPT Ports and PCI PIRQ are I O events that can prevent the system from entering a power saving mode or can awaken the system from such a mode When an I O device wants to gain the attention of the operating system it signals this by causing an IRQ to occur When the operating system is ready to respond to the request it interrupts itself and performs the service ...

Page 39: ...ng is PCI Card Reset Configuration Data This field allows you to determine whether to reset the configuration data or not The default value is Disabled Resources Controlled by This PnP BIOS can configure all of the boot and compatible devices with the use of a PnP operating system such as Windows 95 PCI VGA Palette Snoop Some non standard VGA display cards may not show colors properly This field a...

Page 40: ...e 41 C 105 F FAN3 Speed 0 RPM FAN1 Speed 7031 RPM FAN2 Speed 0 RPM Vcore 1 30 V 12 V 12 34 V 1 8V 1 89V 5V 4 99 V 3 3V 3 15V VBAT V 3 15 V 5VSB V 5 31 V CPU Warning Temperature This field allows the user to set the temperature so that when the temperature is reached the system sounds a warning This function can help prevent damage to the system that is caused by overheating Temperatures Voltages T...

Page 41: ...etup Utility Frequency Voltage Control Auto Detect PCI Clk Disabled ITEM HELP Spread Spectrum Modulated Disabled Menu Level Auto Detect PCI Clk This field enables or disables the auto detection of the PCI clock Spread Spectrum Modulated This field sets the value of the spread spectrum The default setting is Disabled This field is for CE testing use only ...

Page 42: ...ssword message prompts on the screen Type the password up to eight characters in length and press Enter The system confirms your password by asking you to type it again After setting a password the screen automatically returns to the main screen To disable a password just press the Enter key when you are prompted to enter the password A message will confirm the password to be disabled Once the pas...

Page 43: ... Area Network CAN interfaces as well as internal processor items such as Enhanced Direct Memory Access EDMA Because the core of the Intel EP80579 Integrated Processor is based on Intel architecture operating systems currently supporting Intel architecture will function without this software package For the most recent software package updates from Intel please visit downloadcenter intel com The fo...

Page 44: ...DRIVERS INSTALLATION 40 MB835 User s Manual This page is intentionally left blank ...

Page 45: ...5 B Relays RJ45 A CN2 WDT GPIO Communication States There are two communications states for the bypass function 1 Normal State 2 Bypass State A watchdog timer WDT or a GPIO are used to control and switch the communication between the two states The block diagram in the section above shows the Normal State where the two Ethernet ports work independently The following diagram shows the Bypass State ...

Page 46: ...APPENDIX 42 MB835 User s Manual I O Command Relays are Dis energized Driver Relay Bypass State Ethemet 2 Ethemet 1 Bypass RJ45 B Relays RJ45 A CN2 WDT GPIO ...

Page 47: ...PLE CODE THIS CODE AND INFORMATION IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND OR FITNESS FOR A PARTICULAR PURPOSE include stdio h include stdlib h include W627EHG H int main int argc char argv void copyright void void EnableWDT int void DisableWDT void int main int argc char argv unsigned cha...

Page 48: ...igned char bBuf bBuf Get_W627EHG_Reg 0x2D bBuf 0x01 Set_W627EHG_Reg 0x2D bBuf Enable WDTO Set_W627EHG_LD 0x08 switch to logic device 8 Set_W627EHG_Reg 0x30 0x01 enable timer bBuf Get_W627EHG_Reg 0xF5 bBuf 0x08 Set_W627EHG_Reg 0xF5 bBuf count mode is second Set_W627EHG_Reg 0xF6 interval set timer void DisableWDT void Set_W627EHG_LD 0x08 switch to logic device 8 Set_W627EHG_Reg 0xF6 0x00 clear watch...

Page 49: ...result unsigned char ucDid W627EHG_BASE 0x2E result W627EHG_BASE ucDid Get_W627EHG_Reg 0x20 if ucDid 0x88 goto Init_Finish W627EHG_BASE 0x4E result W627EHG_BASE ucDid Get_W627EHG_Reg 0x20 if ucDid 0x88 goto Init_Finish W627EHG_BASE 0x00 result W627EHG_BASE Init_Finish return result void Unlock_W627EHG void outportb W627EHG_INDEX_PORT W627EHG_UNLOCK outportb W627EHG_INDEX_PORT W627EHG_UNLOCK void L...

Page 50: ... INFORMATION IS PROVIDED AS IS WITHOUT WARRANTY OF ANY KIND EITHER EXPRESSED OR IMPLIED INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND OR FITNESS FOR A PARTICULAR PURPOSE ifndef __W627EHG_H define __W627EHG_H 1 define W627EHG_INDEX_PORT W627EHG_BASE define W627EHG_DATA_PORT W627EHG_BASE 1 define W627EHG_REG_LD 0x07 define W627EHG_UNLOCK 0x87 define W627EHG_LOCK 0xAA uns...

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