CV-M40
- 5 -
5.3. Input and Output Circuits
In the following schematic diagrams the input and output circuits for video and timing signals
are shown.
Video output
The video output is a 75
Ω
DC coupled
circuit. The video DC level for video and
video + sync is shown with 75
Ω
termination.
DC level with
75
Ω
termination
GND
#4/12
75
Video
Output
FL
CXA
1310
300 mV
470 mV
BNC
DC level with
75
Ω
termination
GND
#4/12
75
Video
Output
FL
CXA
1310
300 mV
470 mV
BNC
The vertical composite sync is with
serration and equalize pulses.
Fig. 4. Video output.
HD, VD and Trigger input
GND
+5V
33k
TTL
1k
100n
1k
HD VD
Trigger
input
33k
100k
1n
JP
75
GND
+5V
33k
TTL
1k
100n
1k
HD VD
Trigger
input
33k
100k
1n
JP
75
The inputs are AC coupled. To allow
longer pulse width, the input circuit is
a flip flop, which is toggled by the
negative or positive differentiated spikes
caused by the falling and rising edge.
The input is TTL as factory setting.
It can be 75
Ω
terminated by jumper.
As factory setting HD and VD are input.
Warning!
In trigger modes, the HD and VD
input circuits are used as trigger inputs.
Do not connect signal not used for the
actual trigger mode.
Fig. 5. HD, VD and Trigger input.
HD, VD, WEN and PCLK output
GND
10
10
10k
10k
67
TTL
220
GND
10
10
10k
10k
67
TTL
220
Output circuit for HD, VD, WEN and pixel clock
is TTL through emitter follower with 75
Ω
in series.
Output level
≥
4 V from 75
Ω
. (Non-terminated).
WEN active polarity is positive 1H. It can be changed
to be active low. The WEN timing then depend of
the actual mode. Refer to timing diagrams.
If not used, the pixel clock should be disabled.
Fig. 6. HD, VD, WEN and PCLK output.
