I-Bus IBC 2606, User Manual

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8 IBC 2606 User's Guide
1.2 Specifications
Standard SBC Functions
• CPU: Socket 370 Pentium
®
III Coppermine CPU up to 850 MHz
Socket 370 Celeron
TM
CPU up to 566 MHz
• BIOS: Award 2 Mb flash memory
• Chipset: Intel
®
440BX Chipset
• Front Side Bus Clock: 100 MHz for Intel
®
Pentium
®
III CPU 66 MHz for Celeron
TM
CPU
• Bus Interface: 32-bit, 33 MHz, PICMG 2.0 compliant
• 2nd level cache: CPU built-in 256 KB (Pentium
®
III) or 128 KB (Celeron
TM
) on die
• RAM: Two 144-pin SO-DIMM sockets. Support PC-100 SDRAMs with memory capacity up to
512 MB. Support ECC.
• Enhanced IDE interface: Two channels handles up to 4 IDE HDDs or other IDE devices via J3
connector. Supports PIO mode 4 and Ultra DMA/33 mode.
• Floppy disk drive interface: Supports up to two floppy disk drives through the J3 connector
• Serial ports: Two RS-232 ports with 16C550 compatible UARTs
• USB interface: One USB connector with fuse protection. Complies with USB specification 1.0
• Keyboard/mouse connectors: One 6-pin mini-DIN connector on the front panel
• Watchdog timer: Can generate a system reset. Software enabled/disabled. Time interval is from
1 to 63 seconds, jumperless with run-time setup.
PCI-to-PCI Bridge
• Controller chip: One (IBC 2606) Intel
®
DEC 21150 controller chip, drives up to 7/14 PCI master
peripherals
• Drives bus segment through J1 and J2 connectors
• Supports up to seven bus masters
• Provides seven pairs of GNT# and REQ# signals
10/100Base-TX Ethernet Interface
• Controller chips: Two Intel 82599 Fast Ethernet controller chips
• Dual LAN ports
• 10 Mbps or 100 Mbps auto-switching