Hytera MD652, Service Manual

Page: 134 / 207

Circuit Description
VHF1 (136
‐
174 MHz)
26
Receiver Back-end
The first IF signal (44.85 MHz) output by the IF amplifier goes into IF IC via Pin 47, where the signal is
converted to the second IF signal (2.25 MHz). Then the un-demodulated digital I/Q signal output from
the SSI interface is sent to U1002 for demodulation. IF IC employs a reference frequency of 19.2 MHz
and it shares the crystal with U1002 and U8001. The second LO VCO consists of the external transistor,
varactor and relevant components, to provide the second LO signal. The 18 MHz clock frequency is
generated by the LC (D6002, L6021, C6047 and C6054) resonance loop circuit. DSP (U1002) acquires
the audio signal from IF IC (U6001). Then this signal goes through U1002 to output data signal, which is
sent to U3001 and Pin 44 (SSI_DI) for digital-to-analog conversion.
5.3.3
Frequency Generation Unit (FGU)
PLL Synthesizer
The PLL synthesizer that consists of the reference oscillator (X8001), PLL IC (U8001) and VCO, is
utilized to supply excitation signal source to the transmitter, and local oscillator signal to the receiver.
Reference Crystal Oscillator
Reference crystal oscillator (X8001) employs a 19.2 MHz TCXO, and its reference frequency is
calibrated by the digital-to-analog converter IC (U8004) for accuracy.
PLL IC
The PLL IC (U8001) employs a fractional frequency divider IC. The logic switch ICs (U8002 and U8003)
work with the PLL IC (U8001) to achieve locking.