Huawei G530 V2, White Paper

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PCIe
Device CPU PCIe
Stand
ard Conn
ector
Band
width Bus
Band
width Port
Num
ber Root
Port
B/D/F Devic
e
B/D/F Slot Size
Riser 4
slot 2 CPU 1 PCIe
3.0
x16 x8 Port
2A 3a/00/0 54/00/0 Half-
height
half-
length
single-slot
Riser 4
slot 3 CPU 1 PCIe
3.0
x16 x8 Port
2A 3a/00/0 51/00/0 Half-
height
half-
length
single-slot
Riser 4
slot 4 CPU 1 PCIe
3.0
x16 x8 Port
2A 3a/00/0 52/00/0 Half-
height
half-
length
single-slot
Expansion
slot CPU 1 PCIe
3.0
x16 x8 Port
2A 3a/00/0 3e/00/0 Full-
height
full-length
single-slot
I/O slots 1
and 3 CPU 1 PCIe
3.0
x16 x16 Port
2A 3a/00/0 41/00/0
41/00/1 Half-
height
half-
length
single-slot
I/O slots 2
and 4 CPU 2 PCIe
3.0
x16 x16 Port
2A ae/00/0 b5/00/0
b5/00/1 Half-
height
half-
length
single-slot
NOTE
l
The expansion slot and riser 3 slot 1 cannot be enabled at the same time. Only one of the two slots
can be enabled by software programming. By default, the expansion slot is disabled.
l The preceding B/D/F information is the system default configuration. If PCIe cards with the PCI
bridge function are configured, the B/D/F allocation result will change.
l The B/D/F allocation result of an I/O card with two ports is used as an example. Each port
corresponds to one B/D/F allocation result.
Huawei G5500 Server G530 V2 Compute Node
White Paper
2 About the G530 V2 and GP316
Issue 03 (2018-02-12) Huawei Proprietary and Confidential
Copyright © Huawei Technologies Co., Ltd.
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