64
2 System Board
Host Bus
Host Bus
The Host bus of the Pentium III processors, also referred to as the FSB
(Front Side Bus), is implemented in the AGTL (Assisted Gunning
Transceiver Logic)+ technology. This technology features open-drain signal
drivers that are pulled-up to 1.5 V through resistors at bus extremities;
these resistors also act as bus terminators, and are integrated in the
processor.
If only one processor is installed, a processor terminating card must be
installed in the second processor slot.
The supported operating frequencies of the AGTL+ bus are 100 MHz or
133 MHz. The width of the data bus is 64 bits, while the width of the address
is 36 bits. Along with the operating frequencies, the processor voltage is set
automatically.
The control signals of the Host bus allow the implementation of a
“split -
transaction”
bus protocol. This allows the Pentium III processor to send its
request (for example, for the contents of a given memory address) and then
to release the bus, rather than waiting for the result, thereby allowing it to
820
Memory
Controller Hub
(MCH)
82820
Direct Rambus
channel
Address (36)
Control
Data (64)
AGP
4x Bus
Intel Pentium III
Processor
(optional second processor)
with L2 cache memory
FC-PGA Package
FC-PGA Package
Host (also called FSB) two-
way Bus (100/133 MHz,
1 GB/s data transfer rate)
HUB LINK 8
Intel Pentium III
Processor
with L2 cache memory
I/O Controller
Hub
(ICH) 82801AA
Two onboard RIMM sockets
supporting RDRAM memory.
