HP Kayak XU700, Technical Reference Manual

Page: 45 / 124

45
2 System Board
The Input/Output Controller Hub 2 (82801BA)
AC’97 Controller
This is the single-chip CS4299 audio controller that provides full audio
features for the Kayak XU700.
Refer to page 46 for information about the CS4299 audio solution.
IDE Controller
The IDE controller is implemented as part of the ICH2 chip and has PCI-
Master capability. Two independent ATA/100 IDE channels are provided
with two connectors per channel. Two IDE devices (one master and one
slave) can be connected per channel. In order to guarantee data transfer
integrity, Ultra-ATA cables must be used for Ultra-ATA modes (Ultra-ATA/33,
Ultra-ATA/66 and Ultra-ATA/100).
The PIO IDE transfers of up to 14 Mbytes/sec and Bus Master IDE transfer
rates of up to 66 Mbytes/sec are supported. The IDE controller integrates
16 x 32-bit buffers for optimal transfers.
It is possible to mix a fast and a slow device, such as a hard disk drive and a
CD-ROM, on the same channel without affecting the performance of the fast
device. The BIOS automatically determines the fastest configuration that
each device supports.
DMA Controller
The seven-channel DMA controller incorporates the functionality of two
82C37 DMA controllers. Channels 0 to 3 are for 8-bit count-by-byte
transfers, while channels 5 to 7 are for 16-bit count-by-word transfers (refer
to table on
page 93 for allocated DMA channel allocations). Any two of the
seven DMA channels can be programmed to support fast Type-F transfers.
The ICH2 DMA controller supports the LPC (Low Pin Count) DMA. Single,
Demand, Verify and Incremental modes are supported on the LPC interface.
Channels 0-3 are 8-bit, while channels 5-7 are 16-bit. Channel 4 is reserved
as a generic bus master request.
Interrupt Controller
The Interrupt controller is equivalent in function to the two 82C59 interrupt
controllers. The two interrupt controllers are cascaded so that 14 external
and two internal interrupts are possible. In addition, the ICH2 supports a
serial interrupt scheme and also implements the I/O APIC controller. A table
on
page 59 shows how the master and slave controllers are connected.