2BCPU 29
Table 3-4
Class: HP_ProcessorCore
Property name
Property implementation
•
0 (Unknown)
OperationalStatus
•
2 (OK), when CPU is enabled and operational
•
5 (Predictive Failure), when IML error information is
logged for this CPU
•
6 (Error), when CPU is disabled through POST
error
•
10 (Stopped), when CPU is disabled through RBSU
StatusDescriptions StatusDescriptions[0] text per OperationalStatus[0]:
•
Processor-module status unknown.
•
Processor-module status OK
•
Processor-module is degraded, it is predicted to Fail
•
Processor-module in Slot:
a
Socket:
b
disabled by
BIOS (POST Error), where
a
is the slot number and
b
is the socket number
•
Processor-module in Slot:
a
Socket:
b
disabled by
User through BIOS Setup, where
a
is the slot
number and
b
is the socket number
•
0 (Unknown), when OperationalStatus[0]=0
(Unknown)
HealthState
•
5 (OK), when OperationalStatus[0]=2 (OK)
•
15 (Minor Failure), when OperationalStatus[0]=10
(Stopped)
•
20 (Major Failure), when OperationalStatus[0]=5
(Predictive Failure)
•
25 (Critical Failure), when OperationalStatus[0]=6
(Error)
CIM_LogicalElement
CIM_EnabledLogicalElement
EnabledState 2
(Enabled)
RequestedState
12 (Not Applicable)
EnabledDefault 2
(Enabled)
CIM_ProcessorCore
InstanceID HPQ:HP_ProcessorCore:
n
, where n is a unique,
sequentially-assigned number in the form 001, 002,
and so on.
•
0 (Unknown)
CoreEnabledState
•
1 (DMTF Reserved)
•
2 (Core Enabled)
•
3 (Core Disabled)
•
4 (Core Disabled by User)
•
5 (Core Disabled by POST Error)