HP HP 8753E, Service Manual, Page: 461 / 612

Source High Band Operation
The high band frequency range is 16 MHz to 3.0 or 16 MHz to 6.0 with
Option 006. These frequencies are generated in subsweeps by phase-locking the
source signal to harmonic multiples of the fractional-N VCO. The high band
sequence, in 12-5, follows these steps:
1. A OUT) is generated
by the fractional-N VCQ. The
VCO in
the fractional-N assembly generates a CW or swept signal in the range
of 30 to MHz. This signal is synthesized and phase locked to a 100
reference signal from the reference assembly. The signal from the
fractional-N VCO is divided by 1 or 2, and goes to the pulse generator.
2. A comb
of harmonics
LO) is produced the pulse generator.
The divided down signal from the fractional-N VCO drives a step recovery
diode (SRD) in the pulse generator assembly. The SRD multiplies
the fundamental signal from the fractional-N into a comb of harmonic
frequencies The harmonics are used as the LO (local oscillator) signal to
the samplers One of the harmonic signals is 1 MHz below the start signal set
from the front panel.
3. The source is pretuued. The source output is fed to the sampler.
The DAC in the All phase lock assembly sets the source to a
approximation frequency (1 to 6 MHz higher than the start frequency). This
signal (RF OUT) goes to the R input sampler/mixer assembly.
4. The synthesizer and the source signal are combined by the
sampler. A difference frequency
is
generated.
In the sampler, the
LO signal from the pulse generator is combined with the source output signal.
The (intermediate frequency) produced is a approximation of 1 MHz.
This signal IF’) is routed back to the A11 phase lock assembly.
5. The difference frequency IF’) from the sampler is compared to a
reference.
The IF feedback signal from the is filtered and applied to
a phase comparator circuit in the A11 phase lock assembly. The other input
to the phase comparator is a crystal controlled 1 MHz signal from the
reference assembly. Any frequency difference between these two signals
produces a proportional error voltage.
6. A tunes the source and phase lock is achieved.
The error voltage is used to drive the source YIG oscillator, in order to
bring it closer to the required frequency. The loop process continues until
the IF feedback signal to the phase comparator is equal to the 1 MHz
reference signal, and phase lock is achieved.
Theory of Operation 12-18