HP HP 8753E, Service Manual, Page: 458 / 612

Source Low Band Operation
The low band frequency range is 300 to 16 MHz. These frequencies are
generated by locking the source to a reference signal. The reference signal
is synthesized by mixing down the fundamental output of the fractional-N
with a 40 MHz crystal reference signal. Low band operation differs from high
band in these respects: The reference frequency for the All phase lock is not
a 1 MHz signal, but varies with the frequency of the fractional-N
signal. The sampler diodes are biased on to pass the signal through to the mixer.
The IF signal from the sampler is not fixed but is identical to the source
output signal and sweeps with it. The following steps outline the low band
sweep sequence, illustrated in Figure 12-4.
1. A LO)
is generated by the fractional-N VCO. The
VCO in the
assembly generates a
CW
or swept signal that is 40 MHz
greater than the start frequency. The signal is divided down to 100 and
phase locked in the assembly, as in high band operation.
2. The fractional-N VCO is mixed with 40 to produce a
reference
signal. The signal LO) from the Fractional-N VCO goes to the
reference assembly, where it is mixed with the 40 MHz VCXO (voltage
controlled crystal oscillator). The resulting signal is the reference to the
phase comparator in the All assembly.
3. The source is pretuned. The source output is fed to the sampler.
The pretuned DAC in the All phase lock assembly sets the source to a
frequency 1 to 6 MHz above the start frequency. This signal (source output)
goes to the R input sampler/mixer assembly.
4. The from the source is fed back IF’) to the phase comparator.
The source output signal passes directly through the sampler in the
assembly, because the sampler is biased on. The signal is fed back
unaltered to the phase comparator in the All phase lock assembly. The other
input to the phase comparator is the heterodyned reference signal from the
assembly. Any frequency difference between these two signals produces
a proportional error voltage.
5.
A tuning signal
DRIVE) the source
and lock is achieved.
The error voltage is used to drive the source YIG oscillator to bring the
YIG closer to the reference frequency. The loop process continues until the
source frequency and the reference frequency are the same, and phase lock
is achieved.
12-16 Theory of Operation