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1-308

Package Characteristics

Parameter

Sym.

Device

Min.

Typ.*

Max.

 Units

 Test Conditions

Fig.

Note

Input-Output

V

ISO

2500

V rms

RH 

50%,

3, 13

Momentary

t = 1 min.,

Withstand Voltage**

T

A

 = 25

°

C

Input-Output

R

I-O

10

12

V

I-O

 = 500 Vdc

3

Resistance

Input-Output

C

I-O

0.6

pF

f = 1 MHz

Capacitance

V

I-O

 = 0 Vdc

Input-Input

I

I-I

2430

0.005

µ

A

RH 

45%

8

Insulation Leakage

t = 5 s,

Current

V

I-I

 = 500 Vdc

Resistance

R

I-I

2430

10

11

V

I-I

 = 500 Vdc

8

(Input-Input)

Capacitance

C

I-I

2430

0.25

pF

f = 1 MHz

8

(Input-Input)

*

All typical values are at T

A

 = 25

°

C.

**The Input-Output Momentary Withstand Voltage is a dielectric voltage rating that should not be interpreted as an input-output
continuous voltage rating. For the continuous voltage rating refer to the VDE 0884 Insulation Related Characteristics Table (if
applicable), your equipment level safety specification or HP Application Note 1074 entitled “Optocoupler Input-Output Endurance
Voltage,” publication number 5963-2203E.

Notes:

1. Each channel.
2. Duration of output short circuit time

not to exceed 10 ms.

3. Device considered a two terminal

device: pins 1, 2, 3, and 4 shorted
together, and pins 5, 6, 7, and 8
shorted together.

4. t

PHL

 propagation delay is measured

from the 50% level on the rising edge
of the input current pulse to the 1.5 V
level on the falling edge of the output
pulse. The t

PLH 

propagation delay is

measured from the 50% level on the
falling edge of the input current pulse
to the 1.5 V level on the rising edge of
the output pulse.

5. The typical data shown is indicative of

what can be expected using the
application circuit in Figure 13.

6. This specification simulates the worst

case operating conditions of the
HCPL-2400 over the recommended
operating temperature and V

CC 

range

with the suggested application circuit
of Figure 13.

7. Propagation delay skew is discussed

later in this data sheet.

8. Measured between pins 1 and 2

shorted together, and pins 3 and 4
shorted together.

9. Common mode transient immunity in a

Logic High level is the maximum
tolerable (positive) dV

CM

/dt of the

common mode pulse, V

CM

, to assure

that the output will remain in a Logic
High state (i.e., V

O

 > 2.0 V. Common

mode transient immunity in a Logic
Low level is the maximum tolerable
(negative) dV

CM

/dt of the common

mode pulse, V

CM

, to assure that the

output will remain in a Logic Low state
(i.e., V

O

 < 0.8 V).

10. Power Supply Noise Immunity is the

peak to peak amplitude of the ac ripple
voltage on the V

CC

 line that the device

will withstand and still remain in the
desired logic state. For desired logic
high state, V

OH(MIN

) > 2.0 V, and for

desired logic low state,
V

OL(MAX) 

< 0.8 V.

11. Use of a 0.1 

µ

F bypass capacitor

connected between pins 8 and 5
adjacent to the device is required.

12. Peak Forward Input Current pulse

width < 50 

µ

s at 1 KHz maximum

repetition rate.

13. In accordance with UL 1577, each

optocoupler is proof tested by applying
an insulation test voltage 

3000 V rms

for one second (leakage detection
current limit, I

I-O

 

 5 

µ

A). This test is

performed before the 100% Produc-
tion test shown in the VDE 0884
Insulation Related Characteristics
Table, if applicable.

Summary of Contents for HCPL-2400

Page 1: ...CPL 5430 1 20 MBd High CMR Logic Gate Optocouplers Technical Data HCPL 2400 HCPL 2430 Applications Isolation of High Speed Logic Systems Computer Peripheral Interfaces Switching Power Supplies Isolated Bus Driver Networking Applications Ground Loop Elimination High Speed Disk Drive I O Digital Isolation for A D D A Conversion Pulse Transformer Replacement Functional Diagram CAUTION It is advised t...

Page 2: ... The electrical and switching characteristics of the HCPL 2400 and HCPL 2430 are guaranteed over the temperature range of 0 C to 70 C These optocouplers are compatible with TTL STTL LSTTL and HCMOS logic families When Schottky type TTL devices STTL are used a data rate performance of 20 MBd over temperature is guaranteed when using the application circuit of Figure 13 Typical data rates are 40 MBd...

Page 3: ...0 NOT MARKED Package Outline Drawings 8 Pin DIP Package HCPL 2400 HCPL 2430 8 Pin DIP Package with Gull Wing Surface Mount Option 300 HCPL 2400 HCPL 2430 0 635 0 25 0 025 0 010 12 NOM 9 65 0 25 0 380 0 010 0 635 0 130 0 025 0 005 7 62 0 25 0 300 0 010 5 6 7 8 4 3 2 1 9 65 0 25 0 380 0 010 6 350 0 25 0 250 0 010 1 016 0 040 1 194 0 047 1 194 0 047 1 778 0 070 9 398 0 370 9 906 0 390 4 826 0 190 TYP...

Page 4: ...ut Tracking External terminals shortest distance path along body Creepage Minimum Internal 0 08 mm Through insulation distance conductor to Plastic Gap conductor usually the direct distance between the Internal Clearance photoemitter and photodetector inside the optocoupler cavity Tracking Resistance CTI 200 Volts DIN IEC 112 VDE 0303 Part 1 Comparative Tracking Index Isolation Group IIIa Material...

Page 5: ...t Voltage Method a VIORM x 1 5 VPR Type and sample test VPR 945 V peak tm 60 sec Partial Discharge 5 pC Highest Allowable Overvoltage Transient Overvoltage tini 10 sec VIOTM 6000 V peak Safety Limiting Values Maximum values allowed in the event of a failure also see Figure 12 Thermal Derating curve Case Temperature TS 175 C Input Current IS INPUT 230 mA Output Power PS OUTPUT 600 mW Insulation Res...

Page 6: ...0 V Output Voltage VO 0 5 18 V Output Collector Power Dissipation PO 40 mW Each Channel Total Package Power Dissipation PT 350 mW Each Channel Lead Solder Temperature 260 C for 10 sec 1 6 mm below seating plane for Through Hole Devices Reflow Temperature Profile See Package Outline Drawings section Option 300 Recommended Operating Conditions Parameter Symbol Minimum Maximum Units Power Supply Volt...

Page 7: ...6 mA VCC 5 25 V VE 0 V IO Open 2430 34 46 VCC 5 25 V IO Open Logic High Supply ICCH 2400 17 26 mA VCC 5 25 V VE 0 V Current IO Open 2430 32 42 VCC 5 25 V IO Open High Impedance State ICCZ 2400 22 28 mA VCC 5 25 V VE 5 25 V Supply Current High Impedance State IOZL 2400 20 µA VO 0 4 V VE 2 V IOZH 20 µA VO 2 4 V IOZH 100 µA VO 5 25 V Logic Low Short Circuit IOSL 52 mA VO VCC 5 25 V 2 Output Current I...

Page 8: ...7 mA 5 8 6 Distortion 5 25 Propagation Delay tPSK 35 ns Per Notes Text 15 16 7 Skew Output Rise Time tr 20 ns 5 Output Fall Time tf 10 ns 5 Output Enable Time tPZH 2400 15 ns 9 10 to Logic High Output Enable Time tPZL 2400 30 ns 9 10 to Logic Low Output Disable Time tPHZ 2400 20 ns 9 10 from Logic High Output Disable Time tPLZ 2400 15 ns 9 10 from Logic Low Logic High Common CMH 1000 10 000 V µs V...

Page 9: ...ng edge of the output pulse 5 The typical data shown is indicative of what can be expected using the application circuit in Figure 13 6 This specification simulates the worst case operating conditions of the HCPL 2400 over the recommended operating temperature and VCC range with the suggested application circuit of Figure 13 7 Propagation delay skew is discussed later in this data sheet 8 Measured...

Page 10: ...agation Delay vs Input Forward Current Figure 8 Typical Pulse Width Distortion vs Ambient Temperature Figure 5 Test Circuit for tPLH tPHL tr and tf Figure 1 Typical Logic Low Output Voltage vs Logic Low Output Current Figure 2 Typical Logic High Output Voltage vs Logic High Output Current Figure 3 Typical Output Voltage vs Input Forward Current ...

Page 11: ...d Typical Waveforms Figure 12 Thermal Derating Curve Dependence of Safety Limiting Value with Case Temperature per VDE 0884 OUTPUT POWER P S INPUT CURRENT I S 0 0 TS CASE TEMPERATURE C 200 50 400 125 25 75 100 150 600 800 200 100 300 500 700 PS mW IS mA 175 0 1 µF VFF F I CC V GND NC NC CM V 7 5 6 8 2 3 4 1 C 15 pF A B PULSE GENERATOR L CC V OUTPUT V MONITORING NODE O HCPL 2400 11 ...

Page 12: ...mended 20 MBd HCPL 2400 30 Interface Circuit Applications Figure 14 Alternative HCPL 2400 30 Interface Circuit Figure 16 Parallel Data Transmission Example Figure 17 Modulation Code Selections Figure 18 Typical HCPL 2400 30 Output Schematic DATA t PSK INPUTS CLOCK DATA OUTPUTS CLOCK t PSK HCPL 2400 HCPL 2400 V ...

Page 13: ...or tPHL As mentioned earlier tPSK can determine the maximum parallel data transmission rate Figure 16 is the timing diagram of a typical parallel data application with both the clock and the data lines being sent through optocouplers The figure shows data and clock signals at the inputs and outputs of the optocouplers To obtain the maximum data transmission rate both edges of the clock signals are...

Page 14: ... worst case switching parameters given in the data sheet can be met using common 74LS TTL invert ing gates or buffers Use of faster TTL families will slightly reduce the overall propagation delays from the input of the drive circuit to the output of the optocoupler but will not necessarily result in lower pulse width distortion or propagation delay skew This reduction in overall propagation delay ...

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