HP Compaq dc7600 MT Technical Reference Manual Download

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Technical Reference Guide

www.hp.com

4-9

System Support

4.2.6 PCI Connectors

PCI 2.3 Connector

Figure 4-5. PCI 2.3 Bus Connector (32-Bit, 5.0-volt Type)

Table 4-5.

PCI 2.3 Bus Connector Pinout

Pin

B Signal

A Signal

Pin

B Signal

A Signal

Pin

B Signal

A Signal

-12 VDC

TRST-

GND

AD28

+3.3 VDC

PAR

TCK

+12 VDC

AD27

AD26

C/BE1-

AD15

GND

TMS

AD25

GND

AD14

+3.3 VDC

TDO

TDI

+3.3 VDC

AD24

GND

AD13

+5 VDC

C/BE3-

IDSEL

AD12

AD11

+5 VDC

INTA-

AD23

+3.3 VDC

AD10

GND

INTB-

INTC-

GND

AD22

GND

AD09

INTD-

+5 VDC

AD21

AD20

Key

PRSNT1-

Reserved

AD19

GND

Key

RSVD

+5 VDC

+3.3 VDC

AD18

AD08

C/BE0-

PRSNT2-

Reserved

AD17

AD16

AD07

+3.3 VDC

GND

C/BE2-

+3.3 VDC

AD06

GND

FRAME-

AD05

AD04

RSVD

+3.3 AUX

IRDY-

GND

AD03

GND

RST-

+3.3 VDC

TRDY-

GND

AD02

CLK

+5 VDC

DEVSEL-

GND

AD01

AD00

GND

GNT-

GND

STOP-

+5 VDC

REQ-

GND

LOCK-

+3.3 VDC

ACK64-

REQ64-

+5 VDC

PME-

PERR-

SDONE n

+5 VDC

AD31

AD30

+3.3 VDC

SBO-

+5 VDC

AD29

+3.3 VDC

SERR-

GND

A62

A49

B49

B62

B52

A52

Summary of Contents for Compaq dc7600 MT

Page 1: ...91758 001 January 2005 This document provides information on the design architecture function and capabilities of the HP Compaq dx7200 and dc7600 Series Business Desktop Computers This information may be used by engineers technicians administrators or anyone needing detailed information on the products covered ...

Page 2: ...ng herein should be construed as constituting an additional warranty HP shall not be liable for technical or editorial errors or omissions contained herein This document contains proprietary information that is protected by copyright No part of this document may be photocopied reproduced or translated to another language without the prior written consent of Hewlett Packard Company ÅWARNING Text se...

Page 3: ... 1 6 Common Acronyms and Abbreviations 1 4 2 System Overview 2 1 Introduction 2 1 2 2 Features 2 2 2 3 Mechanical Design 2 4 2 3 1 Cabinet Layouts 2 5 2 3 2 Chassis Layouts 2 11 2 3 3 Board Layouts 2 15 2 4 System Architecture 2 18 2 4 1 Intel Pentium 4 Processor 2 20 2 4 2 Chipset 2 21 2 4 3 Support Components 2 22 2 4 4 System Memory 2 22 2 4 5 Mass Storage 2 23 2 4 6 Serial and Parallel Interfa...

Page 4: ...tandard CMOS Locations 4 20 4 5 System Management 4 20 4 5 1 Security Functions 4 20 4 5 2 Power Management 4 22 4 5 3 System Status 4 23 4 5 4 Thermal Sensing and Cooling 4 23 4 6 Register Map and Miscellaneous Functions 4 24 4 6 1 System I O Map 4 24 4 6 2 SCH5307 I O Controller Functions 4 26 5 Input Output Interfaces 5 1 Introduction 5 1 5 2 Enhanced IDE SATA Interfaces 5 1 5 2 1 EIDE Interfac...

Page 5: ...c 5 32 5 8 4 Audio Programming 5 33 5 8 5 Audio Specifications 5 35 5 9 Network Interface Controller 5 36 5 9 1 Wake On LAN Support 5 37 5 9 2 Alert Standard Format Support 5 37 5 9 3 Power Management Support 5 37 5 9 4 NIC Programming 5 38 5 9 5 NIC Connector 5 38 5 9 6 NIC Specifications 5 39 6 Integrated Graphics Subsystem 6 1 Introduction 6 1 6 2 Functional Description 6 2 6 3 Display Modes 6 ...

Page 6: ... Device Order 8 3 8 3 2 Network Boot F12 Support 8 4 8 3 3 Memory Detection and Configuration 8 4 8 3 4 Boot Error Codes 8 5 8 4 Setup Utility 8 6 8 5 Client Management Functions 8 16 8 5 1 System ID and ROM Type 8 16 8 5 2 Temperature Status 8 16 8 5 3 Drive Fault Prediction 8 16 8 6 SMBIOS 8 18 8 7 USB Legacy Support 8 18 A Error Messages and Codes B ASCII Character Set C Keyboard Index ...

Page 7: ...or monitor will also allow the user to view the color shading used to highlight differential data A softcopy of the latest edition of this guide is available for downloading in pdf file format at the URL listed below www hp com Viewing the file requires a copy of Adobe Acrobat Reader available at no charge from Adobe Systems Inc at the following URL www adobe com When viewing with Adobe Acrobat Re...

Page 8: ...1 2 www hp com Technical Reference Guide Introduction 1 3 Model Numbering Convention The model numbering convention or HP systems is as follows ...

Page 9: ...mits for a parameter are shown using the following methods 1 5 3 Register Notation and Usage This guide uses standard Intel naming conventions in discussing the microprocessor s CPU internal registers Registers that are accessed through programmable I O using an indexing scheme are indicated using the following format In the example above register 03C5 17h is accessed by writing the index port val...

Page 10: ...e Interrupt Controller APM advanced power management AOL Alert On LAN ASIC application specific integrated circuit ASF Alert Standard Format AT 1 attention modem commands 2 286 based PC architecture ATA AT attachment IDE protocol ATAPI ATA w packet interface extensions AVI audio video interleaved AVGA Advanced VGA AWG American Wire Gauge specification BAT Basic assurance test BCD binary coded deci...

Page 11: ...DOS compatibility hole DDC Display Data Channel DDR Double data rate memory DIMM dual inline memory module DIN Deutche IndustriNorm connector type DIP dual inline package DMA direct memory access DMI Desktop management interface dpi dots per inch DRAM dynamic random access memory DRQ data request DVI Digital video interface dword Double word 32 bits EDID extended display identification data EDO ex...

Page 12: ...ground GPIO general purpose I O GPOC general purpose open collector GART Graphics address re mapping table GUI graphic user interface h hexadecimal HW hardware hex hexadecimal Hz Hertz cycles per second ICH I O controller hub IDE integrated drive element IEEE Institute of Electrical and Electronic Engineers IF interrupt flag I F interface IGC integrated graphics controller in inch INT interrupt I ...

Page 13: ...dia extensions MPEG Motion Picture Experts Group ms millisecond MSb MSB most significant bit most significant byte mux multiplex MVA motion video acceleration MVW motion video window n variable parameter value NIC network interface card controller NiMH nickel metal hydride NMI non maskable interrupt NRZI Non return to zero inverted ns nanosecond NT nested task flag NTSC National Television Standar...

Page 14: ...nly memory PTR pointer RAM random access memory RAS row address strobe rcvr receiver RDRAM Direct Rambus DRAM RGB red green blue monitor input RH Relative humidity RMS root mean square ROM read only memory RPM revolutions per minute RTC real time clock R W Read Write SATA Serial ATA SCSI small computer system interface SDR Singles data rate memory SDRAM Synchronous Dynamic RAM SDVO Serial digital ...

Page 15: ...wist pneumatic SVGA super VGA SW software TAD telephone answering device TAFI Temperature sensing And Fan control Integrated circuit TCP tape carrier package transmission control protocol TF trap flag TFT thin film transistor TIA Telecommunications Information Administration TPE twisted pair ethernet TPI track per inch TTL transistor transistor logic TV television TX transmit UART universal asynch...

Page 16: ...t VESA Video Electronic Standards Association VGA video graphics adapter VLSI very large scale integration VRAM Video RAM W watt WOL Wake On LAN WRAM Windows RAM ZF zero flag ZIF zero insertion force socket Table 1 1 Acronyms and Abbreviations Acronym or Abbreviation Description ...

Page 17: ...phasize performance along with industry compatibility These models feature architectures incorporating the PCI bus All models are easily upgradeable and expandable to keep pace with the needs of the office enterprise Figure 2 1 HP Compaq dx7200and dc7600 Series Business Desktop Computers This chapter includes the following topics Features 2 2 page 2 2 Mechanical design 2 3 page 2 4 System architec...

Page 18: ...terface PCI 2 3 and PCI Express interfaces Hard drive fault prediction Eight USB 2 0 ports High definition HD audio processor with one headphone output at least one microphone input one line output and one line input Network interface controller providing 10 100 1000Base T support Plug n Play compatible with ESCD support Intelligent Manageability support Energy Star compliant Security features inc...

Page 19: ...ll height dimensions height 4 2 in length 6 875 in Table 2 1 Difference Matrix by Form Factor USDT SFF ST MT CMT Series dc7600 dc7600 dx7200 dx7200 dc7600 System Board Type custom custom custom µATX µATX Serial and parallel ports Optional 1 Standard Standard Standard Standard Memory of sockets Maximum memory Memory type 3 3 GB DDR2 4 4 GB DDR2 4 4 GB DDR2 4 4 GB DDR2 4 4 GB DDR2 Drive bays Externa...

Page 20: ...n ATX type unit providing the most expandability and being adaptable to desktop horizontal or floor standing vertical placement The following subsections describe the mechanical physical aspects of models ÄCAUTION Voltages are present within the system unit whenever the unit is plugged into a live AC outlet regardless of the system s Power On condition Always disconnect the power cable from the po...

Page 21: ...anel components of the Ultra Slim Desktop USDT format factor Figure 2 2 HP Compaq dc7600 USDT Front View Item Description Item Decription 1 MultiBay device bay 5 USB ports 7 8 2 MultiBay device eject lever 6 Power LED 3 Microphone audio In jack 7 MultiBay device HD activity LED 4 Headphone audio Out jack 8 Power button ...

Page 22: ...q dc7600 SFF Front View Item Description Item Decription 1 Diskette drive activity LED 7 Microphone audio In jack 2 Diskette drive media door 8 Headphone audio Out jack 3 CD ROM drive acitvity LED 9 USB ports 7 8 4 Diskette drive eject button 10 Hard drive activity LED 5 CD ROM media tray 11 Power LED 6 CD ROM drive open close button 12 Power button ...

Page 23: ...Compaq dx7200 ST Front View Item Description Item Decription 1 Microphone audio in jack 7 Diskette drive activity LED 2 Headphone audio out jack 8 Diskette media door 3 USB ports 7 8 9 CD ROM drive acitvity LED 4 hard drive activity LED 10 Diskette drive eject button 5 Power LED 11 CD ROM media tray 6 Power button 12 CD ROM drive open close button ...

Page 24: ...Compaq dx7200 MT Front View Item Description Item Decription 1 CD ROM drive 7 CD ROM drive open close button 2 CD ROM drive activity LED 8 Power button 3 Diskette drive media door 9 Power LED 4 Diskette drive activity LED 10 Hard drive activity LED 5 Diskette drive eject button 11 Headphone audio Out jack 6 USB ports 7 8 12 Microphone audio In jack ...

Page 25: ...6 HP Compaq dc7600 CMT Front View Item Description Item Decription 1 CD ROM drive 7 CD ROM drive open close button 2 CD ROM drive activity LED 8 Power button 3 Diskette drive media door 9 Power LED 4 Diskette drive activity LED 10 USB ports 7 8 5 Diskette drive eject button 11 Headphone audio Out jack 6 Hard drive activity LED 12 Microphone audio In jack ...

Page 26: ...or keyboard interface PS 2 female connector color coded green for mouse interface Universal serial bus USB connector for USB 2 0 interface DB 9 male connector for RS 232 serial COM1 or COM2 interface RJ 45 jack for Local Area Network LAN interface DB 25 female connetor for parallel LPT1 interface DB 15 female connector for video monitor 1 8 inch 3 conductor phone jack color coded blue for stereo a...

Page 27: ... and or the maintenance and service guide for these systems UIltra Slim Desktop Chassis The Ultra Slim Desktop USDT chassis used for the HP Compaq dc7600 models uses a compact space saving form factor Figure 2 7 USDT Chassis Layout TopView Item Description Item Description 1 Power supply assembly 5 Chassis fan 2 DIMM sockets 3 6 MultiBay device 3 PCI card cage 7 Hard drive under MultiBay 4 Process...

Page 28: ...alf height full length PCI 2 3 slots One PCI Express x16 graphics SDVO reverse layout slot One PCI Express x1 slot With card cage Two full height full length PCI 2 3 slots NOTE 1 Accepts PCI E graphics or reversed layout ADD2 card Figure 2 8 SFF ST Chassis Layout Top Right Side Views Item Description Item Description 1 Power supply assembly 6 Card cage 2 DIMM sockets 4 7 Processor socket 3 PCI Exp...

Page 29: ...ots and all socketed system board components NOTE 1 Accepts PCI E graphics or normal layout ADD2 card Figure 2 9 MT Chassis Layout Left Side View 1 3 4 5 6 2 7 8 9 q Item Description Item Description 1 Power supply assembly 7 Speaker 2 Processor socket 8 PCI 2 3 slots 3 DIMM sockets 4 9 PCI Express x1 slot 4 DriveLock 10 PCI Express x16 graphics normal layout SDVO slot 1 5 Externally accessible dr...

Page 30: ...sion slots and all socketed system board components NOTE 1 Accepts PCI E graphics or normal layout ADD2 card Figure 2 10 CMT Chassis Layout Left Side View Minitower configuration 1 3 4 5 6 2 7 8 9 q w Item Description Item Description 1 Power supply assembly 7 Speaker inside optional card guide assembly if installed 2 Processor socket 8 Expansion board area 3 DIMM sockets 4 9 PCI 2 3 slots 4 Drive...

Page 31: ...r 11 Power button power LED HD LED temp sensor header 2 Serial port option header 12 Chassis speaker connector 3 Parallel port option header 13 Front panel audio connector 4 CMOS clear button 14 Chassis fan secondary Front panel USB port connector 5 SATA 0 header 15 Chassis fan connector 6 Password clear jumper header 16 Processor fan connctor 7 PCI Express x16 ADD2 SDVO reversed layout slot 17 DI...

Page 32: ... Chassis speaker connector 4 SATA 1 header white 16 Front panel USB port connector 5 Password clear jumper 17 DIMM sockets 4 6 PCI Express x1 slot 18 Diskette drive connector 7 PCI Express x16 graphics reversed layout SDVO slot 19 PATA primary IDE connector 8 PCI 2 3 slots 20 Auxiliary audio input connector 9 Power supply VccP connector 21 Battery 10 Processor socket 22 Power supply connector 11 P...

Page 33: ...rmal layout SDVO slot 18 Hood sense header 2 5 Chassis fan header 19 Password clear jumper header 6 Power supply VccP connector 20 Power LED button HD LED header 7 Serial port B header 2 21 CMOS clear switch 8 Processor socket 22 SATA 1 connector white 9 Processor fan connector 23 Internal speaker connector 10 DIMM sockets 4 24 Auxiliary audio input connector 11 Power supply connector 25 Front pan...

Page 34: ...ality Designed to compliment the latest Intel Pentium 4 processors the chipset serves the processor through a 533 800 1066 MB Front Side Bus FSB Communication between the GMCH and ICH8 components occurs through the Direct Media Interface DMI The SFF ST MT and CMT form factors use the integrated graphics controller of the 82945G that may be upgraded through a PCI Express x16 graphics slot All syste...

Page 35: ...raphics Cntlr RGB Monitor Hard Drive USB Ports 1 8 Serial I F 1 Diskette I F Kybd Mouse I F x16 slot PEG 1 PCI Express x1 slot 1 SATA2 HD Audio Subsystem I F PATA PCI 2 3 slot s Keyboard NIC I F Mouse Floppy CD ROM Audio I F LPC I F PCI Cntlr MultiBay Device 2 DMI DMI Power Supply Notes 1 USDT reverse layout ADD2 card only 2 Option for USDT form factor standard on SFF ST MT and CMT form factors CM...

Page 36: ... processor features Net Burst Architecture that uses hyper pipelined technology and a rapid execution engine that runs at twice the processor s core speed These systems employ a zero insertion force ZIF Socket T designed for mounting an LGA775 processor package Figure 2 15 Figure 2 15 Processor Socket and Processor Package To remove the processor 1 Remove the processore heat sink fan assembly not ...

Page 37: ...t Components Components Function 82945G GMCH Intel Graphics Media Accelerator 950 integrated graphics controller PCI Express x16 graphics interface 945G only SDRAM controller supporting unbuffered non ECC PC2 4200 DDR2 DIMMs 533 or 800 MHz FSB 82801GB ICH8 PCI 2 3 bus I F PCI Express x1 LPC bus I F SMBus I F IDE I F with SATA and PATA support HD audio interface RTC CMOS IRQ controller Power manage...

Page 38: ...ovide four DIMM sockets and support a total of four gigabytes of memory The maximum memory amounts stated above are with 1 GB memory modules using 1 Gb technology DIMMs Table 2 5 Support Component Functions Component Name Function SCH5307 I O Controller Keyboard and pointing device I F Diskette I F Serial I F COM1and COM2 Parallel I F LPT1 LPT2 or LPT3 PCI reset generation Interrupt IRQ serializer...

Page 39: ...rial interface is RS 232 C 16550 compatible and supports standard baud rates up to 115 200 as well as two high speed baud rates of 230K and 460K The parallel interface is Enhanced Parallel Port EPP1 9 and Enhanced Capability Port ECP compatible and supports bi directional data transfers 2 4 7 Universal Serial Bus Interface All models provide eight Universal Serial Bus USB ports with two ports acce...

Page 40: ...rade on the USDT form factor is only possible through the PCI 2 3 slot 2 4 10 Audio Subsystem These systems use the integrated HDaudio controller of the chipset and the Realtek ALC260 High Definition audio codec High definition audio provides improvements over AC 97 audio such as higher sampling rates refined signal interfaces and higher signal to noise ratio audio processors These systems include...

Page 41: ...o F 30o to 60o C max rate of change 20 C Hr Shock w o damage 5 Gs 1 20 Gs 1 Vibration 0 000215 G2 Hz 10 300 Hz 0 0005 G2 Hz 10 500 Hz Humidity 10 90 Rh 28o C max wet bulb temperature 5 95 Rh 38 7o C max wet bulb temperature Maximum Altitude 10 000 ft 3048 m 2 30 000 ft 9144 m 2 Table 2 8 Electrical Specifications Parameter U S International Input Line Voltage Nominal Maximum 100 240 VAC 90 264 VAC...

Page 42: ...s a monitor Table 2 9 Physical Specifications Parameter USDT ST SFF MT CMT 3 Height 2 95 in 7 49 cm 13 3 in 33 78 cm 3 95 in 10 03 cm 14 5 in 36 8 cm 17 65 in 44 8 cm Width 12 4 in 31 5 cm 3 95 in 10 03 cm 13 3 in 33 78 cm 6 88 in 17 5 cm 6 60 in 16 8 cm Depth 13 18 in 33 48 cm 14 9 in 37 85 cm 14 9 in 37 85 cm 16 31 in 41 1 cm 17 8 in 45 21 cm Weight 1 13 2 lb 2 6 0 kg 2 19 5 lb 8 8 kg 19 5 lb 8 ...

Page 43: ...Media Type 3 5 in 1 44 MB 720 KB diskette Height 1 3 bay 1 in Bytes per Sector 512 Sectors per Track High Density Low Density 18 9 Tracks per Side High Density Low Density 80 80 Read Write Heads 2 Average Access Time Track to Track high low Average high low Settling Time Latency Average 3 ms 6 ms 94 ms 169 ms 15 ms 100 ms ...

Page 44: ...CD ROM 4 8 Kb s CD ROM CD R 1 5 6 Kb s Transfer Rate Writes N a CD R 2 4 Kbps sustained CD RW 1 5 Kbps sustained Capacity Mode 1 12 cm Mode 2 12 cm 8 cm 550 MB 640 MB 180 MB 650 MB 12 cm Center Hole Diameter 15 mm 15 mm Disc Diameter 8 12 cm 8 12 cm Disc Thickness 1 2 mm 1 2 mm Track Pitch 1 6 um 1 6 um Laser Beam Divergence Output Power Type Wave Length 1 5 0 14 mW GaAs 790 25 nm 53 5 1 5 53 6 0 ...

Page 45: ...SATA SATA Transfer Rate 300 Gb s 300 Gb s 300 Gb s Drive Protection System Support Yes Yes Yes Typical Seek Time w settling Single Track Average Full Stroke 1 2 ms 8 0 ms 18 ms 0 8 ms 9 0 ms 17 ms 0 8 ms 9 ms 17 ms Disk Format logical blocks 78 165 360 156 301 488 320 173 056 Rotation Speed 5400 7200 5400 7200 7200 RPM Drive Fault Prediction SMART III SMART III SMART III ...

Page 46: ...2 30 www hp com Technical Reference Guide System Overview ...

Page 47: ... and the 945G chipset Figure 3 1 The dx7200 and dc7600 models support PC2 4200 DDR2 DIMMs Figure 3 1 Processor Memory Subsystem Architecture This chapter includes the following topics Pentium 4 processor 3 2 page 3 2 Memory subsystem 3 3 page 3 4 Pentium 4 Processor 82945G GMCH Cntrl SDRAM XMM1 Ch A DIMM Ch A DIMM Ch B DIMM Ch B DIMM XMM3 XMM4 XMM2 1 FSB I F Note 1 SFF ST and CMT models only ...

Page 48: ...re occurring branches are detected in the main processing loop This feature allows instruction decoding to be removed from the main processing loop Rapid Execution Engine Arithmetic Logic Units ALUs run at twice 2x processing frequency for higher throughput and reduced latency 1 MB Advanced transfer L2 cache Using 32 byte wide interface at processing speed the large L2 cache provides a substantial...

Page 49: ...e same type heatsink fan assembly as the original to ensure proper cooling The processor uses a PLGA775 package consisting of the processor die mounted upside down on a PC board This arrangement allows the heat sink to come in direct contact with the processor die The heat sink and attachment clip are specially designed provide maximum heat transfer from the processor component ÄCAUTION Attachment...

Page 50: ... installed for both channels but of unequal channel capacities Dual channel interleaved mode recommended DIMMs installed for both channels and offering equal channel capacities proving the highest performance These systems support DIMMs with the following parameters Unbuffered compatible with SPD rev 1 0 256 Mb 512 Mb and 1 Gb memory technologies for x8 and x16 devices CAS latency CL of 4 Single o...

Page 51: ...ocket Loading Channel A Channel B Socket 1 Socket 2 1 Socket 3 Socket 4 Total 128 MB none none none 128 MB 128 MB none 128 MB none 256 MB dual channel 128 MB 128 MB 128 MB none 384 MB dual channel 128 MB 128 MB 128 MB 128 MB 512 MB dua channel 256 MB none none none 256 MB 256 MB none 256 MB none 512 MB dual channel 512 MB none none none 512 MB 512 MB none 512 MB none 1 GB dual channel 1 GB none no...

Page 52: ...on Notes Byte Description Notes 0 No of Bytes Written Into EEPROM 1 25 Min CLK Cycle Time at CL X 2 7 1 Total Bytes In EEPROM 2 26 Max Acc Time From CLK CL X 2 7 2 Memory Type 27 Min Row Prechge Time 7 3 No of Row Addresses On DIMM 3 28 Min Row Active to Delay 7 4 No of Column Addresses On DIMM 29 Min RAS to CAS Delay 7 5 No of Module Banks On DIMM 30 31 Reserved 6 7 Data Width of Module 32 61 Sup...

Page 53: ...north bridge be mapped to DRAM or to PCI space Graphics RAM area is mapped to PCI or AGP locations Figure 3 3 System Memory Map High BIOS Area DMI APIC PCI Top of DRAM 16 MB 4 GB TSEG IGC 1 32 MB DOS 640 KB FFFF FFFFh 1 MB Main BIOS 00FF FFFFh FFE0 0000h 000F FFFFh Base Memory Extended BIOS Legacy Video Expansion Area 0000 0000h 0010 0000h 0100 0000h Main Area F000 0000h Memory Area Memory Memory ...

Page 54: ...3 8 www hp com Technical Reference Guide Processor Memory Subsystem ...

Page 55: ...tion refer to the appropriate PCI specification or the PCI web site www pcisig com These systems implement the following types of PCI buses PCI 2 3 Legacy parallel interface operating at 33 MHz PCI Express High performance interface capable of using multiple TX RX high speed lanes of serial data streams The PCI bus handles address data transfers through the identification of devices and functions ...

Page 56: ...s For I O and memory cycles a standard 32 bit address decode AD31 0 for byte level addressing is handled by the appropriate PCI device For memory addressing PCI devices decode the AD31 2 lines for dword level addressing and check the AD1 0 lines for burst linear incrementing mode In burst mode subsequent data phases are conducted a dword at a time with addressing assumed to increment accordingly f...

Page 57: ...eing serviced by a downstream bridge Figure 4 2 shows the configuration cycle format and how the loading of 0CF8h results in a Type 0 configuration cycle on the PCI bus The Device Number bits 15 11 determines which one of the AD31 11 lines is to be asserted high for the IDSEL signal which acts as a chip select function for the PCI device to be configured The function number CF8h bits 10 8 is used ...

Page 58: ...r 0 1 0 28 28 2 0 0 0 PCI Express x16 graphics slot 2 0 0 32 82801EB ICH8 PCI Bridge LPC Bridge IDE Controller Serial ATA Controller SMBus Controller USB I F 1 USB I F 2 USB I F 3 USB I F 4 USB 2 0 Controller AC97 Audio Controller AC97 Modem Controller Network Interface Controller PCI Express port 1 PCI Express port 2 PCI Express port 3 PCI Express port 4 PCI Express port 5 PCI Express port 6 Inte...

Page 59: ...nsaction with a target If the PCI device already owns the bus a request is not needed and the device can simply assert FRAME and conduct the transaction Table 4 3 shows the grant and request signals assignments for the devices on the PCI bus Not required Data required by PCI protocol Configuration Space Header PCI Configuration Space Type 1 Class Code Command 31 24 23 16 15 8 7 0 Revision ID Vendo...

Page 60: ...ame methods of device discovery and resource allocation that legacy PCI based operating systems and drivers are designed to use The use of PCI configuration space and the programmability of I O devices are also used in the same way as for legacy PCI buses although PCI Express operation uses more configuration space The software driver layer provides read and write requests to the transaction layer...

Page 61: ...ne for receive Figure 4 4 Figure 4 4 PCI Express Bus Lane Each byte is transferred using 8b 10b encoding which embeds the clock signal with the data Operating at a 2 5 Gigabit transfer rate a single lane can provide a data flow of 200 MBps The bandwidth is increased if additional lanes are available for use During the initialization process two PCI Express devices will negotiate for the number of ...

Page 62: ...eir own specific firmware in ROM Such option ROM data if detected is loaded into system memory s DOS compatibility area refer to the system memory map shown in chapter 3 4 2 4 PCI Interrupts Eight interrupt signals INTA thru INTH are available for use by PCI devices These signals may be generated by on board PCI devices or by devices installed in the PCI slots For more information on interrupts in...

Page 63: ... INTA 27 AD23 3 3 VDC 48 AD10 GND 07 INTB INTC 28 GND AD22 49 GND AD09 08 INTD 5 VDC 29 AD21 AD20 50 Key Key 09 PRSNT1 Reserved 30 AD19 GND 51 Key Key 10 RSVD 5 VDC 31 3 3 VDC AD18 52 AD08 C BE0 11 PRSNT2 Reserved 32 AD17 AD16 53 AD07 3 3 VDC 12 GND GND 33 C BE2 3 3 VDC 54 3 3 VDC AD06 13 GND GND 34 GND FRAME 55 AD05 AD04 14 RSVD 3 3 AUX 35 IRDY GND 56 AD03 GND 15 GND RST 36 3 3 VDC TRDY 57 GND AD...

Page 64: ... 10 3 3 Vaux 3 3 VDC 38 PETn5 GND 66 PETp12 GND 11 WAKE PERST 39 GND PERp5 67 PETn12 GND 12 RSVD GND 40 GND PERn5 68 GND PERp12 13 GND REFCLK 41 PETp6 GND 69 GND PERn12 14 PETp0 REFCLK 42 PETn6 GND 70 PETp13 GND 15 PETn0 GND 43 GND PERp6 71 PETn13 GND 16 GND PERp0 44 GND PERn6 72 GND PERp13 17 PRSNT2 PERn0 45 PETp7 GND 73 GND PERn13 18 GND GND 46 PETn7 GND 74 PETp14 GND 19 PETp1 RSVD 47 GND PERp7 ...

Page 65: ...or software means external to the microprocessor Maskable Interrupts The maskable interrupt is a hardware generated signal used by peripheral functions within the system to get the attention of the microprocessor Peripheral functions produce a unique INTA H PCI or IRQ0 15 ISA signal that is routed to interrupt processing logic that asserts the interrupt INTR input to the microprocessor The micropr...

Page 66: ... first Table 4 7 Maskable Interrupt Priorities and Assignments Priority Signal Label Source Typical 1 IRQ0 Interval timer 1 counter 0 2 IRQ1 Keyboard 3 IRQ8 Real time clock 4 IRQ9 Unused 5 IRQ10 PCI devices slots 6 IRQ11 Audio codec 7 IRQ12 Mouse 8 IRQ13 Coprocessor math 9 IRQ14 Primary IDE controller 10 IRQ15 Sec IDE I F controller not available on SATA units 11 IRQ3 Serial port COM2 12 IRQ4 Seri...

Page 67: ...nimize latency and wired as follows NOTES 1 Connection internal to the ICH Will be reported by BIOS as using INTA but is NOT shared with other functions using INTA CMT form factors only SFF ST CMT form factors only The PCI interrupts can be configured by PCI Configuration Registers 60h 63h to share the standard ISA interrupts IRQn The APIC mode is supported by the Windows NT Windows 2000 and Windo...

Page 68: ... signals the NMI and the SMI These signals have service priority over all maskable interrupts with the SMI having top priority over all interrupts including the NMI NMI Generation The Non Maskable Interrupt NMI signal can be generated by one of the following actions Parity errors detected on a PCI bus activating SERR or PERR Microprocessor internal error activating IERRA or IERRB The SERR and PERR...

Page 69: ...tivity timers are monitored When a timer times out SMI is asserted and invokes the microprocessor s SMI handler The SMI handler works with the APM BIOS to service the SMI according to the cause of the timeout Although the SMI is primarily used for power management the interrupt is also employed for the QuickLock QuickBlank functions as well Bit Function 7 NMI Status 0 No NMI from system board pari...

Page 70: ...rity than those in controller 2 Note that channel 4 is not available for use other than its cascading function for controller 1 The DMA controller 2 can transfer words only on an even address boundary The DMA controller and page register define a 24 bit address that allows data transfers within the address space of the CPU In addition to device configuration each channel can be configured through ...

Page 71: ...bits bytes The words must always be addressed on an even boundary DMA controller 1 can move up to 64 Kbytes of data per DMA transfer DMA controller 2 can move up to 64 Kwords 128 Kbytes of data per DMA transfer Word DMA operations are only possible between 16 bit memory and 16 bit peripherals The RAM refresh is designed to perform a memory read cycle on each of the 512 row addresses in the DRAM me...

Page 72: ...sk Bits 00Fh 0DEh W Software DRQx Request 009h 0D2h W Base and Current Address Ch 0 000h 0C0h W Current Address Ch 0 000h 0C0h R Base and Current Word Count Ch 0 001h 0C2h W Current Word Count Ch 0 001h 0C2h R Base and Current Address Ch 1 002h 0C4h W Current Address Ch 1 002h 0C4h R Base and Current Word Count Ch 1 003h 0C6h W Current Word Count Ch 1 003h 0C6h R Base and Current Address Ch 2 004h...

Page 73: ...r from the power supply The battery is located in a battery holder on the system board and has a life expectancy of three or more years When the battery has expired it is replaced with a Renata CR2032 or equivalent 3 VDC lithium battery 4 4 1 Clearing CMOS The contents of configuration memory including the Power On Password can be cleared by the following procedure 1 Turn off the unit 2 Disconnect...

Page 74: ...e operating system and application software Table 4 12 Configuration Memory CMOS Map Location Function Location Function 00 0Dh Real time clock 24h System board ID 0Eh Diagnostic status 25h System architecture data 0Fh System reset code 26h Auxiliary peripheral configuration 10h Diskette drive type 27h Speed control external drive 11h Reserved 28h Expanded base mem size IRQ12 12h Hard drive type 2...

Page 75: ... Setup utility may be configured to be always changeable or changeable only by entering a password Refer to the previous procedure Power On Setup Password for clearing the Setup password Cable Lock Provision These systems include a chassis cutout on the rear panel for the attachment of a cable lock mechanism I O Interface Security The serial parallel USB and diskette interfaces may be disabled ind...

Page 76: ... GPIO ports 44 and 45 of the SCH5307 I O controller provide the lock and unlock signals to the solenoid A locked hood may be bypassed by removing special screws that hold the locking mechanism in place The special screws are removed with the Smart Cover Lock Failsafe Key 4 5 2 Power Management This system provides baseline hardware support of ACPI and APM compliant firmware and software Key power ...

Page 77: ...is the result of the temperature of the CPU as sensed by speed control circuitry The fans are controlled to run at the slowest quietest speed that will maintain proper cooling Units using chassis and CPU fans must have both fans connected to their corresponding headers to ensure proper cooling of the system Table 4 13 System Operational Status LED Indications System Status PowerLED Beeps 2 Action ...

Page 78: ... Controller 00A0 00B1h Interrupt Controller 2 00B2h 00B3h APM Control Status Ports 00B4 00BDh Interrupt Controller 00C0 00DFh DMA Controller 2 00F0h Coprocessor error register 0170 0177h IDE Controller 2 active only if standard I O space is enabled for secondary controller 01F0 01F7h IDE Controller 1 active only if standard I O space is enabled for primary controller 0278 027Fh Parallel Port LPT2 ...

Page 79: ...P standard control registers for the SCH5307 NOTE For a detailed description of registers refer to appropriate documentation available from SMC Corporation Table 4 15 SCH5307 I O Controller Control Registers Index Function Reset Value 02h Configuration Control 00h 03h Reserved 07h Logical Device Interface Select 00h Diskette Drive I F 01h Reserved 02h Reserved 03h Parallel I F 04h Serial I F UART ...

Page 80: ...uder sensing The battery backed D latch logic internal to the SCH5307 is connected to the hood sensor switch to record hood cover removal Hood lock unlock Supported on SFF ST and CMT form factors logic internal to the SCH5307 controls the lock bar mechanism I O security The parallel serial and diskette interfaces may be disabled individually by software and the SCH5307 s disabling register locked ...

Page 81: ... parallel ATA or PATA and serial ATA SATA interfaces All systems are shipped configured with SATA hard drives 5 2 1 PATA Interface The USDT form factor includes an IDE PATA interface as part of the MultiBay interface The SFF ST MT and CMT form factors include one 40 pin IDE connector on the system board The controller can be configured for the following modes of operation Programmed I O PIO mode C...

Page 82: ... PCI Conf Address Register Reset Value PCI Conf Addr Register Reset Value 00 01h Vender ID 8086h 0F 1Fh Reserved 0 s 02 03h Device ID 1 20 23h BMIDE Base Address 1 04 05h PCI Command 0000h 2C 2Dh Subsystem Vender ID 0000h 06 07h PCI Status 0280h 2E 2Fh Subsystem ID 0000h 08h Revision ID 00h 30 3Fh Reserved 0 s 09h Programming 80h 40 43h Pri Sec IDE Timing 0 s 0Ah Sub Class 01h 44h Slave IDE Timing...

Page 83: ... factory configurations connects to a optical drive CD or DVD Some signals are re defined for UATA 33 and higher modes Device power is supplied through a separate connector Figure 5 1 40 Pin IDE PATA Connector The USDT form factor does not include 40 pin IDE connctor The IDE interface and hard drive power signals are both a part of the MultiBay interface used on the USDT form factor Table 5 2 IDE ...

Page 84: ...scription Pin Signal Description 1 RESET Reset 21 DRQ DMA Request 2 GND Ground 22 GND Ground 3 DD7 Data Bit 7 23 IOW I O Write 1 4 DD8 Data Bit 8 24 GND Ground 5 DD6 Data Bit 6 25 IOR I O Read 2 6 DD9 Data Bit 9 26 GND Ground 7 DD5 Data Bit 5 27 IORDY I O Channel Ready 3 8 DD10 Data Bit 10 28 CSEL Cable Select 9 DD4 Data Bit 4 29 DAK DMA Acknowledge 10 DD11 Data Bit 11 30 GND Ground 11 DD3 Data Bi...

Page 85: ... configuration SATA Configuration Registers The SATA controller is configured as a PCI device with bus mastering capability The PCI configuration registers for the SATA controller function PCI device 31 function 2 are listed in Table 5 4 Table 5 4 SATA PCI Configuration Registers 82801 Device 31 Function 2 PCI Conf Addr Register Reset Value PCI Conf Addr Register Reset Value 00 01h Vender ID 8086h...

Page 86: ...in SATA connector is shown in the figure below Figure 5 2 7 Pin SATA Connector on system board Table 5 5 IDE Bus Master Control Registers I O Addr Offset Size Bytes Register Default Value 00h 1 Bus Master IDE Command Primary 00h 02h 1 Bus Master IDE Status Primary 00h 04h 4 Bus Master IDE Descriptor Pointer Primary 0000 0000h 08h 1 Bus Master IDE Command Secondary 00h 0Ah 2 Bus Master IDE Status S...

Page 87: ...kette drive a mechnical control function of the drive or an operation that remains internal to the diskette drive controller Data transfers writes or reads with the diskette drive controller are by DMA using the DRQ2 and DACK2 signals for control The Results phase consists of the CPU reading a series of status bytes from the data register 3F5h 375h that indicate the results of the command Note tha...

Page 88: ...detailed configuration register information refer to the SMSC data sheet for the SCH5307 I O component Table 5 7 Diskette Drive Interface Configuration Registers Index Address Function R W Reset Value 30h Activate R W 01h 60 61h Base Address R W 03F0h 70h Interrupt Select R W 06h 74h DMA Channel Select R W 02h F0h DD Mode R W 02h F1h DD Option R W 00h F2h DD Type R W FFh F4h DD 0 R W 00h F5h DD 1 ...

Page 89: ...0h 370h Status Register A 7 Interrupt pending 6 Reserved always 1 5 STEP pin status active high 4 TRK 0 status active high 3 HDSEL status 0 side 0 1 side 1 2 INDEX status active high 1 WR PRTK status 0 disk is write protected 0 Direction 0 outward 1 inward R 3F1h 371h Status Register B 7 6 Reserved always 1 s 5 DOR bit 0 status 4 Write data toggle 3 Read data toggle 2 WGATE status active high 1 0 ...

Page 90: ...Select Register DRSR 7 Software reset active high 6 Low power mode enable active high 5 Reserved 0 4 2 Precompensation select default 000 1 0 Data rate select 00 500 Kb s 01 300 Kb s 10 250 Kb s 11 2 1 Mb s R W 3F5h 375h Data Register 7 0 Data R W 3F6h 376h Reserved 3F7h 377h Digital Input Register DIR 7 DSK CHG status records opposite value of pin 6 0 Reserved 0 s Configuration Control Register C...

Page 91: ...rection control 2 LOW DEN Low density select 19 GND Ground 3 KEY 20 STEP Drive head track step cntrl 4 MEDIA ID Media identification 21 GND Ground 5 GND Ground 22 WR DATA Write data 6 DRV 4 SEL Drive 4 select 23 GND Ground 7 GND Ground 24 WR ENABLE Enable for WR DATA 8 INDEX Media index is detected 25 GND Ground 9 GND Ground 26 TRK 00 Heads at track 00 indicator 10 MTR 1 ON Activates drive motor 2...

Page 92: ...ace uses a DB 9 connector as shown in the following figure with the pinout listed in Table 5 10 Figure 5 4 Serial Interface Connector Male DB 9 as viewed from rear of chassis The standard RS 232 C limitation of 50 feet or less of cable between the DTE computer and DCE modem should be followed to minimize transmission errors Higher baud rates may require shorter cables 5 4 2 Serial Interface Progra...

Page 93: ...nction R W 30h Activate R W 60h Base Address MSB R W 61h Base Address LSB R W 70h Interrupt Select R W F0h Mode Register R W Table 5 12 Serial Interface Control Registers COM1 Addr COM2 Addr Register R W 3F8h 2F8h Receive Data Buffer Transmit Data Buffer Baud Rate Divisor Register 0 when bit 7 of Line Control Reg Is set R W W 3F9h 2F9h Baud Rate Divisor Register 1 when bit 7 of Line Control Reg Is...

Page 94: ... system either waits for a status change or generates an error message 2 The system sends a byte of data to the Printer Data register then pulses the printer STROBE signal through the Printer Control register for at least 500 ns 3 The system then monitors the Printer Status register for acknowledgment of the data byte before sending the next byte In extended mode a direction control bit CTR 37Ah b...

Page 95: ... by the Extended Control register Two submodes of ECP allow the parallel port to be controlled by software In these modes the FIFO is cleared and not used and DMA and RLE are inhibited 5 5 4 Parallel Interface Programming Programming the parallel interface consists of configuration which typically occurs during POST and control which occurs during runtime Parallel Interface Configuration The paral...

Page 96: ...egisters and associated functions based on mode Base Address LPT1 378h LPT2 278h LPT3 3BCh Table 5 14 Parallel Interface Control Registers I O Address Register SPP Mode Ports EPP Mode Ports ECP Mode Ports Base Data LPT1 2 3 LPT1 2 LPT1 2 3 Base 1h Printer Status LPT1 2 3 LPT1 2 LPT1 2 3 Base 2h Control LPT1 2 3 LPT1 2 LPT1 2 3 Base 3h Address LPT1 2 Base 4h Data Port 0 LPT1 2 Base 5h Data Port 1 L...

Page 97: ...to Feed or Host Acknowledge 3 EPP mode user defined ECP modes Fault or Peripheral Req 4 EPP mode Reset ECP modes Initialize or Reverse Req Table 5 15 DB 25 Parallel Connector Pinout Pin Signal Function Pin Signal Function 1 STB Strobe Write 1 14 LF Line Feed 2 2 D0 Data 0 15 ERR Error 3 3 D1 Data 1 16 INIT Initialize Paper 4 4 D2 Data 2 17 SLCTIN Select In Address Strobe 1 5 D3 Data 3 18 GND Groun...

Page 98: ...command the 8042 clamps the clock signal from the keyboard for a minimum of 60 us If the keyboard is transmitting data at that time the transmission is allowed to finish When the 8042 is ready to transmit to the keyboard the 8042 pulls the data line low causing the keyboard to respond by pulling the clock line low as well allowing the start bit to be clocked out of the 8042 The data is then transf...

Page 99: ...other set of scan codes and sends an option byte after ACK is received 01h Mode 1 02h Mode 2 03h Mode 3 Read ID F2h Instructs the keyboard to stop scanning and return two keyboard ID bytes Set Typematic Rate Display F3h Instructs the keyboard to change typematic rate and delay to specified values Bit 7 Reserved 0 Bits 6 5 Delay Time 00 250 ms 01 500 ms 10 750 ms 11 1000 ms Bits 4 0 Transmission Ra...

Page 100: ...nabling and speed parameters of the 8042 logic are affected through the PnP configuration registers of the SCH5307 I O controller Enabling and speed control are automatically set by the BIOS during POST but can also be accomplished with the Setup utility and other software Set Keys Make Brake F8h Clears keyboard buffer and sets default scan code set 1 Set Keys Make F9h Clears keyboard buffer and s...

Page 101: ... bit 1 should also be checked to ensure space is available I O Port 60h I O port 60h is used for accessing the input and output buffers This register is used to send and receive data from the keyboard and the pointing device This register is also used to send the second byte of multi byte commands to the 8042 and to receive responses from the 8042 for commands that require a response A read of 60h...

Page 102: ...ommands to the 8042 Value Command Description 20h Put current command byte in port 60h 60h Load new command byte A4h Test password installed Tests whether or not a password is installed in the 8042 If FAh is returned password is installed If F1h is returned no password is installed A5h Load password This multi byte operation places a password in the 8042 using the following manner 1 Write A5h to p...

Page 103: ...eived C3h Poll Input Port Low This command directs the 8042 to place bits 3 0 of the input port into the lower half of the status byte on a continous basis until another command is received D0h Read output port This command directs the 8042 to transfer the contents of the output port to the output buffer so that they can be read at port 60h D1h Write output port This command directs the 8042 to pl...

Page 104: ...dentical both physically and electrically Figure 5 7 and Table 5 19 show the connector and pinout of the keyboard pointing device interface connectors Figure 5 7 PS 2 Keyboard or Pointing Device Interface Connector as viewed from rear of chassis Table 5 19 Keyboard Pointing Device Connector Pinout Pin Signal Description Pin Signal Description 1 DATA Data 4 5 VDC Power 2 NC Not Connected 5 CLK Cloc...

Page 105: ...B ports accessible at the front of the unit and six USB ports on the rear panel The USB ports are dynamically configured to either a USB 1 1 controller or the USB 2 0 controller depending on the capability of the peripheral device The 1 1 controllers provide a maximum transfer rate of 12 Mb s while the 2 0 controller provides a maximum transfer rate of 480 Mb s Figure 5 8 USB I F Block Diagram 828...

Page 106: ...s in out start of frame SOF setup data acknowledge stall preamble and the degree of error correction to be applied Address Field 7 bit field that provides source information required in token packets Endpoint Field 4 bit field that provides destination information required in token packets Frame Field 11 bit field sent in Start of Frame SOF packets that are incremented by the host and sent only at...

Page 107: ... 1 1 1 24D2h USB 1 1 2 24D4h USB 1 1 3 24D7h USB 1 1 4 24DDh USB 2 0 24DDh Table 5 20 USB Interface Configuration Registers PCI Config Address Register Reset Value PCI Config Address Register Reset Value 00 01h Vendor ID 8086h 0Eh Header Type 00h 02 03h Device ID 1 20 23h I O Space Base Address 1d 04 05h PCI Command 0000h 2C 2Dh Sub Vender ID 00h 06 07h PCI Status 0280h 3Ch Interrupt Line 00h 08h ...

Page 108: ...ector Female Table 5 21 USB Control Registers I O Address Register Default Value 00 01h Command 0000h 02 03h Status 0000h 04 05h Interupt Enable 0000h 06 07 Frame Number 0000h 08 0B Frame List Base Address 0000h 0Ch Start of Frame Modify 40h 10 11h Port 1 Status Control 0080h 12 13h Port 2 Status Control 0080h 18h Test Data 00h Table 5 22 USB Connector Pinout Pin Signal Description Pin Signal Desc...

Page 109: ... when using sub standard cable shorter lengths may be allowable and or necessary The shield chassis ground and power ground should be tied together at the host end but left unconnected at the device end to avoid ground loops Table 5 23 USB Cable Length Data Conductor Size Resistance Maximum Length 20 AWG 0 036 Ω 16 4 ft 5 00 m 22 AWG 0 057 Ω 9 94 ft 3 03 m 24 AWG 0 091 Ω 6 82 ft 2 08 m 26 AWG 0 14...

Page 110: ...stems with both front and rear microphone jacks either jack is available for use but not simultaneously Line In This input uses a three conductor stereo mini jack that is specifically designed for connection of a high impedance audio source such as a tape deck Headphones Out This input uses a three conductor stereo mini jack that is designed for connecting a set of 32 ohm nom stereo headphones Plu...

Page 111: ...om the controller and serial data in SDI from the audio codec that transfer control and PCM audio data serially to and from the audio codec using a time division multiplexed TDM protocol The data lines are qualified by the 24 MHz BCLK signal driven by the audio controller Data is transferred in frames synchronized by the 48 KHz SYNC signal which is derived from the clock signal and driven by the a...

Page 112: ...h an equalizer or applied directly to the digital to analog converter DAC The codec supports simultaneous record and playback of stereo left and right audio The sampling rate used by the Sample Rate Controllers SRC may be set independently for the ADCs and the DAC The integrated analog mixer provides the computer control console functionality handling multiple audio inputs Figure 5 13 ALC260 HD Au...

Page 113: ... sheet for more information Table 5 24 HD Audio Controller PCI Configuration Registers 82801 Device 27 Function 0 PCI Config Address Register Value on Reset PCI Config Address Register Value on Reset 00 01h Vendor ID 8086h 14 17h HD Audio Upper Base Addr 0 02 03h Device ID 24D5h 2C 2Dh Subsystem Vender ID 0000h 04 05h PCI Command 0000h 2E 2Fh Subsystem ID 0000h 06 07h PCI Status 0280h 34h Capabili...

Page 114: ...g State F03h Set Pin Widget Cntrl 707h Get GPIO Unsol Resp En Mask F19h Set Processing State 703h Get Unsol Resp Cntrl F08h Set GPIO Unsol Resp En Mask 719h Get Coefficient Index 00Dh Set Unsol Resp Cntrl 708h Function Reset 7FFh Set Coefficient Index 005h Get Pin Sense F09h Get Digital Converter Control F0Dh Get Processing Coefficient 00Ch Execute Pin Sense 709h Set Digital Conv Cntrl 1 70Dh Set ...

Page 115: ...Rates DAC ADC 44 1 48 96 192 KHz 1 44 1 48 96 KHz 1 Resolution DAC ADC 24 bit 20 bit Nominal Input Voltage Mic In w 20 db gain Line In 283 Vp p 2 83 Vp p Subsystem Impedance nominal Mic In Line In Line Out Headphones Out 64K ohms 64K ohms 200 ohms 32 0hms Signal to Noise Ratio input to Line Out 95 db nom Max Subsystem Power Output to 4 ohm Internal Speaker with 10 THD 1 5 watts Gain Step 1 db Mast...

Page 116: ...t for ACPI 1 1 PXE 2 0 WOL ASF 1 0 IPMI Cisco Etherchannel support Link and Activity LED indicator drivers The controller features high and low priority queues and provides priority packet processing for networks that can support that feature The controller s micro machine processes transmit and receive frames independently and concurrently Receive runt under sized frames are not passed on as faul...

Page 117: ...network with an ASF compliant management console 5 9 3 Power Management Support The NIC features Wired for Management WfM support providing system wake up from network events WOL as well as generating system status messages AOL and supports ACPI power management environments The controller receives 3 3 VDC auxiliary power as long as the system is plugged into a live AC receptacle allowing support ...

Page 118: ...space The BIOS for the BCM5782 is contained within the HP Compaq BIOS in system ROM Refer to Broadcom documentation for details regarding BCM5782 register programming 5 9 5 NIC Connector Figure 5 14 shows the RJ 45 connector used for the NIC interface This connector includes the two status LEDs as part of the connector assembly Figure 5 15 Ethernet TPE Connector RJ 45 viewed from card edge 1 2 4 3...

Page 119: ...00BASE TX full duplex 2 Gb s Standards Compliance IEEE 802 1P 802 1Q IEEE 802 2 IEEE 802 3 802 3ab 802 3ad 802 3u 802 3x 802 3z OS Driver Support MS DOS MS Windows 3 1 MS Windows 95 pre OSR2 98 and 2000 Professional XP Home XP Pro MS Windows NT 3 51 4 0 Novell Netware 3 x 4 x 5x Novell Netware IntraNetWare SCO UnixWare 7 Linux 2 2 2 4 PXE 2 0 Boot ROM Support Intel PRO 100 Boot Agent PXE 3 0 RPL F...

Page 120: ...5 40 www hp com Technical Reference Guide Input Output Interfaces ...

Page 121: ... PCI 2 3 slot The USDT form factor may be upgraded by installing an ADD2 reverse layout card in the PCI E slot or a graphics card into the PCI 2 3 slot An installed PCI Express or PCI 2 3 graphics controller card will be detected by the BIOS during the boot sequence and the integrated graphics controller of the 82945G GMCH will then be disabled refer to section 6 4 for more information on upgradin...

Page 122: ...ut SDVO ADD2 type card only All systems may be also be upgraded by installing a PCI graphics card in the PCI 2 3 slot Figure 6 1 945G Based Graphics Block diagram The Integrated Graphics Controller provides the following features 2x performance over previous generation IGC Rapid pixel and texel rendering using four pipelines that allow 2D and 3D operations to overlap speeding up visual effects red...

Page 123: ... The total memory allocation is determined by the amount of system memory installed in a system The video BIOS pre allocates 8 megabytes of memory during POST System memory that is pre allocated is not seen by the operating system which will report the total amount of memory installed less the amount of pre allocated memory Example A system with 128 MB of SDRAM with the video BIOS set to 8 MB will...

Page 124: ...on In Windows 2000 or XP the video memory size reported by DirectX will always be 32 MB even if the total memory installed is over 128 MB Some applications particularly games that require advanced 3D hardware acceleration may not install or run correectly on systems using the IGC 6 3 Display Modes The IGC supports most standard display modes for 2D video displays up to and including 2048 x 1536 85...

Page 125: ...ific cards Two SDVO channels are provided by the IGC for supporting two digital displays Existing option cards and drivers support one CRT and digital display Dual digital display support may be possible with future cards and drivers The upgrade procedure is as follows 1 Shut down the system through the operating system 2 Unplug the power cord from the rear of the system unit 3 Remove the chassis ...

Page 126: ...NOTES 1 Fuse automatically resets when excessive load is removed Table 6 1 DB 15 Monitor Connector Pinout Pin Signal Description Pin Signal Description 1 R Red Analog 9 PWR 5 VDC fused 1 2 G Blue Analog 10 GND Ground 3 B Green Analog 11 NC Not Connected 4 NC Not Connected 12 SDA DDC2 B Data 5 GND Ground 13 HSync Horizontal Sync 6 R GND Red Analog Ground 14 VSync Vertical Sync 7 G GND Blue Analog G...

Page 127: ...ution 7 4 page 7 12 7 2 Power Supply Assembly Control These systems feature a power supply assembly that is controlled through programmable logic Figure 7 1 Figure 7 1 Power Distribution and Control Block Diagram System Board Power Supply Power On CPU slots Chipsets Logic Front Bezel Voltage Regulators Assembly Fan PS On 5 VDC 12 VccP Power Button Spd 1 12 VDC 12 VDC 3 3 VDC Drives 3 3 VDC 5 VDC 1...

Page 128: ... A power planes NOTES Total continuous power should not exceed 240 watts Total surge power 10 seconds w duty cycle 5 should not exceed 260 watts 1 The minimum current loading figures apply to a PS On start up only Table 7 1 200 Watt USDT Power Supply Assembly Specifications Range or Tolerance Min Current Loading 1 Max Current Surge Current 2 Max Ripple Input Line Voltage 115 230 VAC auto ranging 9...

Page 129: ...h 12 volt tolerance 10 Table 7 3 300 Watt MT Power Supply Assembly Specifications Range or Tolerance Min Current Loading 1 Max Current Surge Current Max Ripple Input Line Voltage 100 127 VAC 200 240 VAC 90 132 VAC 180 264 VAC Line Frequency 47 63 Hz Input AC Current 6 0 A 3 3 VDC Output 5 0 10 A 18 0 A 19 0 A 50 mV 5 08 VDC Output 5 0 0 30 A 25 0 A 25 0 A 50 mV 5 08 AUX Output 5 0 0 00 A 2 00 A 2 ...

Page 130: ...lts In Off Negative pulse of which the falling edge results in power control logic asserting PS On signal to Power Supply Assembly which then initializes ACPI four second counter is not active On ACPI Disabled Negative pulse of which the falling edge causes power control logic to de assert the PS On signal ACPI four second counter is not active On ACPI Enabled Pressed and Released Under Four Secon...

Page 131: ...ormal full on operation Blinks green 0 5 Hz Suspend state S1 or suspend to RAM S3 Blinks red 2 times 1 Hz 1 Processor thermal shut down Check air flow fan operation and CPU heat sink Blinks red 3 times 1 Hz 1 Processor not installed Install or reseat CPU Blinks red 4 times 1 Hz 1 Power failure power supply is overloaded Check voltage selector if applicable stroage devices expansion cards and or sy...

Page 132: ...rtion of the PME signal on the PCI bus Refer to Chapter 5 Network Support for more information Modem Ring A ring condition on a serial port can be detected by the power control logic and if so configured cause the PS On signal to be asserted Power Management Event A power management event that asserts the PME signal on the PCI bus can be enabled to cause the power control logic to generate the PS ...

Page 133: ...n To S0 by 2 OS Restart Required G0 S0 D0 System fully on OS and application is running all components Maximum N A No G1 S1 C1 D1 System on CPU is executing and data is held in memory Some peripheral subsystems may be on low power Monitor is blanked Low 2 sec after keyboard or pointing device action No G1 S2 3 C2 D2 Standby or suspend System on CPU not executing cache data lost Memory is holding d...

Page 134: ...tor NOTES Connectors not shown to scale All and values are VDC RTN Return signal ground sns sense GND Power ground RS Remote sense FO Fan off FSpd Fan speed FS Fan Sink FC Fan Command Vccp 12 VDC for CPU 1 This row represents pins 13 24 of connector P1 Figure 7 2 USDT Power Cable Diagram Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 P1 5 aux RTN 5 5 PS On RTN Pwr ...

Page 135: ...n Sink POK Power OK power good VccP 12 for CPU 1 This row represents pins 13 24 of connector P1 Figure 7 3 SFF ST Power Cable Diagram Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 P1 5 aux RTN 5 5 PS On RTN Pwr Gd 3 3 3 3 Tach RTN Fan P1 1 12 5 sns RTN 5 5 3 3 RTN 3 3 sns 3 3 3 3 RTN 12 P2 5 RTN RTN 12 P3 RTN RTN RTN VccP VccP 12 P4 5 3 3 RTN 5 RTN 12 P6 12 RTN RT...

Page 136: ...d FC Fan Command 1 This row represents pins 13 24 of connector P1 Figure 7 4 MT Power Cable Diagram Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 P1 3 3 3 3 RTN 5 RTN 5 RTN POK 5 aux 12 12 3 3 P1 1 3 3 12 RTN PS On RTN RTN RTN Open 5 5 5 RTN P3 RTN RTN VccP VccP P4 5 9 10 3 3 RTN 5 08 RTN 12 P6 7 11 12 RTN RTN 5 P8 5 RTN RTN 12 Power Supply 385576 P1 P3 P5 P1 13 1...

Page 137: ...d FC Fan Command 1 This row represents pins 13 24 of connector P1 Figure 7 5 CMT Power Cable Diagram Conn Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 Pin 10 Pin 11 Pin 12 P1 3 3 3 3 RTN 5 RTN 5 RTN POK 5 aux 12 12 3 3 P1 1 3 3 12 RTN PS On RTN RTN RTN Open 5 5 5 RTN P3 RTN RTN VccP VccP P4 5 9 10 3 3 RTN 5 08 RTN 12 P6 7 11 12 RTN RTN 5 P8 5 RTN RTN 12 Power Supply 379294 P1 P5 P7 P1 13 ...

Page 138: ...it Processor VccP Clk S Bridge PCI USB PS2 Kybd Aux 5 VDC 5 Aux PS Switch Regulator 5 VDC 3 3 VDC AUX 1 2 VDC Aux 5 VDC PS CPU 12 VDC PS PCI SATA LPT Chipset 2 5 VDC AUX Power 3 VDC Switch Supply Chipset 5 VDC PS 5 Aux PS COM Diskette logic Chipset 3 3 VDC PS 3 3 VDC PS SIO Audio FWH logic Clk PCI COM logic 3 3 VDC 1 8 V Regulator 0 9 V Regulator Chipset DIMMs DIMMs 1 2 Aux V Regulator 2 5 V Regul...

Page 139: ...eader pinout Figure 7 7 USDT Form Factor Signal Distribution Diagram P8 12 VccP Power LED IDE I F P1 Power P6 P5 P3 Supply Assembly 3 3 5 5 Aux 12 VDC MultiBay Front Mouse PS On POK Hard Drive SATA Keyboard P60 P21 P23 Daughter Board Diskette I F CD Audio HD LED System Chassis Fan Speaker CD DVD or P24 Panel I O Module Board 376335 001 Power On J66 SATA I F USB 6 7 Tx Rx Kybd data Mic In HP Out Au...

Page 140: ... Distribution Diagram P8 12 VccP Power LED P1 Power P6 P5 P3 Supply Assembly 3 3 5 5 Aux 12 VDC Front Mouse PS On POK Hard Drive SATA Keyboard P60 P20 P10 P23 IDE I F HD LED System Chassis Fan Speaker CD ROM P24 Panel I O Module Board 376332 001 Power On Diskette J66 J67 Diskette I F SATA I F USB 6 7 Tx Rx Kybd data Mic In HP Out Audio Mouse data ...

Page 141: ...ower P6 P5 P3 Supply Assembly 3 3 5 5 Aux 12 VDC Front Mouse PS On POK Hard Drive SATA Keyboard P60 P20 P10 P23 HD LED System Chassis Fan Speaker CD ROM P24 Panel I O Module Board 375374 001 Power On Diskette J68 Diskette I F SATA I F USB 6 7 Tx Rx Kybd data Mic In HP Out Audio Mouse data J30 PCI Expansion PCI 2 3 I F Daughter Board 1 NOTE 1 CMT form factor only ...

Page 142: ...DCD 13 12 Comm B Detect 12V 15 14 12V Serial Port B Header P52 Hood Lock 1 GND 5 2 Coil Conn 4 12V 6 Hood Unlock Hood Lock Header P124 1 Hood SW Detect 2 GND 3 Hood Sensor Hood Sense Header P125 HD LED Cathode 1 HD LED Anode 3 GND5 2 PS LED Cathode 4 PS LED Anode 8 GND 6 Pwr Btn GND 11 Therm Diode A 13 12 NC Chassis ID0 9 14 Therm Diode C Power Button LED HD LED Header P5 USDT SFF ST 10 Chassis ID...

Page 143: ...red for PnP support OS 2 ver 2 1 and OS 2 Warp SCO Unix DMI 2 1 Intel Wired for Management WfM ver 2 2 Alert Standard Format ASF 2 0 ACPI and OnNow SMBIOS 2 4 Intel PXE boot ROM for the integrated LAN controller BIOS Boot Specification 1 01 Enhanced Disk Drive Specification 3 0 El Torito Bootable CD ROM Format Specification 1 0 ATAPI Removeable Media Device BIOS Specification 1 0 The BIOS firmware...

Page 144: ...ocessor All BIOS ROM upgrades are available directly from HP Flashing is done either locally thrugh F10 setup the HPQFlash program in a Windows environment or with the FLASHBIN EXE utility in a DOS or DOS like environment Flashing may also be done by deploying either HPQFlash or FLASHBIN EXE through the network boot function This system includes 64 KB of write protected boot block ROM that provide...

Page 145: ..._Filename Background_Color Foreground_Color The utility checks to insure that the specified image meets the splash screen requirements listed above or it will not be loaded into the ROM 8 3 Boot Functions The BIOS supports various functions related to the boot process including those that occur during the Power On Self Test POST routine 8 3 1 Boot Device Order The default boot device order is as f...

Page 146: ...pliant server 8 3 3 Memory Detection and Configuration This system uses the Serial Presence Detect SPD method of determining the installed DIMM configuration The BIOS communicates with an EEPROM on each DIMM through the SMBus to obtain data on the following DIMM parameters Presence Size Type Timing CAS latency PC133 capability Refer to Chapter 3 Processor Memory Subsystem for the SPD format and DI...

Page 147: ...Hz None Power failure power supply is overloaded Check voltage selector if applicable stroage devices expansion cards and or system board Blinks red 5 times 1 Hz 5 beeps Pre video memory error Incompatible or incorrectly seated DIMM Blinks red 6 times 1 Hz 6 beeps Pre video graphics error On system with integrated graphics check replace system board On system with graphics card check replace graph...

Page 148: ...n Chassis serial number Asset tracking number About Displays copyright information Set Time and Date Allows you to set system time and date Flash System ROM Allows user to update the BIOS image from Setup The binary file can be obtained from a USB diskette or CD removable media Replicated Setup Save to Removable Media Saves system configuration including CMOS to a formatted 1 44 MB diskette a USB ...

Page 149: ...e emulation Drive Type Emulation Options ATAPI Zip drive None treated as Other Diskette treated as diskette drive ATA Hard disk None treated as Other Disk treated as hard drive Legacy diskette No emulation options available CD ROM drive No emulation options available ATAPI LS 120 None treated as Other Diskette treated as diskette drive Default Values IDE SATA Multisector Transfers ATA disks only S...

Page 150: ...e emulation Drive Type Emulation Options ATAPI Zip drive None treated as Other Diskette treated as diskette drive ATA Hard disk None treated as Other Disk treated as hard drive Legacy diskette No emulation options available CD ROM drive No emulation options available ATAPI LS 120 None treated as Other Diskette treated as diskette drive Default Values IDE SATA Multisector Transfers ATA disks only S...

Page 151: ...omputer off then on manually BIOS DMA Data Transfers Allows you to control how BIOS disk I O requests are serviced When Enable is selected the BIOS will service ATA disk read and write requests with DMA data transfers When Disable is selected the BIOS will service ATA disk read and write requests with PIO data transfers SATA Emulation Allows you to choose how the SATA controller and devices are ac...

Page 152: ...ed hard drives The first hard drive in the order will have priority in the boot sequence and will be recognized as drive C if any devices are attached MS DOS drive lettering assignments may not apply after a non MS DOS operating system has started Shortcut to Temporarily Override Boot Order To boot one time from a device other than the default device specified in Boot Order restart the computer an...

Page 153: ... Management Guide on the Documentation CD for more information Device Security Enables disables serial ports parallel port front USB ports system audio network controllers some models MultiBay devices some models SMBus controller some models and SCSI controllers some models Network Service Boot Enables disables the computer s ability to boot from an operating system installed on a network server F...

Page 154: ...time Power Management selected processors only Enable Disable Allows certain operating systems to reduce processor voltage and frequency when the current software load does not require the full capabilities of the processor Idle Power Savings selected processors only Extended Normal Allows certain operating systems to decrease the processors power consumption when the processor is idle ACPI S3 Sup...

Page 155: ... message before loading options ROMs This feature is supported on select models only Remote wakeup boot source remote server local hard drive After Power Loss off on previous state After power loss if you connect your computer to an electric power strip and would like to turn on power to the computer using the switch on the power strip set this option to ON If you turn off power to your computer u...

Page 156: ...options without entering Setup password Execute Memory Test When selected will reboot system and perform a complete memory test BIOS Power On Allows you to set the computer to turn on automatically at a time you specify Onboard Devices Allows you to set resources for or disable onboard system devices diskette controller serial port or parallel port PCI Devices Lists currently installed PCI devices...

Page 157: ... LED blink pattern that uniquely identifies each sleep state Integrated Video enable disable Allows you to use integrated video and PCI Up Solution video at the same time available on select models only Inserting a PCI or PCI Express video card automatically disables Integrated Video When PCI Express video is on Integrated Video must remain disabled Monitor Tracking enable disable Allows ROM to sa...

Page 158: ...s 3 Calling the client management service to perform the desired function The BIOS32 Service Directory is a 16 byte block that begins on a 16 byte boundary between the physical address range of 0E0000h 0FFFFFh The following subsections provide a brief description of key Client Management functions Table 8 3 Client Management Functions INT15 AX Function Mode E800h Get system ID Real 16 32 bit Prot ...

Page 159: ...E816h to retrieve the status of a system s interior temperature This function allows an application to check whether the temperature situation is at a Normal Caution or Critical condition 8 5 3 Drive Fault Prediction The BIOS directly supports Drive Fault Prediction for IDE ATA type hard drives This feature is provided through two Client Management BIOS calls Function INT 15 AX E817h is used to re...

Page 160: ...d setup and also on a system with an OS that does not include a USB driver On such a system a keystroke will generate an SMI and the SMI handler will retrieve the data from the device and convert it to PS 2 data The data will be passed to the keyboard controller and processed as in the PS 2 interface Changing the delay and or typematic rate of a USB keyboard though BIOS function INT 16 is not supp...

Page 161: ...heat sink None Blinks red 3 times 1 Hz Processor not installed Install or reseat CPU None Blinks red 4 times 1 Hz Power failure power supply is overloaded Check voltage selector if applicable stroage devices expansion cards and or system board 5 beeps Blinks red 5 times 1 Hz Pre video memory error Incompatible or incorrectly seated DIMM 6 beeps Blinks red 6 times 1 Hz Pre video graphics error On s...

Page 162: ...ncompatible Memory Module BIOS detected installed DIMM s as being not compatible 214 DIM Configuration Warning A specific error has occurred in a memory device installed in the identified socket 216 Memory Size Exceeds Max Installed memory exceeds the maximum supported by the system 217 DIMM Configuration Warning Unbalanced memory configuration 219 ECC Memory Module Detected ECC Modules not suppor...

Page 163: ...able from front panel USB and audio connectors is missing or not connected properly 1720 SMART Hard Drive Detects Imminent Failure SMART circuitry on an IDE drive has detected possible equipment failure 1721 SMART SCSI Hard Drive Detects Imminent Failure SMART circuitry on a SCSI drive has detected possible equipment failure 1785 MultiBay incorrectly installed For integrated MultiBay USDT systems ...

Page 164: ...ch Check for ROM update Invalid Electronic Serial Number Electronic serial number has become corrupted Network Server Mode Active and No Keyboard Attached Keyboard failure while Network Server Mode enabled Parity Check 2 Keyboard failure while Network Server Mode enabled Table A 2 Continued Power On Self Test POST Messages Error Message Probable Cause ...

Page 165: ...Fast mode out of range 105 04 Port 61 bit 1 not at zero 112 04 Speed test unable to enter Slow mode 105 05 Port 61 bit 0 not at zero 112 05 Speed test unable to enter Mixed mode 105 06 Port 61 bit 5 not at one 112 06 Speed test unable to enter Fast mode 105 07 Port 61 bit 3 not at one 112 07 Speed test system error 105 08 Port 61 bit 1 not at one 112 08 Unable to enter Auto mode in speed test 105 ...

Page 166: ...iled 203 02 Error while saving block in read write test 203 03 Error while restoring block in read write test 204 01 Memory address test failed 204 02 Error while saving block in address test 204 03 Error while restoring block in address test 204 04 A20 address test failed 204 05 Page hit address test failed 205 01 Walking I O test failed 205 02 Error while saving block in walking I O test 205 03 ...

Page 167: ...test failed 303 06 LED test LED command test failed 301 02 Kybd short test interface test failed 303 07 LED test LED command test failed 301 03 Kybd short test echo test failed 303 08 LED test command byte restore test failed 301 04 Kybd short test kybd reset failed 303 09 LED test LEDs failed to light 301 05 Kybd short test kybd reset failed 304 01 Keyboard repeat key test failed 302 xx Failed in...

Page 168: ...ted interrupt received 402 06 Loopback test and cntrl reg failed 402 01 Printer pattern test failed 402 07 Loopback tst data cntrl reg failed 403 xx Printer pattern test failed 402 08 Interrupt test failed 404 xx Parallel port address conflict 402 09 Interrupt test and data reg failed 498 00 Printer failed or not connected 402 10 Interrupt test and control reg failed Table A 7 Video Graphics Error...

Page 169: ... media ID error run Setup 608 xx Diskette drive write protect test Table A 8 Diskette Drive Error Messages Message Probable Cause Message Probable Cause 6xx 01 Exceeded maximum soft error limit 6xx 20 Failed to get drive type 6xx 02 Exceeded maximum hard error limit 6xx 21 Failed to get change line status 6xx 03 Previously exceeded max soft limit 6xx 22 Failed to clear change line status 6xx 04 Pr...

Page 170: ...ization failure 1101 04 Data line fault 1109 02 Clock register rollover failure 1101 05 UART cntrl signal failure 1109 03 Clock reset failure 1101 06 UART THRE bit failure 1109 04 Input line or clock failure 1101 07 UART Data RDY bit failure 1109 05 Address line fault 1101 08 UART TX RX buffer failure 1109 06 Data line fault 1101 09 Interrupt circuit failure 1150 xx Comm port setup error run Setup...

Page 171: ...cuit failure 1205 XX Modem auto answer test 1201 10 COM1 set to invalid inturrupt 1205 01 Time out waiting for SYNC 5 1201 11 COM2 set to invalid 1205 02 Time out waiting for response 5 1201 12 DRVR RCVR control signal failure 1205 03 Data block retry limit reached 5 1201 13 UART control signal interrupt failure 1205 04 RX exceeded carrier lost limit 1201 14 DRVR RCVR data failure 1205 05 TX excee...

Page 172: ... 1203 XX Modem external termination test 1210 05 TX exceeded carrier lost limit 1203 01 Modem external TIP RING failure 1210 06 Time out waiting for dial tone 1203 02 Modem external data TIP RING fail 1210 07 Dial number string too long 1203 03 Modem line termination failure 1210 08 Modem time out waiting for remote response 1204 XX Modem auto originate test 1210 09 Modem exceeded maximum redial l...

Page 173: ...uffer 17xx 09 Failed to format a track 17xx 59 Failed to read sector buffer 17xx 10 Failed diskette sector wrap during read 17xx 60 Failed uncorrectable ECC error 17xx 19 Cntlr failed to deallocate bad sectors 17xx 62 Failed correctable ECC error 17xx 40 Cylinder 0 error 17xx 63 Failed soft error rate 17xx 41 Drive not ready 17xx 65 Exceeded max bad sectors per track 17xx 42 Failed to recalibrate ...

Page 174: ...e controller test xx 71 Pri IDE controller address conflict xx 06 Hard drive ready test xx 72 Sec IDE controller address conflict xx 07 Hard drive recalibrate test xx 80 Disk 0 failure xx 08 Hard drive format bad track test xx 81 Disk 1 failure xx 09 Hard drive reset controller test xx 82 Pri IDE controller failure xx 10 Hard drive park head test xx 90 Disk 0 failure xx 14 Hard drive file write te...

Page 175: ...to erase cartridge 19xx 06 Tape write protect error 19xx 26 Cannot identify drive 19xx 07 Tape already Servo Written 19xx 27 Drive not compatible with controller 19xx 08 Unable to Servo Write 19xx 28 Format gap error 19xx 09 Unable to format 19xx 30 Exception bit not set 19xx 10 Format mode error 19xx 31 Unexpected drive status 19xx 11 Drive recalibration error 19xx 32 Device fault 19xx 12 Tape no...

Page 176: ...est failed 2409 01 320x200 mode color set 1 test failed 2425 01 EGA Mono graphics mode test failed 2410 01 640x200 mode test failed 2431 01 640x480 graphics mode test failed 2411 01 Screen memory page test failed 2432 01 320x200 256 color set test failed 2412 01 Gray scale test failed 2448 01 Advanced VGA controller test failed 2414 01 White screen test failed 2451 01 132 column AVGA test failed 2...

Page 177: ... Network Interface Error Messages Message Probable Cause Message Probable Cause 6000 xx Pointing device interface error 6054 xx Token ring configuration test failed 6014 xx Ethernet configuration test failed 6056 xx Token ring reset test failed 6016 xx Ethernet reset test failed 6068 xx Token ring int loopback test failed 6028 xx Ethernet int loopback test failed 6069 xx Token ring ext loopback te...

Page 178: ...9 Reserved 6nyy 41 SSI bus stayed busy 6nyy 10 Reserved 6nyy 42 ACK REQ lines bad 6nyy 11 Media soft error 6nyy 43 ACK did not deassert 6nyy 12 Drive not ready 6nyy 44 Parity error 6nyy 13 Media error 6nyy 50 Data pins bad 6nyy 14 Drive hardware error 6nyy 51 Data line 7 bad 6nyy 15 Illegal drive command 6nyy 52 MSG C D or I O lines bad 6nyy 16 Media was changed 6nyy 53 BSY never went busy 6nyy 17...

Page 179: ...ssage Probable Cause 8601 01 Mouse ID fails 8601 07 Right block not selected 8601 02 Left mouse button is inoperative 8601 08 Timeout occurred 8601 03 Left mouse button is stuck closed 8601 09 Mouse loopback test failed 8601 04 Right mouse button is inoperative 8601 10 Pointing device is inoperative 8601 05 Right mouse button is stuck closed 8602 xx I F test failed 8601 06 Left block not selected ...

Page 180: ...A 20 www hp com Technical Reference Guide Error Messages and Codes ...

Page 181: ... at the end of the table Applications may interpret multiple keystroke accesses differently or ignore them completely Table B 1 ASCII Character Set Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol Dec Hex Symbol 0 00 Blank 32 20 Space 64 40 96 60 1 01 33 21 65 41 A 97 61 a 2 02 34 22 66 42 B 98 62 b 3 03 35 23 67 43 C 99 63 c 4 04 36 24 68 44 D 100 64 d 5 05 ß 37 25 69 45 E 101 65 e 6 06 38 26 70 46 F...

Page 182: ...t 63 3F 95 5F _ 127 7F 1 128 80 Ç 160 A0 á 192 C0 224 E0 129 81 ü 161 A1 í 193 C1 225 E1 ß 130 82 é 162 A2 ó 194 C2 226 E2 131 83 â 163 A3 ú 195 C3 227 E3 132 84 ä 164 A4 ñ 196 C4 228 E4 133 85 à 165 A5 Ñ 197 C5 229 E5 134 86 å 166 A6 ª 198 C6 230 E6 µ 135 87 ç 167 A7 º 199 C7 231 E7 136 88 ê 168 A8 200 C8 232 E8 137 89 ë 169 A9 201 C9 233 E9 138 8A è 170 AA 202 CA 234 EA 139 8B ï 171 AB 203 CB 23...

Page 183: ...ps Lock active 91 93 Key w corresponding symbol 94 95 Shift and key w corresponding symbol 96 Key w corresponding symbol 97 126 Key w corresponding symbol or Shift and key w corresponding symbol and Caps Lock active 127 Ctrl 128 255 Alt and decimal digit s of desired character 145 91 æ 177 B1 209 D1 241 F1 146 92 Æ 178 B2 210 D2 242 F2 147 93 ô 179 B3 211 D3 243 F3 148 94 ö 180 B4 212 D4 244 F4 14...

Page 184: ...B 4 www hp com Technical Reference Guide ASCII Character Set ...

Page 185: ...h each system Other types may be available as an option This appendix discusses only the keyboard unit The keyboard interface is a function of the system unit and is discussed in Chapter 5 Input Output Interfaces C 2 Keystroke Processing A functional block diagram of the keystroke processing elements is shown in Figure C 1 Power 5 VDC is obtained from the system through the PS 2 type interface The...

Page 186: ...ful completion of the POR and BAT a completion code AAh is sent to the CPU and the scanning process begins The keyboard processor includes a 16 byte FIFO buffer for holding scan codes until the system is ready to receive them Response and typematic codes are not buffered If the buffer is full 16 bytes held a 17th byte of a successive scan code results in an overrun condition and the overrun code r...

Page 187: ...urred The system uses the same timing relationships during reads typically with slightly reduced time periods The enhanced keyboard has three operating modes Mode 1 PC XT compatible Mode 2 PC AT compatible default Mode 3 Select mode keys are programmable as to make only break only typematic Modes can be selected by the user or set by the system Mode 2 is the default mode Each mode produces a diffe...

Page 188: ...e key layouts for keyboards shipped with HPsystems Actual styling details including location of the HP logo as well as the numbers lock caps lock and scroll lock LEDs may vary C 2 3 1 Standard Enhanced Keyboards Figure C 3 U S English 101 Key Keyboard Key Positions Figure C 4 National 102 Key Keyboard Key Positions 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 39...

Page 189: ...40 41 42 43 44 45 46 47 48 30 49 50 51 59 60 61 62 63 64 65 66 67 68 69 70 71 75 76 77 78 79 80 81 82 83 84 85 86 92 93 94 95 96 52 53 54 55 56 57 72 73 74 88 89 90 100 58 91 87 97 98 99 101 110 111 112 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 31 39 32 33 34 35 36 37 38 40 41 42 43 44 45 46 47 48 49 50 51 59 60 61 62 63 64 65 66 67 68 69 70 75 76 77 78 79 80 81...

Page 190: ... Windows Enhanced type keyboard that includes special buttons allowing quick internet navigation The Easy Access Keyboard uses the PS 2 type connection Main key positions same as Windows Enhanced Figures C 5 or C 6 Figure C 7 8 Button Easy Access Keyboard Layout Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7 Btn 8 ...

Page 191: ...d generate an interrupt that initiates a print routine This function may be inhibited by the application Scroll Lock The Scroll Lock key pos 15 when pressed and released invokes a BIOS routine that turns on the scroll lock LED and inhibits movement of the cursor When pressed and released again the LED is turned off and the function is removed This keystroke is always serviced by the BIOS as indica...

Page 192: ...quired twice if in the Windows environment initiates a system reset warm boot that is handled by the BIOS C 2 4 3 Windows Keystrokes Windows enhanced keyboards include three additional key positions Key positions 110 and 111 marked with the Windows logo have the same functionality and are used by themselves or in combination with other keys to perform specific hot key type functions for the Window...

Page 193: ...tionality described below All buttons may be re programmed by the user through the Easy Access utility 8 Button Easy Access Keyboard Button Description Default Function 1 Go to favorite web site Customer web site of choice 2 Go to AltaVista AltaVista web site 3 Search AltaVista search engine 4 Check Email Launches user Email 5 Business Community Industry specification info 6 Market Monitor Launche...

Page 194: ...itch closure couldn t be identified BAT Completion AAh Indicates to the system that the BAT has been successful BAT Failure FCh Indicates failure of the BAT by the keyboard Echo EEh Indicates that the Echo command was received by the keyboard Acknowledge ACK FAh Issued by the keyboard as a response to valid system inputs except the Echo and Resend commands Resend FEh Issued by the keyboard followi...

Page 195: ... required by the BIOS This mode was made necessary with the development of the Enhanced III keyboard which includes additional functions over earlier standard keyboards Applications should use BIOS function INT 16h with AH 10h 11h and 12h for obtaining codes and status data In Mode 2 the keyboard generates the Break code a two byte sequence that consists of a Make code immediately preceded by F0h ...

Page 196: ...0 3E 3E F0 3E 26 9 0A 8A 46 F0 46 46 F0 46 27 0 0B 8B 45 F0 45 45 F0 45 28 0C 8C 4E F0 4E 4E F0 4E 29 0D 8D 55 F0 55 55 F0 55 30 2B AB 5D F0 5D 5C F0 5C 31 Backspace 0E 8E 66 F0 66 66 F0 66 32 Insert E0 52 E0 D2 E0 AA E0 52 E0 D2 E0 2A 4 E0 2A E0 52 E0 D2 E0 AA 6 E0 70 E0 F0 70 E0 F0 12 E0 70 E0 F0 70 E0 12 5 E0 12 E0 70 E0 F0 70 E0 F0 12 6 67 na 33 Home E0 47 E0 D2 E0 AA E0 52 E0 D2 E0 2A 4 E0 2A...

Page 197: ...F0 4D 50 1A 9A 54 F0 54 54 F0 54 51 1B 9B 5B F0 5B 5B F0 5B 52 Delete E0 53 E0 D3 E0 AA E0 53 E0 D3 E0 2A 4 E0 2A E0 53 E0 D3 E0 AA 6 E0 71 E0 F0 71 E0 F0 12 E0 71 E0 F0 71 E0 12 5 E0 12 E0 71 E0 F0 71 E0 F0 12 6 64 F0 64 53 End E0 4F E0 CF E0 AA E0 4F E0 CF E0 2A 4 E0 2A E0 4F E0 CF E0 AA 6 E0 69 E0 F0 69 E0 F0 12 E0 69 E0 F0 69 E0 12 5 E0 12 E0 69 E0 F0 69 E0 F0 12 6 65 F0 65 54 Page Down E0 51 ...

Page 198: ... 4B 69 27 A7 4C F0 4C 4C F0 4C 70 28 A8 52 F0 52 52 F0 52 71 Enter 1C 9C 5A F0 5A 5A F0 5A 72 4 4B CB 6 6B F0 6B 6 6B na 6 73 5 4C CC 6 73 F0 73 6 73 na 6 74 6 4D CD 6 74 F0 74 6 74 na 6 75 Shift left 2A AA 12 F0 12 12 F0 12 76 Z 2C AC 1A F0 1A 1A F0 1A 77 X 2D AD 22 F0 22 22 F0 22 78 C 2E AE 21 F0 21 21 F0 21 79 V 2F AF 2A F0 2A 2A F0 2A 80 B 30 B0 32 F0 32 32 F0 32 81 N 31 B1 31 F0 31 31 F0 31 8...

Page 199: ...a 96 Ctrl right E0 1D E0 9D E0 14 F0 E0 14 58 na 97 E0 4B E0 CB E0 AA E0 4B E0 CB E0 2A 4 E0 2A E0 4B E0 CB E0 AA 6 E0 6B Eo F0 6B E0 F0 12 E0 6B E0 F0 6B E0 12 5 E0 12 E0 6B E0 F0 6B E0 F0 12 6 61 F0 61 98 E0 50 E0 D0 E0 AA E0 50 E0 D0 E0 2A 4 E0 2A E0 50 E0 D0 E0 AA 6 E0 72 E0 F0 72 E0 F0 12 E0 72 E0 F0 72 E0 12 5 E0 12 E0 72 E0 F0 72 E0 F0 12 6 60 F0 60 99 E0 4D E0 CD E0 AA E0 4D E0 CD E0 2A 4 ...

Page 200: ...0 27 E0 F0 27 E0 12 5 E0 12 E0 27 E0 F0 27 E0 F0 12 6 8C F0 8C 112 Win Apps 7 E0 5D E0 DD E0 AA E0 5D E0 DD E0 2A 4 E0 2A E0 5D E0 DD E0 AA 6 E0 2F E0 F0 2F E0 F0 12 E0 2F E0 F0 2F E0 12 5 E0 12 E0 2F E0 F0 2F E0 F0 12 6 8D F0 8D Btn 1 8 E0 1E E0 9E E0 1C E0 F0 1C 95 F0 95 Btn 2 8 E0 26 E0 A6 E0 4B E0 F0 4B 9C F0 9C Btn 3 8 E0 25 E0 A5 E0 42 E0 F0 42 9D F0 9D Btn 4 8 E0 23 E0 A3 E0 33 E0 F0 33 9A ...

Page 201: ...Systems that do not provide a PS 2 interface will ship with a USB keyboard For a detailed description of the PS 2 and USB interfaces refer to Chapter 5 Input Output of this guide The keyboard cable connectors and their pinouts are described in the following figures Figure C 9 PS 2 Keyboard Cable Connector Male Figure C 10 USB Keyboard Cable Connector Male Pin Function 1 Data 2 Not connected 3 Grou...

Page 202: ...C 18 www hp com Technical Reference Guide Keyboard ...

Page 203: ...face 5 7 F G graphics subsystem 6 1 H HD Audio Controller 5 31 header pinouts 7 15 I I O map 4 25 IDE PATA Connector 5 3 integrated graphics controller IGC 6 2 interrupts hardware 4 11 interrupts PCI 4 13 K keyboard interface 5 24 L LED indications 4 23 8 5 M Memory 3 4 memory allocation 6 3 memory map 3 7 model numbering 1 2 mouse pointing device interface 5 18 N Network Boot 8 4 Network Interfac...

Page 204: ... Smart Cover Lock 2 22 Smart Cover Sensor 2 21 SMBIOS 8 18 SPD address map 3 6 specifications physical 2 26 system ID 8 17 T Temperature Status 8 17 U Universal Serial Bus USB interface 5 25 upgrading BIOS 8 2 upgrading graphics 6 5 USB 5 25 V VGA connector 6 6 W Web sites Adobe Systems Inc 1 1 HP 1 1 Intel Corporation 1 1 Standard Microsystems Corporation 1 1 USB user group 1 1 ...

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