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HP Compaq d330 DT, Technical Reference Manual

The HP Compaq d330 DT offers seamless performance with its powerful hardware. For those seeking in-depth technical information, the product's Technical Reference Manual is available for free download at manualshive.com. Access the comprehensive manual to learn all about this remarkable PC's features and functionalities.

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Chapter 6  Integrated Graphics Subsystem

 

   hp compaq d330 and d530 Series of Personal Computers 
    Featuring the Intel Pentium 4 Processor 

     

 

 

First Edition - June 2003

 

6-8 

 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 
 

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Summary of Contents for Compaq d330 DT

Page 1: ...his document provides information on the design architecture function and capabilities of the hp compaq d330 and d530 This information may be used by engineers technicians administrators or anyone needing detailed information on the products covered Document Part Number 340154 001 ...

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Page 3: ... in the 8 x 11 inch format The title block below may can be copied and or cut out and placed into a slip or taped onto the binder hp compaq d330 and d530 Personal Computers featuring the Intel Pentium 4 processor and Intel 865G chipset TRG ...

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Page 5: ...nformation in this document is provided as is without warranty of any kind including but not limited to the implied warranties of merchantability and fitness for a particular purpose and is subject to change without notice The warranties for HP products are set forth in the express limited warranty statement accompanying such products Nothing herein should be construed as constituting an additiona...

Page 6: ...Technical Reference Guide hp compaq d330 and d530 Series Personal Computers Featuring the Intel Pentium 4 Processor First Edition June 2003 ii ...

Page 7: ...2 3 1 CABINET LAYOUTS 2 5 2 3 2 CHASSIS LAYOUTS 2 7 2 3 3 BOARD LAYOUTS 2 13 2 4 SYSTEM ARCHITECTURE 2 14 2 4 1 INTEL PENTIUM 4 PROCESSOR 2 16 2 4 2 CHIPSET 2 17 2 4 3 SUPPORT COMPONENTS 2 17 2 4 4 SYSTEM MEMORY 2 18 2 4 5 MASS STORAGE 2 18 2 4 6 SERIAL AND PARALLEL INTERFACES 2 18 2 4 7 UNIVERSAL SERIAL BUS INTERFACE 2 18 2 4 8 NETWORK INTERFACE CONTROLLER 2 19 2 4 9 GRAPHICS SUBSYSTEM 2 19 2 4 1...

Page 8: ... REGISTER MAP AND MISCELLANEOUS FUNCTIONS 4 29 4 8 1 SYSTEM I O MAP 4 29 4 8 2 LPC47B387 I O CONTROLLER FUNCTIONS 4 30 CHAPTER 5 INPUT OUTPUT INTERFACES 5 1 INTRODUCTION 5 1 5 2 ENHANCED IDE SATA INTERFACES 5 1 5 2 1 EIDE INTERFACES 5 1 5 2 2 SATA INTERFACES 5 4 5 3 DISKETTE DRIVE INTERFACE 5 6 5 3 1 DISKETTE DRIVE PROGRAMMING 5 7 5 3 2 DISKETTE DRIVE CONNECTOR 5 9 5 4 SERIAL INTERFACE 5 10 5 4 1 ...

Page 9: ... 36 5 9 4 NIC PROGRAMMING 5 36 5 9 5 NIC CONNECTOR 5 37 5 9 6 NIC SPECIFICATIONS 5 37 CHAPTER 6 INTREGRATED GRAPHICS SUBSYSTEM 6 1 INTRODUCTION 6 1 6 2 FUNCTIONAL DESCRIPTION 6 2 6 2 1 VIDEO MEMORY ALLOCATION REPORTING 6 4 6 3 DISPLAY MODES 6 5 6 4 PROGRAMMING 6 6 6 5 UPGRADING THE GRAPHICS SUBSYTEM 6 6 6 6 VGA MONITOR CONNECTOR 6 7 CHAPTER 7 POWER SUPPLY AND DISTRIBUTION 7 1 INTRODUCTION 7 1 7 2 ...

Page 10: ... 3 POWER ON SELF TEST POST MESSAGES A 2 A 4 SYSTEM ERROR MESSAGES 1XX XX A 3 A 5 MEMORY ERROR MESSAGES 2XX XX A 4 A 6 KEYBOARD ERROR MESSAGES 30X XX A 4 A 7 PRINTER ERROR MESSAGES 4XX XX A 5 A 8 VIDEO GRAPHICS ERROR MESSAGES 5XX XX A 5 A 9 DISKETTE DRIVE ERROR MESSAGES 6XX XX A 6 A 10 SERIAL INTERFACE ERROR MESSAGES 11XX XX A 6 A 11 MODEM COMMUNICATIONS ERROR MESSAGES 12XX XX A 7 A 12 SYSTEM STATU...

Page 11: ...E PROCESSING C 2 C 2 1 PS 2 TYPE KEYBOARD TRANSMISSIONS C 3 C 2 2 USB TYPE KEYBOARD TRANSMISSIONS C 4 C 2 3 KEYBOARD LAYOUTS C 5 C 2 4 KEYS C 8 C 2 5 KEYBOARD COMMANDS C 11 C 2 6 SCAN CODES C 11 C 3 CONNECTORS C 16 hp compaq d330 and d530 Series Personal Computers Featuring the Intel Pentium 4 Processor First Edition June 2003 vii ...

Page 12: ... TRANSFER PEAK TRANSFER RATE 2128 MB S 4 12 FIGURE 4 9 1 5 VOLT AGP BUS CONNECTOR 4 13 FIGURE 4 10 MASKABLE INTERRUPT PROCESSING BLOCK DIAGRAM 4 14 FIGURE 4 11 CONFIGURATION MEMORY MAP 4 22 FIGURE 4 12 FAN CONTROL BLOCK DIAGRAM 4 28 FIGURE 5 1 40 PIN IDE CONNECTOR ON SYSTEM BOARD 5 3 FIGURE 5 2 7 PIN SATA CONNECTOR ON SYSTEM BOARD 5 5 FIGURE 5 3 34 PIN DISKETTE DRIVE CONNECTOR 5 9 FIGURE 5 4 SERIA...

Page 13: ...ESSING ELEMENTS BLOCK DIAGRAM C 2 FIGURE C 2 PS 2 KEYBOARD TO SYSTEM TRANSMISSION TIMING DIAGRAM C 3 FIGURE C 3 U S ENGLISH 101 KEY KEYBOARD KEY POSITIONS C 5 FIGURE C 4 NATIONAL 102 KEY KEYBOARD KEY POSITIONS C 5 FIGURE C 5 U S ENGLISH WINDOWS 101W KEY KEYBOARD KEY POSITIONS C 6 FIGURE C 6 NATIONAL WINDOWS 102W KEY KEYBOARD KEY POSITIONS C 6 FIGURE C 7 7 BUTTON EASY ACCESS KEYBOARD LAYOUT C 7 FIG...

Page 14: ...8 TABLE 4 9 DMA PAGE REGISTER ADDRESSES 4 19 TABLE 4 10 DMA CONTROLLER REGISTERS 4 20 TABLE 4 11 CLOCK GENERATION AND DISTRIBUTION 4 21 TABLE 4 12 CONFIGURATION MEMORY CMOS MAP 4 23 TABLE 4 13 SYSTEM BOOT ROM FLASH STATUS LED INDICATIONS 4 26 TABLE 4 14 SYSTEM OPERATIONAL STATUS LED INDICATION 4 27 TABLE 4 15 SYSTEM I O MAP 4 29 TABLE 4 16 LPC47B387 I O CONTROLLER REGISTERS 4 30 TABLE 5 1 EIDE PCI...

Page 15: ...CODES 8 2 TABLE 8 2 BOOT ERROR CODES 8 5 TABLE 8 3 SETUP UTILITY FUNCTIONS 8 6 TABLE 8 4 CLIENT MANAGEMENT FUNCTIONS INT15 8 12 TABLE 8 5 PNP BIOS FUNCTIONS 8 15 TABLE A 1 BEEP KEYBOARD LED CODES A 1 TABLE A 2 POWER ON SELF TEST POST MESSAGES A 2 TABLE A 3 SYSTEM ERROR MESSAGES A 3 TABLE A 4 MEMORY ERROR MESSAGES A 4 TABLE A 5 KEYBOARD ERROR MESSAGES A 4 TABLE A 6 PRINTER ERROR MESSAGES A 5 TABLE ...

Page 16: ...Technical Reference Guide hp compaq d330 and d530 Series Personal Computers Featuring the Intel Pentium 4 Processor First Edition June 2003 xii ...

Page 17: ...ument or in hardcopy form 1 1 1 ONLINE VIEWING Online viewing allows for quick navigating and convenient searching through the document A color monitor will also allow the user to view the color shading used to highlight differential data A softcopy of the latest edition of this guide is available for downloading in pdf file format at the URL listed below http www hp com Viewing the file requires ...

Page 18: ...orks 2003 NA only OS 1 Linux 2 Win2000 3 XP Home 4 XP Pro Graphics Blank integrated v DVI add in card AA GFrc2 MX200 64 MB AB GFrc2 MX400 32 MB AE GFrc4 MX420 64 MB AF Quadro4 200NVS AG Quadro4 400NVS AH Quadro4 100NVS VGA AJ Quadro4 100NVA DVI AQ GFrc4 MX440 64 MB Memory speed B DDR266 single channel C DDR266 dual channel D DDR333 single channel E DDR333 dual channel F DDR400 single channel G DDR...

Page 19: ...and 4 Example B IRQ3 7 9 IRQ signals 3 through 7 and IRQ signal 9 1 5 3 REGISTER NOTATION AND USAGE This guide uses standard Intel naming conventions in discussing the microprocessor s CPU internal registers Registers that are accessed through programmable I O using an indexing scheme are indicated using the following format 03C5 17h Index port Data port In the example above register 03C5 17h is a...

Page 20: ...t w packet interface extensions AVI audio video interleaved AVGA Advanced VGA AWG American Wire Gauge specification BAT Basic assurance test BCD binary coded decimal BIOS basic input output system bis second new revision BNC Bayonet Neill Concelman connector type bps or b s bits per second BSP Bootstrap processor BTO Built to order CAS column address strobe CD compact disk CD ROM compact disk read...

Page 21: ...tion EISA extended ISA EPP enhanced parallel port EIDE enhanced IDE ESCD Extended System Configuration Data format EV Environmental Variable data ExCA Exchangeable Card Architecture FIFO first in first out FL flag register FM frequency modulation FPM fast page mode RAM type FPU Floating point unit numeric or math coprocessor FPS Frames per second ft Foot feet GB gigabyte GMCH Graphics memory contr...

Page 22: ...tensions MPEG Motion Picture Experts Group ms millisecond MSb MSB most significant bit most significant byte mux multiplex MVA motion video acceleration MVW motion video window n variable parameter value NIC network interface card controller NiMH nickel metal hydride NMI non maskable interrupt NRZI Non return to zero inverted ns nanosecond NT nested task flag NTSC National Television Standards Com...

Page 23: ...R Singles data rate memory SDRAM Synchronous Dynamic RAM SEC Single Edge Connector SECAM sequential colour avec memoire sequential color with memory SF sign flag SGRAM Synchronous Graphics RAM SIMD Single instruction multiple data SIMM single in line memory module SMART Self Monitor Analysis Report Technology SMI system management interrupt SMM system management mode SMRAM system management RAM SP...

Page 24: ... Telecommunications Information Administration TPE twisted pair ethernet TPI track per inch TTL transistor transistor logic TV television TX transmit UART universal asynchronous receiver transmitter UDMA Ultra DMA URL Uniform resource locator us µs microsecond USB Universal Serial Bus UTP unshielded twisted pair V volt VAC Volts alternating current VDC Volts direct current VESA Video Electronic St...

Page 25: ...rporating the PCI bus All models are easily upgradeable and expandable to keep pace with the needs of the office enterprise hp compaq d530 Small Form Factor hp compaq d530 Configurable Minitower hp compaq d330 Slim Tower hp compaq d330 Microtower hp compaq d530 Ultra Slim Desktop hp compaq d330 Desktop Figure 2 1 hp Compaq d330 and d530 Series Personal Computers This chapter includes the following...

Page 26: ...use Table 2 1 shows the differences in features between the different PC series based on form factor Table 2 1 Feature Difference Matrix Table 2 1 Difference Matrix by Form Factor USDT ST SFF DT µT CMT Series D530 D330 D530 D330 D330 D530 System Board Type Proprietary µATX µATX µATX µATX µATX Series d530 d330 d530 d330 d330 d530 DIMM sockets 2 4 4 4 4 4 Drive bays total 2 3 3 5 5 6 AGP slot none L...

Page 27: ... Hard drives controllers 40 GB 5400 RPM UATA 100 hard drive 40 GB 7200 RPM UATA 100 hard drive 80 GB 7200 RPM UATA 100 hard drive 160 GB 7200 RPM UATA 100 hard drive Removeable media drives 16x 10x 40x CD RW drive 10x 40x Max DVD ROM drive LS 120 Super Disk drive PCI DXR DVD Decoder kit Graphics Monitors Compaq P700 17 CRT Compaq P900 19 CRT Compaq P1100 21 CRT Compaq TFT5010 15 Flat Panel Compaq ...

Page 28: ...tower an ATX type unit providing the most expandability and being adaptable to desktop horizontal or floor standing vertical placement The following subsections describe the mechanical physical aspects of models CAUTION Voltages are present within the system unit whenever the unit is plugged into a live AC outlet regardless of the system s Power On condition Always disconnect the power cable from ...

Page 29: ...ktop Item Description Item Decription 1 Microphone In Jack 7 Diskette drive activity 2 Headphone Out Jack 8 Diskette drive eject button 3 Universal Serial Bus Connectors 9 CD ROM drive headphone jack 4 Power LED 10 CD ROM drive volume control 5 Hard Drive Activity LED 11 CD ROM drive activity LED 6 Power Button 12 LED CD ROM drive open close button Figure 2 2 Front Views hp compaq d330 and d530 Se...

Page 30: ...12 6 3 9 2 11 13 7 5 4 10 8 Microtower Configurable Minitower Desktop Item Description Item Description 1 Voltage select switch 8 VGA monitor connector 2 AC power connector 9 Parallel connector 3 Audio input jack 10 Serial port A connector 4 Audio output jack 11 Keyboard connector 5 Microphone input jack 12 Mouse connector 6 NIC LAN connector 13 Serial port B connector 7 USB connectors Figure 2 3 ...

Page 31: ...sktop USDT chassis used for the d530 models uses a low profile minimal footprint design with the following features Easy access to DIMM and processor sockets PCI slot horizontally mounted Back Power Supply System Board PCI slot Horizontal Multibay drive Lower externally accessible Processor Fan Internal drive Upper Speaker Front Figure 2 4 Ultra Slim Desktop Chassis Layout Top View hp compaq d330 ...

Page 32: ... in tower stand supplied NOTE The d330 slim tower chassis may be ordered in the chassis configuration that uses a riser card to provide two full height PCI slots This configuration will very similar to the layout shown in Figure 2 6 for the small form factor Low Profile AGP Slot Low Profile PCI Slot 1 Low Profile PCI Slot 2 Low Profile PCI Slot 3 System Board Back Front Speaker Multibay Drive Powe...

Page 33: ...kets Two full height half length PCI slots One low profile AGP 8X slot Upper Drive Bays Tilting Assembly Processor Fan PCI Conn 2 Slot 2 PCI Conn 1 Slot 1 Slots On Backplane Rear View Speaker Assembly Hood Lock Solenoid Optional Card Cage Assembly System Board Power Supply Back Front Figure 2 6 Small Form Factor Chassis Layout Top View hp compaq d330 and d530 Series Personal Computers Featuring th...

Page 34: ...expansion slots and all socketed system board components Smart Cover Sensor Switch Hood Lock Solenoid Optional Lower Drive Bays PCI Slot 1 PCI Slot 2 PCI Slot 3 AGP Slot Auxiliary Chassis Fan Air Baffle Assembly Speaker Power Supply Back Upper Drive Bays Tilting Assembly Front Figure 2 7 Desktop Chassis Layout Top View hp compaq d330 and d530 Series Personal Computers Featuring the Intel Pentium 4...

Page 35: ...sition Easy access to expansion slots and all socketed system board components Front Back Power Supply Hood Lock Solenoid Optional Chassis Fan AGP Slot PCI Slot 1 PCI Slot 2 PCI Slot 3 Processor Heat Sink Fan Assembly Drive Lock Externally Accessible Drive Bays Internal Drive Bays Speaker Figure 2 8 Microtower Chassis Layout Left Side View hp compaq d330 and d530 Series Personal Computers Featurin...

Page 36: ...xpansion slots and all socketed system board components System Board Processor Heat Sink Fan Assembly PCI Slot 1 PCI Slot 2 PCI Slot 3 PCI Slot 4 PCI Slot 5 AGP Slot Chassis Fan Power Supply Back Front Drive Lock Externally Accessible Drive Bays Internal Drive Bays Hood Lock Solenoid Optional Speaker PCI Expansion Board Figure 2 9 Configurable Minitower Chassis Layout Left Side View Minitower conf...

Page 37: ...rial ATA connector 8 Audio input top output Microphone input 28 Hood lock connector 9 NIC connector top USB connectors 2 29 Battery 10 USB connectors 2 30 Hood sense connector 11 VGA monitor connector 31 Power button LED HD LED connector 12 NIC connector 32 CMOS clear switch 13 Parallel connector 33 Clear password jumper 14 Serial port A connector 34 Primary serial ATA connector 15 PS 2 Mouse top ...

Page 38: ... 2 All system also include at least one 32 bit PCI slots for expandability and include a 10 100 1000 network interface controller An SMC 47B387 super I O Controller provides serial parallel keyboard mouse and diskette drive interface functions The 865G chipset includes the 82865G GMCH designed to support the Pentium 4 processor with an FSB speed of 400 533 or 800 MHz The 82865 GMCH also includes a...

Page 39: ...o Subsystem SDRAM Cntlr 400 533 800 MHz FSB Memory Bus 0 82865G GMCH Pentium 4 Processor PCI Slot s Hub Link Bus LPC Bus 865G Chipset UATA Hard Drive 33 MHz 32 Bit PCI Bus Diskette I F Keyboard Mouse I F LPC47B387 I O Controller Parallel I F Serial I F 2 Sec IDE Cntlr 82802 FWH Power Supply USB Cntlrs Pri IDE Cntlr 82801EB ICH5 DDR SDRAM Figure 2 11 System Architecture Block diagram hp compaq d330...

Page 40: ...hat uses hyper pipelined technology and a rapid execution engine that runs at twice the processor s core speed These systems employ an mPGA478B zero insertion force ZIF socket designed for mounting a Flip Chip FC PGA2 processor package Figure 2 12 Lock Unlock Handle Heatsink Fan Assembly 1 Processor in FC PGA 2 Package Fan Assembly Release Tab Heat Sink Retaining Clips Socket Figure 2 12 Processor...

Page 41: ...nterface controller 82802 FWH 2 Loaded with hp Compaq BIOS NOTE 1 Or equivalent component 2 4 3 SUPPORT COMPONENTS Input output functions not provided by the chipset are handled by other support components Some of these components also provide housekeeping and various other functions as well Table 2 4 shows the functions provided by the support components Table 2 4 Support Component Functions Tabl...

Page 42: ...160 GB UATA100 IDE hard drive and one removable media drive such as a CD ROM drive The removable media device in the USDT form factor must be a multibay device 2 4 6 SERIAL AND PARALLEL INTERFACES All models except USDT form factor models include two serial ports and a parallel port accessible at the rear of the chassis Each serial interface is RS 232 C 16550 compatible and supports standard baud ...

Page 43: ... use a portion of system memory according to the needs of the application Table 2 5 lists the key features of the integrated graphics subsystem Table 2 5 Integrated Graphics Subsystem Statistics Table 2 5 Integrated Graphics Subsystem Statistics 82865G GMCH Integrated Graphics Controller Recommended for Hi 2D Entry 3D Bus Type Integrated Graphics Controller Mem Amount uses system memory Mem Type U...

Page 44: ...10 C Hr 24 o to 140 o F 30 o to 60 o C max rate of change 20 C Hr Shock w o damage 5 Gs 1 20 Gs 1 Vibration 0 000215 G 2 Hz 10 300 Hz 0 0005 G 2 Hz 10 500 Hz Humidity 10 90 Rh 28 o C max wet bulb temperature 5 95 Rh 38 7 o C max wet bulb temperature Maximum Altitude 10 000 ft 3048 m 2 30 000 ft 9144 m 2 NOTE 1 Peak input acceleration during an 11 ms half sine shock pulse 2 Maximum rate of change 1...

Page 45: ... System weight may vary depending on installed drives peripherals 2 Without Multibay device installed 3 Minitower configuration For desktop configuration swap Height and Width dimensions 4 Applicable to unit in desktop orientation only and assumes reasonable type of load such as a monitor Table 2 9 Diskette Drive Specifications Table 2 9 Diskette Drive Specifications Compaq SP 179161 001 Parameter...

Page 46: ... mm 15 mm Disc Diameter 8 12 cm 8 12 cm Disc Thickness 1 2 mm 1 2 mm Track Pitch 1 6 um 1 6 um Laser Beam Divergence Output Power Type Wave Length 53 5 1 5 53 6 0 14 mW GaAs 790 25 nm 53 5 1 5 53 6 0 14 mW GaAs 790 25 nm Average Access Time Random Full Stroke 100 ms 150 ms 120 ms 200 ms Audio Output Level 0 7 Vrms 0 7 Vrms Cache Buffer 128 KB 128 KB Table 2 11 Hard Drive Specifications Table 2 11 ...

Page 47: ...n Socket XMM3 Ch 2 DIMM Socket XMM4 Ch 1 DIMM In Socket XMM1 Ch 1 DIMM Socket XMM2 ST SFF DT MT CMT System Memory Ch 2 DIMM In Socket XMM2 XMM1 Ch 1 DIMM In Socket USDT System Memory Hub I F Memory Cntlr FSB I F 82865G GMCH AGP I F Pentium 4 Processor Covered in Chapter 4 Figure 3 1 Processor Memory Subsystem Architecture This chapter includes the following topics Pentium 4 processor 3 2 page 3 2 ...

Page 48: ...g to be removed from the main processing loop Rapid Execution Engine Arithmetic Logic Units ALUs run at twice 2x processing frequency for higher throughput and reduced latency 256 or 512 KB Advanced transfer L2 cache Using 32 byte wide interface at processing speed the L2 cache can provide an increase of 3x over a Pentium III of equal speed Advanced dynamic execution Using a larger 4K branch targe...

Page 49: ... 8 GHz 400 MHz 256 KB 1 80 1 80 GHz 3 6 GHz 400 MHz 256 KB 1 70 1 70 GHz 3 4 GHz 400 MHz 256 KB 1 6 1 60 GHz 3 2 GHz 400 MHz 256 KB Figure 3 2 Pentium 4 Processor Internal Architecture The Pentium 4 increases processing speed with higher clock speeds made possible with hyper pipelined technology that can handle significantly more instructions at a time The Pentium 4 features a branch prediction me...

Page 50: ...processor die The heat sink and attachment clip are specially designed provide maximum heat transfer from the processor component CAUTION Attachment of the heatsink to the processor is critical on these systems Improper attachment of the heatsink will likely result in a thermal condition Although the system is designed to detect thermal conditions and automatically shut down such a condition could...

Page 51: ...onal Compaq added features such as part number and serial number The SPD format as supported in this system SPD rev 1 is shown in Table 3 3 The key SPD bytes that BIOS checks for compatibility are 2 9 10 18 23 24 and 126 If BIOS detects EDO a memory incompatible message will be displayed and the system will halt These systems are shipped with non ECC DIMMs only Refer to chapter 8 for a description...

Page 52: ...es Supported 4 127 Reserved 19 CS Latency 4 128 131 Compaq header CPQ1 9 20 Write Latency 4 132 Header checksum 9 21 DIMM Attributes 133 145 Unit serial number 9 10 22 Memory Device Attributes 146 DIMM ID 9 11 23 Min CLK Cycle Time at CL X 1 7 147 Checksum 9 24 Max Acc Time From CLK CL X 1 7 Reserved 9 NOTES 1 Programmed as 128 bytes by the DIMM OEM 2 Must be programmed to 256 bytes 3 High order b...

Page 53: ...ded Memory 15 MB Extended BIOS Area Base Memory 512 KB Fixed Mem Area 128 KB System BIOS Area 64 KB Graphics SMRAM RAM 128 KB FFFF FFFFh High BIOS Area 2 MB Top of DRAM 16 MB 1 MB 640 KB 512 KB NOTE All locations in memory are cacheable Base memory is always mapped to DRAM The next 128 KB fixed memory area can through the north bridge be mapped to DRAM or to PCI space Graphics RAM area is mapped t...

Page 54: ...Memory Buffer Strength 55h 04 05h Command 0006h 70h Multi Transaction Timer 00h 06 07h Status 1 71h CPU Latency Timer 10h 08h Revision ID 72h SMRAM Control 02h 0A 0Bh Class Code 90h Error Command 00h 0Dh Latency Timer 00h 91h Error Status Register 0 00h 0Eh Header Type 00h 92h Error Status Register 1 00h 10 13h Aperture Base Config 2 93h Reset Control 00h 50 51h PAC Config Reg 00h A0 A3h AGP Capab...

Page 55: ... and configuration memory 4 6 page 4 22 System management 4 7 page 4 24 Register map and miscellaneous functions 4 8 page 4 29 This chapter covers functions provided by off the shelf chipsets and therefore describes only basic aspects of these functions as well as information unique to the systems covered in this guide For detailed information on specific components refer to the applicable manufac...

Page 56: ...re 4 1 The PCI bus 0 is internal to the chipset components and is not physically accessible The AGP bus that services the AGP slot if present is designated as PCI bus 1 All PCI slots and the NIC function internal to the ICH5 reside on PCI bus 2 Figure 4 1 PCI Bus Devices and Functions 82865G GMCH Component Integrated Graphics Controller Mem Cntlr Function PCI Bus 0 PCI Bus 1 AGP Bus AGP Bridge Fun...

Page 57: ...CI Device Number S device for access ction of 10 8 Function Number Selects fun evice selected PCI d Register Index S Configuration Cy 4 2 1 1 I O and Memory Cycles essing ucted a dword at a time with ddressing assumed to increment accordingly four bytes at a time 4 2 1 2 Configuration Cycles vice by t 0CF8h holds a value that specifies the PCI bus PCI evice and specific register to be accessed The...

Page 58: ... Index Register 0CF8h Results in NOTES 1 Bits 1 0 00 Type 0 Cycle 01 Type 1 cycle ed on Type 00 cycle Number Number s ar fu hi co ponent 1 Bus Figure 4 2 Configuration Cycle Table 4 1 shows the standard configuration of device num components and slots residing on a PCI bus iguration Access Table 4 1 ompon Configurat cess PCI Component Notes Function Dev PCI Bus IDSEL Wired to ice 82865G GMCH dge p...

Page 59: ...s I O Base Upper 16 Bits Device ID Vendor ID 0 7 8 15 16 23 24 31 Command Revision ID Line Size Class Code Hdr Type Status PCI Configuration Space Type 1 Configuration Space Header Data required by PCI protocol Not required Figure 4 3 PCI Configuration Space Mapping Each PCI device is identified with a vendor ID assigned to the vendor by the PCI Special Interest Group and a device ID assigned by t...

Page 60: ...action Table 4 3 shows the grant and request signals assignments for the devices on the PCI bus Table 4 3 PCI Bus Mastering Devices Table 4 3 PCI Bus Mastering Devices Device REQ GNT Line Note PCI Connector Slot 1 REQ0 GNT0 PCI Connector Slot 2 REQ1 GNT1 1 PCI Connector Slot 3 REQ2 GNT2 2 PCI Connector Slot 4 REQ3 GNT3 3 PCI Connector Slot 5 REQ4 GNT4 3 lot GREQ GGNT AGP S OTE N only 1 ST SFF DT M...

Page 61: ...I Power Management Interface Specification rev 1 0 The PCI Power Management Enable PME signal is supported by the chipset and allows compliant PCI and AGP peripherals to initiate the power management routine 4 2 6 PCI SUB BUSSES The chipset implements two data busses that are supplementary in operation to the PCI bus and the ICH5 This bus is transparent software and is not accessible for expansion...

Page 62: ...D GND 43 3 3 VDC PAR 74 AD55 AD54 13 GND GND 44 C BE1 AD15 75 AD53 5 VDC 14 RSVD UX C 3 3 A 45 AD14 3 3 VD 76 GND AD52 15 GND RST 46 GND AD13 77 AD51 AD50 16 CLK 5 VDC 47 AD12 AD11 78 AD49 GND 17 GND GNT 48 AD10 GND 79 5 VDC AD48 18 REQ GND 49 GND AD09 80 AD47 AD46 19 5 VDC PME 50 Key Key 81 AD45 GND 20 AD31 AD30 51 Key Key 82 GND AD44 21 AD29 3 3 VDC 52 AD08 C BE0 83 AD43 AD42 22 GND AD28 53 AD07...

Page 63: ...s generally as the AGP master but can also ehave as a PCI target during fast writes from the GMCH b ey differences between the AGP interface and the PCI interface are as follows K Address phase and associated data transfer phase are disconnected transactions Addressing and data transferring occur as contiguous actions on the PCI bus On th e AGP bus a request pecified by the graphics address re map...

Page 64: ...Each transaction resulting from a request involves at least eight bytes requiring the 32 AD lines to handle at least two transfers per request The 82865 GMCH supports four transfer rates 1X 2X 4X and 8X Regardless of the rate used the speed of the bus clock is constant at 66 MHz The following subsections describe how the use of additional strobe signals makes possible higher ransfer rates t GP 1X ...

Page 65: ... byte transfer occurs in one CLK cycle Figure 4 6 The first four bytes DnA are latched by the receiving agent on the falling edge of AD_STBx and the second four bytes DnB are latched A A T1 T2 T3 T4 T5 T6 T7 TRDY GNT CLK AD_STBx AD D1A D2A D3A D1B D2B D3B D4A D4B ST0 2 00x xxx xxx xxx xxx xxx F F AGP 4X Transfers The AGP 4X transfer rate allows sixteen bytes of data to be transferred in one clock ...

Page 66: ...transfer rate allows 32 bytes of data to be transferred in one clock cycle As with th other transfer rates the 66 MHz CLK signal is used only for qualifying control signals while strobe signals are used to latch each 4 byte transfer on the AD lines As shown in Fi b e A T1 T2 1 st Data Latched C D TRDY D1A D2A D3A D1B D2B D3B D4A D4B Final Data Latched _STBF LK AD AD_STBS hp compaq d330 and d530 Se...

Page 67: ...ND 53 PAD13 PAD14 10 ST1 ST0 32 AD_STB1 1 AD_STB 54 PAD11 PAD12 11 NC ST2 33 CBE3 PAD23 55 GND GND 12 PIPE RBF 34 VDDQ VDDQ 56 PAD09 PAD10 13 GND GND 35 PAD22 PAD21 57 CBE0 PAD08 14 WBF NC 36 PAD20 PAD19 58 VDDQ VDDQ 15 SBA1 SBA0 37 GND GND 59 AD_STB0 0 AD_STB 16 VDD3 VDD3 38 PAD18 PAD17 60 PAD06 PAD07 17 SBA3 SBA2 39 PAD16 CBE2 61 GND GND 18 SB_STB B SB_ST 40 VDDQ VDDQ 62 PAD04 PAD05 19 GND GND 4...

Page 68: ... attention of the microprocessor Peripheral functions produce a unique INTA H PCI or IRQ0 15 ISA signal that is routed to interrupt processing logic that asserts the interrupt INTR input to the microprocessor The microprocessor halts execution to determine the source f the interrupt and then services the peripheral as appropriate o Figure 4 10 shows the routing of PCI and ISA interrupts Most IRQs ...

Page 69: ...LABLE Cascade from interrupt controller 2 Int Cntlr APIC Mode The Advanced Programmable Interrupt Controller APIC mode provides enhanced interrupt rocessing with the following advantages p pt acknowledge cycle by using a separate APIC bus Eliminates the processor s interru Programmable interrupt priority Additional interrupts total of 24 The APIC mode accommodates eight PCI interrupt signals INTA ...

Page 70: ...alization and operation of the interrupt control registers follows standard AT type rotocol p 4 4 1 2 Non Maskable Interrupts Non maskable interrupts cannot be masked inhibited within the microprocessor itself but may be maskable by software using logic external to the microprocessor There are two non maskable interrupt signals the NMI and the SMI These signals have service priority over all maska...

Page 71: ...active NMI has been processed status bits 7 or 6 are cleared by pulsing bits 2 or 3 respectively The NMI Enable Register 070h 7 is used to enable disable the NMI signal Writing 80h to this register masks generation of the NMI Note that the lower six bits of register at I O port 70h affect RTC operation and should be considered when changing NMI generation status SMI Generation The SMI System Manag...

Page 72: ...D Controller 1 byte transfers 0 1 2 3 Spare m Audio subsyste Diskette drive Parallel port Con 4 troller 2 word transfers 5 6 7 Cascade for controller 1 Spare Spare Spare All channels in DMA controller 1 operate at a higher priority than those in controller 2 Note that channel 4 is not available for use other than its cascading function for controller 1 The DMA controller 2 can transfer words only ...

Page 73: ...ge register for the refresh channel must be programmed with 00h for proper operation The memory address is derived as follows 24 Bit Address Controller 1 Byte Transfers 8 Bit Page Register 8 Bit DMA Controller A23 A16 A15 A00 ntrolle 24 Bit Address Co r 2 Word Transfers Regist r er 8 Bit Page e 16 Bit DMA Controll 23 A17 A16 A01 A00 0 A Note that address line A16 from the DMA memory page register ...

Page 74: ...Table 4 10 DMA Controller Registers Table 4 10 DMA Controller Registers Register Controller 1 Controller 2 R W Status 008h 0D0h R Command 008h 0D0h W Mode 00Bh 0D6h W Write Single Mask Bit 00Ah 0D4h W Write All Mask Bits 00Fh 0DEh W Software DRQx Request 009h 0D2h W Base and Current Address Ch 0 000h 0C0h W Current Address Ch 0 000h 0C0h R Base and Current Word Count Ch 0 001h 0C2h W Current Word ...

Page 75: ...le 4 11 Clock Generation and Distribution Frequncy Source Destination 100 133 or 200 MHz CK Processor GMCH 100 133 or 200 MHz CK DIMM sockets 100 MHz CK ICH 66 MHz CK ICH GMCH 48 MHz CK ICH GMCH 33 MHz CK ICH PCI Slots 14 31818 MHz Crystal CK ICH Certain clock outputs are turned off during reduced power modes to conserve energy Clock output control is handled through the SMBus interface by BIOS hp...

Page 76: ...arm Day of Week Date of Month Month Year Register A Register B Register C Register D 82801 0Bh 0Dh 0Ch 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah FFh 80h 7Fh 0Dh 0Eh 00h CMOS Figure 4 11 Configuration Memory Map A lithium 3 VDC battery is used for maintaining the RTC and configuration memory while the system is powered down During system operation a wire Ored circuit allows the RTC and configurat...

Page 77: ...e 4 12 Configuration Memory CMOS Map Table 4 12 Configuration M CMO emory S Map Location tion Function Loca Function 00 0Dh Real time clock 24h System board ID 0Eh Diagnostic status 25h System architecture data 0Fh System reset code 26h Auxiliary peripheral configuration 10h Diskette drive type 27h Speed control external drive 11h Reserved 28h Expanded base mem size IRQ12 12h Hard drive type 29h M...

Page 78: ...tten will require that CMOS be cleared refer to section 4 6 SYSTEM MANAGEMENT This section describes functions havin o SECURITY FUNCTIONS These systems include various features that provide different levels of security Note that this subsection d Power On Password These systems include a power on password which may be enabled or disabled cleared through a jumper on the system board The jumper cont...

Page 79: ...ced until the system is powered up and the user completes the boot sequence successfully at which time the bit will be cleared Through Setup the user can set this function to be used by lert On LAN and or one of three levels of support for a cover removed condition A Level 0 Cover removal indication is essentially disabled at this level During POST status b cleared and no other action is taken by ...

Page 80: ...ble 4 13 are valid only for PS 2 type keyboards A USB keyboard will not provide LED status for the listed events although audible beep indications will occur Table 4 13 System Boot ROM Flash Status LED Indications Table 4 13 System Boot ROM Flash St Indic atus LED ations Event NUM Lock CA ck Scroll Lock Blinking LED Ps Lo LED LED System memory failure 1 Off Off Graphics controller failure 2 Off Bl...

Page 81: ...one S5 Soft off Off clear None Processor thermal shutdown Blinks red 2 times I Hz 1 None Processor not seated installed Blinks red 3 times I Hz 1 None Power supply failure Blinks red 4 times I Hz 1 None Memory error Blinks red 5 times I Hz 1 5 Video error Blinks red 6 times I Hz 1 6 PCA failure Blinks red 7 times I Hz 1 7 Invalid ROM checksum error Blinks red 8 times I Hz 1 8 1 Repeated after 2 se...

Page 82: ...n s Figure 4 12 shows the fan control circuitry for desktops and minitower units The RPM speed of all fans is the result of the temperature of the CPU as sensed by the Control ASIC and indicated to the Speed Control circuitry The fans are controlled by circuitry to run at the slowest quietest speed that will maintain proper cooling NOTE Units using chassis and CPU fans must have both fans connecte...

Page 83: ...ve only if standard I O space is enabled for primary drive 01F0 01F7h IDE Controller 1 active only if standard I O space is enabled for secondary drive 0278 027Fh Parallel Port LPT2 02E8 02EFh Serial Port COM4 02F8 02FFh Serial Port COM2 0370 0377h Diskette Drive Controller Secondary Address 0376h IDE Controller 2 active only if standard I O space is enabled for primary drive 0378 037Fh Parallel P...

Page 84: ...Serial I F UART 2 Port B 06h Reserved 07h Keyboard I F 08h Reserved 09h Reserved 0Ah Runtime Registers GPIO Config 0Bh SMBus Configuration 00h 20h Super I O ID Register SID 56h 21h Revision 22h Logical Device Power Control 00h 23h Logical Device Power Management 00h 24h PLL Oscillator Control 04h 25h Reserved 26h Configuration Address Low Byte 27h Configuration Address High Byte 28 2Fh Reserved NO...

Page 85: ...ternal to the LPC47B387 controls the lock bar mechanism I O security The parallel serial and diskette interfaces may be disabled individually by software and the LPC47B387 s disabling register locked If the disabling register is locked a system reset through a cold boot is required to gain access to the disabling Device Disable register Processor present speed detection One of the battery back gen...

Page 86: ...cy EIDE and the SATA interfaces Systems are shipped configured with EIDE drives but can be reconfigured with SATA devices 5 2 1 EIDE INTERFACES Two 40 pin IDE connectors one for each controller are included on the system board Each controller can be configured independently for the following modes of operation Programmed I O PIO mode CPU controls drive transactions through standard I O mapped regi...

Page 87: ...r Latency Timer 00h 4A 4Bh Sync DMA Timing 0000h 0Eh Header Type 00h 54h EIDE I O Config Register 00h NOTE 1 ICH5 244Bh ICH5 24CBh IDE Bus Master Control Registers The IDE interface can perform PCI bus master operations using the registers listed in Table 5 2 These registers occupy 16 bytes of variable I O space set by software and indicated by PCI configuration register 20h in the previous table ...

Page 88: ...4 29 DAK DMA Acknowledge 10 DD11 Data Bit 11 30 GND Ground 11 DD3 Data Bit 3 31 IRQn Interrupt Request 4 12 DD12 Data Bit 12 32 IO16 16 bit I O 13 DD2 Data Bit 2 33 DA1 Address 1 14 DD13 Data Bit 13 34 DSKPDIAG Pass Diagnostics 15 DD1 Data Bit 1 35 DA0 Address 0 16 DD14 Data Bit 14 36 DA2 Address 2 17 DD0 Data Bit 0 37 CS0 Chip Select 18 DD15 Data Bit 15 38 CS1 Chip Select 19 GND Ground 39 HDACTIV...

Page 89: ...ce with bus mastering capability The PCI configuration registers for the SATA controller function PCI device 31 function 2 are listed in Table 5 1 Table 5 4 IDE PCI Configuration Registers Table 5 4 SATA PCI Configuration Registers 82801 Device 31 Function 2 PCI Conf Addr Register Reset Value PCI Conf Addr Register Reset Value 00 01h Vender ID 8086h 0F 1Fh Reserved 0 s 02 03h Device ID 24D1h 10 17...

Page 90: ...Master IDE Status Primary 00h 04h 4 Bus Master IDE Descriptor Pointer Pri 0000 0000h 08h 1 Bus Master IDE Command Secondary 00h 0Ah 2 Bus Master IDE Status Secondary 00h 0Ch 4 Bus Master IDE Descriptor Pointer Sec 0000 0000h NOTE Unspecified gaps are reserved will return indeterminate data and should not be written to 5 2 2 2 SATA CONNECTOR The 7 pin SATA connector is shown in the figure below Pin...

Page 91: ...f several bytes written in series from the CPU to the data register 3F5h 375h The first byte identifies the command and the remaining bytes define the parameters of the command The Main Status register 3F4h 374h provides data flow control for the diskette drive controller and must be polled between each byte transfer during the Command phase The Execution phase starts as soon as the last byte of t...

Page 92: ...1 Write 07h to I O register 2Eh 2 Write 00h to I O register 2Fh this selects the diskette drive I F 3 Write 30h to I O register 2Eh 4 Write 01h to I O register 2Fh this activates the interface Writing AAh to 2Eh deactivates the configuration phase The diskette drive I F configuration registers are listed in the following table Table 5 7 Diskette Drive Controller Configuration Registers Table 5 7 D...

Page 93: ... W 3F3h 373h Tape Drive Register available for compatibility R W 3F4h 374h Main Status Register MSR 7 Request for master host can transfer data active high 6 Transfer direction 0 write 1 read 5 non DMA execution active high 4 Command busy active high 3 2 Reserved 1 0 Drive 1 2 busy active high Data Rate Select Register DRSR 7 Software reset active high 6 Low power mode enable active high 5 Reserve...

Page 94: ...TEP Drive head track step cntrl 4 MEDIA ID Media identification 21 GND Ground 5 GND Ground 22 WR DATA Write data 6 DRV 4 SEL Drive 4 select 23 GND Ground 7 GND Ground 24 WR ENABLE Enable for WR DATA 8 INDEX Media index is detected 25 GND Ground 9 GND Ground 26 TRK 00 Heads at track 00 indicator 10 MTR 1 ON Activates drive motor 27 GND Ground 11 GND Ground 28 WR PRTK Media write protect status 12 D...

Page 95: ...st be set during the configuration phase 5 4 1 SERIAL CONNECTOR The serial interface uses a DB 9 connector as shown in the following figure with the pinout listed in Table 5 10 Figure 5 4 Serial Interface Connector Male DB 9 as viewed from rear of chassis Table 5 10 DB 9 Serial Connector Pinout Table 5 10 DB 9 Serial Connector Pinout Pin Signal Description Pin Signal Description 1 CD Carrier Detec...

Page 96: ...terface are affected through the PnP configuration registers of the LPC47B387 I O controller The serial interface configuration registers are listed in the following table Table 5 11 Serial Interface Configuration Registers Table 5 11 Serial Interface Configuration Registers Index Address Function R W 30h Activate R W 60h Base Address MSB R W 61h Base Address LSB R W 70h Interrupt Select R W F0h M...

Page 97: ...Addr Register R W 3F8h 2F8h Receive Data Buffer Transmit Data Buffer Baud Rate Divisor Register 0 when bit 7 of Line Control Reg Is set R W W 3F9h 2F9h Baud Rate Divisor Register 1 when bit 7 of Line Control Reg Is set Interrupt Enable Register W R W 3FAh 2FAh Interrupt ID Register FIFO Control Register R W 3FBh 2FBh Line Control Register R W 3FCh 2FCh Modem Control Register R W 3FDh 2FDh Line Sta...

Page 98: ...ad of the parallel port yields the last data byte that was written The following steps define the standard procedure for communicating with a printing device 1 The system checks the Printer Status register If the Busy Paper Out or Printer Fault signals are indicated as being active the system either waits for a status change or generates an error message 2 The system sends a byte of data to the Pr...

Page 99: ...ration of addresses and strobes as well as Run Length Encoding RLE decompression is supported by ECP mode The ECP mode includes a bi directional FIFO buffer that can be accessed by the CPU using DMA or programmed I O For the parallel interface to be initialized for ECP mode a negotiation phase is entered to detect whether or not the connected peripheral is compatible with ECP mode If compatible th...

Page 100: ...ough the PnP configuration registers of the LPC47B387 I O controller Address selection and enabling are automatically done by the BIOS during POST but can also be accomplished with the Setup utility and other software The parallel interface configuration registers are listed in the following table Table 5 13 Parallel Interface Configuration Registers Table 5 13 Parallel Interface Configuration Reg...

Page 101: ...able 5 14 Parallel Interface Control Registers I O Address Register SPP Mode Ports EPP Mode Ports ECP Mode Ports Base Data LPT1 2 3 LPT1 2 LPT1 2 3 Base 1h Printer Status LPT1 2 3 LPT1 2 LPT1 2 3 Base 2h Control LPT1 2 3 LPT1 2 LPT1 2 3 Base 3h Address LPT1 2 Base 4h Data Port 0 LPT1 2 Base 5h Data Port 1 LPT1 2 Base 6h Data Port 2 LPT1 2 Base 7h Data Port 3 LPT1 2 Base 400h Parallel Data FIFO LPT...

Page 102: ...16 INIT Initialize Paper 4 4 D2 Data 2 17 SLCTIN Select In Address Strobe 1 5 D3 Data 3 18 GND Ground 6 D4 Data 4 19 GND Ground 7 D5 Data 5 20 GND Ground 8 D6 Data 6 21 GND Ground 9 D7 Data 7 22 GND Ground 10 ACK Acknowledge Interrupt 1 23 GND Ground 11 BSY Busy Wait 1 24 GND Ground 12 PE Paper End User defined 1 25 GND Ground 13 SLCT Select User defined 1 NOTES 1 Standard and ECP mode function EP...

Page 103: ... of the CPU The 8042 can send a command to the keyboard at any time When the 8042 wants to send a command the 8042 clamps the clock signal from the keyboard for a minimum of 60 us If the keyboard is transmitting data at that time the transmission is allowed to finish When the 8042 is ready to transmit to the keyboard the 8042 pulls the data line low causing the keyboard to respond by pulling the c...

Page 104: ...te Display F3h Instructs the keyboard to change typematic rate and delay to specified values Bit 7 Reserved 0 Bits 6 5 Delay Time 00 250 ms 01 500 ms 10 750 ms 11 1000 ms Bits 4 0 Transmission Rate 00000 30 0 ms 00001 26 6 ms 00010 24 0 ms 00011 21 8 ms 11111 2 0 ms Enable F4h Instructs keyboard to clear output buffer and last typematic key and begin key scanning Default Disable F5h Resets keyboar...

Page 105: ...interface must be enabled and configured for a particular speed before it can be used Enabling and speed parameters of the 8042 logic are affected through the PnP configuration registers of the LPC47B387 I O controller Enabling and speed control are automatically set by the BIOS during POST but can also be accomplished with the Setup utility and other software The keyboard interface configuration ...

Page 106: ...2 and to receive responses from the 8042 for commands that require a response A read of 60h by the CPU yields the byte held in the output buffer The output buffer holds data that has been received from the keyboard and is to be transferred to the system A CPU write to 60h places a data byte in the input byte buffer and sets the CMD DATA bit of the Status register to DATA The input buffer is used f...

Page 107: ...ock line stuck high 03h Data line stuck low 04h Data line stuck high ADh Disable keyboard command sets bit 4 of the 8042 command byte AEh Enable keyboard command clears bit 4 of the 8042 command byte C0h Read input port of the 8042 This command directs the 8042 to transfer the contents of the input port to the output buffer so that they can be read at port 60h C2h Poll Input Port High This command...

Page 108: ...keyboard pointing device interface connectors Figure 5 7 Keyboard or Pointing Device Interface Connector as viewed from rear of chassis Table 5 19 Keyboard Pointing Device Connector Pinout Table 5 19 Keyboard Pointing Device Connector Pinout Pin Signal Description Pin Signal Description 1 DATA Data 4 5 VDC Power 2 NC Not Connected 5 CLK Clock 3 GND Ground 6 NC Not Connected hp compaq d330 and d530...

Page 109: ... configured to either a USB 1 1 controller or the USB 2 0 controller depending on the capability of the peripheral device The 1 1 controllers provide a maximum transfer rate of 12 Mb s while the 2 0 controller provides a maximum transfer rate of 480 Mb s NOTE Not used in these systems 2 0 7 2 0 6 1 1 7 1 1 6 2 0 4 2 0 2 2 0 3 2 0 0 2 0 1 2 0 5 1 1 5 1 1 4 1 1 3 1 1 2 1 1 1 1 1 0 Tx Rx Data 7 NC Tx...

Page 110: ...of error correction to be applied Address Field 7 bit field that provides source information required in token packets Endpoint Field 4 bit field that provides destination information required in token packets Frame Field 11 bit field sent in Start of Frame SOF packets that are incremented by the host and sent only at the start of each frame Data Field 0 1023 byte field of data Cyclic Redundancy C...

Page 111: ...06 07h PCI Status 0280h 3Ch Interrupt Line 00h 08h Revision ID 00h 3Dh Interrupt Pin 03h 09h Programming I F 00h 60h Serial Bus Release No 10h 0Ah Sub Class Code 03h C0 C1h USB Leg Kybd Ms Cntrl 2000h 0Bh Base Class Code 0Ch C4h USB Resume Enable 00h NOTE 1 USB 1 1 1 24D2h USB 1 1 2 24D4h USB 1 1 3 24D7h USB 2 0 24DDh 5 7 2 2 USB Control The USB is controlled through I O registers as listed in tab...

Page 112: ...ing table Table 5 23 USB Cable Length Data Table 5 23 USB Cable Length Data Conductor Size Resistance Maximum Length 20 AWG 0 036 Ω 16 4 ft 5 00 m 22 AWG 0 057 Ω 9 94 ft 3 03 m 24 AWG 0 091 Ω 6 82 ft 2 08 m 26 AWG 0 145 Ω 4 30 ft 1 31 m 28 AWG 0 232 Ω 2 66 ft 0 81 m NOTE For sub channel 1 5 MB s operation and or when using sub standard cable shorter lengths may be allowable and or necessary The sh...

Page 113: ...sed by the codec to silence the internal speaker The analog interfaces allowing connection to external audio devices include Mic In This input uses a three conductor stereo mini jack that is specifically designed for connection of a condenser microphone with an impedance of 10 K ohms This is the default recording input after a system reset On systems with both a front and rear microphone jack eith...

Page 114: ...no Audio Internal Speaker Audio Bias Mic In Line In L R Audio Codec HP Out Audio L R L R TDA 7056 Headphones Line Out NOTE 1 Not available on USDT form factors 2 On USDT multibay connector On all other form factors P7 header Figure 5 11 Audio Subsystem Functional Block Diagram hp compaq d330 and d530 Series of Personal Computers Featuring the Intel Pentium 4 Processor First Edition June 2003 5 29 ...

Page 115: ... and driven by the audio controller The SYNC signal is high during the frame s tag phase then falls during T17 and remains low during the data phase A frame consists of one 16 bit tag slot followed by twelve 20 bit data slots When asserted typically during a power cycle the RESET signal not shown will reset all audio registers to their default values BIT_CLK 12 288 MHz Slot Description 0 Bit 15 Fr...

Page 116: ... audio The Sample Rate Generator may be set for sampling frequencies up to 48 KHz The integrated analog mixer provides the computer control console functionality handling multiple audio inputs Audio Format HP Out R HP Out L SPDIF EQ EQ ADC PB Data R PB Data L DAC DAC Rec Data R ADC Rec Data L S E L R L R L PB Gain PB Gain Rec Gain Rec Gain Σ Mixer CD In R CD In L Line In R Line In L Mic In S e l e...

Page 117: ...io subsystem is controlled through a set of indexed registers that physically reside in the audio codec The register addresses are decoded by the audio controller and forwarded to the audio codec over the AC97 Link Bus previously described The audio codec s control registers Table 5 25 are mapped into 64 kilobytes of variable I O space Table 5 25 AC 97 Audio Codec Control Registers Table 5 25 AC 9...

Page 118: ...Out 1 K ohms nom 10 K ohms min 800 ohms Signal to Noise Ratio input to Line Out 90 db nom Frequency Response 3db to Line Output Line Input Mic Input A D PC record Line input Mic input D A PC playback 20 Hz 20 KHz 100 Hz 12 KHz 20 Hz 19 2 KHz 100 Hz 8 8 Khz 20 Hz 19 2 KHz Max Power Output with 10 THD Small Form Factor Slim Desktop Configurable Minitower 8 watts into 8 ohms 3 watts into 16 ohms Inpu...

Page 119: ...cates network activity and link pulse reception Yellow Speed Indicates link detection in 100 MB s mode always on if 100Base Tx is forced Figure 5 14 Network Interface Controller Block Diagram The Network Interface Controller includes the following features Dual high speed RISC controllers with 16 KB caches Triple mode support with auto switching between 10BASE T 100BASE TX and 1000BASE T Power man...

Page 120: ...n order to process special packets The detection of a Magic Packet by the NIC results in the PME signal on the PCI bus to be asserted initiating system wake up from an ACPI S1 or S3 state 5 9 2 ALERT STANDARD FORMAT SUPPORT Alert Standard Format ASF support allows the NIC to communicate the occurrence of certain events over a network to an ASF 1 0 compliant management console and if necessary take...

Page 121: ... supported in NDIS5 drivers but implemented through remote management software applications such as LanDesk Individual address match Packet with matching user defined byte mask Multicast address match Packet with matching user defined sample frame ARP address resolution protocol packet Flexible packet filtering Packets that match defined CRC signature The PROSet Application software pre installed ...

Page 122: ...ll duplex 20 Mb s 100BASE TX half duplex 100 Mb s 100Base TX full duplex 200 Mb s 1000BASE T half duplex 1 Gb s 1000BASE TX full duplex 2 Gb s Standards Compliance IEEE 802 2 IEEE 802 3 802 3x IEEE Intel priority packet 801 1p OS Driver Support MS DOS MS Windows 3 1 MS Windows 95 pre OSR2 98 and 2000 Professional XP Home XP Pro MS Windows NT 3 51 4 0 Novell Netware 3 x 4 x 5x Novell Netware IntraN...

Page 123: ...Chapter 5 Input Output Interfaces 5 38 hp compaq d330 and d530 Series of Personal Computers Featuring the Intel Pentium 4 Processor First Edition June 2003 This page is intentionally blank ...

Page 124: ...ntegrated graphics by installing a separate AGP or PCI graphics card The system will detect an installed graphics controller card during the boot sequence and disable the integrated graphics controller of the 82865G GMCH NOTE Separate AGP graphics cards that are included in the standard system configurations of some models are described in the appendices of this guide This chapter covers the follo...

Page 125: ...scribed in Chapter 3 Hub Link I F FSB I F SDRAM Controller Integrated Graphics Controller Monitor 82865G GMCH Figure 6 1 865G Based Graphics Block diagram The Integrated Graphics Controller includes the following features Rapid pixel and texel rendering using special pipelines that allow 2D and 3D operations to overlap speeding up visual effects reducing the amount of memory for texture storage Zo...

Page 126: ... Digital Video B Digital Video C DVOC DVOB DDR SDRAM System Memory AGP Slot 1 VSync HSync SDRAM Memory Controller RAM DAC Pipelined Preprocessor RGB Monitor Connector 2D Engine 3D Engine 82865G GMCH Integrated Graphics Controller Figure 6 2 82865G GMCH Integrated Graphics Controller Special features of the integrated graphics controller include 200 MHz core engine 350 MHz 24 bit RAMDAC 2D engine s...

Page 127: ... during the boot process the maximum graphics memory allocation possible according on the amount of system memory installed SDRAM Installed Maximum Memory Allocation 256 megabytes 32 MB 256 megabytes 48 MB The actual amount of system memory used by the IGC in the extended or extreme modes will increase and decrease dynamically according to the needs of the graphics application The amount of memory...

Page 128: ... 7M 85 1900 x 1440 1 3 8 256 75 1900 x 1440 1 3 16 65K 75 1920 x 1080 1 3 4 8 256 85 1920 x 1080 1 3 4 16 65K 85 2048 x 1536 1 3 8 256 85 2048 x 1536 1 3 16 65K 60 2048 x 1536 1 3 32 16 7M 60 NOTES 1 2D 2 3D 3 Analog monitor only 4 dCRT or HDTV only NOTE The IGC is designed for optimum performance with multi sync analog Monitors Digital displays may not provide an image as high in quality dependin...

Page 129: ... 0000h E2 FFh Reserved NOTE Assume unmarked locations gaps as reserved Refer to Intel documentation for detailed register descriptions The graphics controller is controlled through memory mapped registers by the appropriate software driver 6 5 UPGRADING THE GRAPHICS SUBSYTEM All models except those that use the USDT form factor are upgradeable by installing an AGP graphics card into the AGP slot T...

Page 130: ...ription Pin Signal Description 1 R Red Analog 9 PWR 5 VDC fused 1 2 G Blue Analog 10 GND Ground 3 B Green Analog 11 NC Not Connected 4 NC Not Connected 12 SDA DDC2 B Data 5 GND Ground 13 HSync Horizontal Sync 6 R GND Red Analog Ground 14 VSync Vertical Sync 7 G GND Blue Analog Ground 15 SCL DDC2 B Clock 8 B GND Green Analog Ground NOTES 1 Fuse automatically resets when excessive load is removed hp...

Page 131: ...Chapter 6 Integrated Graphics Subsystem hp compaq d330 and d530 Series of Personal Computers Featuring the Intel Pentium 4 Processor First Edition June 2003 6 8 This page is intentionally blank ...

Page 132: ... 10 7 2 POWER SUPPLY ASSEMBLY CONTROL This system features a power supply assembly that is controlled through programmable logic Figure 7 1 P Assembly 5 VDC 12 VDC CPU Slots Chipsets Logic AUX 2 System Board Front Bezel 1 1 12 8 Vcpu 10 220 Select Switch 2 12 VDC 5 VDC Fan Spd Mains Power On Power On Off 3 3 PS On Voltage Regulators 5 AUX 110 230 VAC 12 VDC 5 VDC ower Supply Drives igure 7 1 Power...

Page 133: ... 10 seconds with 12 volt tolerance 10 be the same as the 12 VDC output Tolerance and max ripple specifications apply to both outputs 1 Minimum loading requirements must be met at all times to ensure normal o and specification compliance 2 Surge duration no long 3 The 12 8 VDC may Table 7 2 250 Watt Power Supply Assembly Specifications Table 7 2 185 Watt SFF r S b fic ST Powe u m pply Asse ly Speci...

Page 134: ...typically controlled through the Power Button which when pressed and released applies a negative grounding pulse to the power control logic The resultant action of pressing the power button depends on the state and mode of the system at that time and is described as follows System State Pressed Power Button Results In Off Negative pulse of which the falling edge results in power control logic asse...

Page 135: ... Pre video memory error Incompatible or incorrectly seated DIMM Blinks red 6 times 1 Hz followed by 2 second pause 1 Pre video graphics error On system with integrated graphics check replace system board On system with AGP graphics card check replace graphics card Blinks red 7 times 1 Hz followed by 2 second pause 1 PCA failure Check replace system board Blinks red 8 times 1 Hz followed by 2 secon...

Page 136: ...ality The wake up sequence for each event occurs as follows Wake On LAN The network interface controller NIC can be configured for detection of a Magic Packet and wake the system up from sleep mode through the assertion of the PME signal on the PCI bus Refer to Chapter 5 Network Support for more information Modem Ring A ring condition on a serial port can be detected by the power control logic and...

Page 137: ...r is blanked Low 2 sec after keyboard or pointing device action No G1 S2 3 C2 D2 Standby suspend System on CPU not executing cache data lost Memory is holding data display and I O subsystems on low power Low 5 sec after keyboard pointing device or power button action No G1 S4 D3 Hibernation System off CPU memory and most subsystems shut down Memory image saved to disk for recall on power up Low 25...

Page 138: ...1 2 3 4 P1 1 2 5 4 3 6 9 10 7 8 1 2 4 3 8 7 6 P3 5 To System Board Conn Pin 3 Pin 4 Pin 10 Pin 1 Pin 2 Pin 5 Pin 6 Pin 7 Pin 8 Pin 9 P1 GND NC NC NC 3 3 GND PS On 5 Aux 12 12 P2 12 GND GND 5 12 GND GND 5 NC NC P3 12 GND GND 5 P4 JMPR JMPR FS FC P5 3 3 5 GND 12 GND NOTES e round sense ed 1 This row represents pins 13 24 of connector P1 igure 7 2 USDT Power Cable Diagram Connectors not shown to scal...

Page 139: ...C ground sense POK Power OK power good 1 This row represents pins 8 14 of connector P1 Figure 7 3 SFF Power Cable Diagram Connectors not shown to scale All and values are V RTN Return signal GND Power ground RS Remote FC Fan command FO Fan off FSpd Fan speed FS Fan Sink P2 4 3 2 1 To Drive Assemblies P1 System Board P8 P4 P3 P6 P9 P2 P5 P7 To P3 P5 5 4 3 2 1 1 2 3 4 P4 P7 P8 P6 4 3 2 1 Pow Assembl...

Page 140: ...9 P1 3 3 3 3 RTN 5 RTN 5 RTN POK 5 Aux 12 P1 1 PS On RTN RTN RTN Open 5 5 3 3 12 RTN P3 GND GND 12 12 P7 8 5 GND GND 12 P4 1 5 1 GND 12 3 3 GND 5 P2 4 6 12 GND GND 5 10 P9 GND FC NOTES le round er good Not connected in these systems Sink and command functions are handled on system board igure 7 4 DT MT and CMT Power Cable Diagram Connectors not shown to sca All and values are VDC RTN Return signal...

Page 141: ...s VID4 0 by the processor The possible voltages available are listed as follows F The VccP regulator produces the VccP processor core voltage according to the strappi si VID 4 0 VccP VID 4 0 VccP VID 4 0 VccP 00000 2 05 VDC 01011 1 50 VDC 10110 2 90 VDC 00001 2 00 VDC 01100 1 45 VDC 10111 2 80 VDC 00010 1 95 VDC 01101 1 40 VDC 11000 2 70 VDC 00011 1 90 VDC 01110 1 35 VDC 11001 2 60 VDC 00100 1 85 ...

Page 142: ...n IDE Data Cntl IDE Hard Drive 5 12 VDC CD Audio Daughter Board Multibay IDE I F Diskette I F 3 5 12 VDC 3 5AUX Power Supply Assembly Conn P1 Pri IDE Conn P20 5 12 VDC Multibay Conn P21 USB Port USB Port Conn P23 Mouse CD ROM Front Panel I O Module USB 4 5 I F Mic In HP Out Audio Keyboard Conn P24 OTES N 1 See Figure 7 7 for header pinout Figure 7 6 USDT Form Factor Signal Distribution Diagram hp ...

Page 143: ... CD ROM IDE I F Sec IDE Conn P21 5 12 VDC L R Audio Audio Conn P7 Dskt Data Cntl Diskette Drive 5 12 VDC Dsk Conn P10 Mouse Kybd Conn J68 Mouse Keyboard Headphones Out Front Panel I O Board Assembly Audio Conn P23 Microphone In USB Data PCI Slot Exp Edge Connector USB Conn Conn P24 PCI Bus PCI Slot Exp Card OTES N SFF form factor only CMT form factor only 1 Header pinout shown in Figure 7 7 2 Sens...

Page 144: ... Ground 7 Not Connected 3 2 Not Connected 6 Thermal 4 Not Connected AOL SOS Header P12 Chassis ID2 15 GND 13 NC 11 5 VDC 9 M Reset 7 GND 5 HD LED Anode 3 18 Chassis ID1 Chassis ID0 17 HD LED Cathode 1 16 5 VDC 12 GND 10 NC 8 GND 6 PWR Btn 4 PS LED anode 2 PS LED cathode NOTE No polarity consideration required for connection to speaker header P6 or SCSI HD LED heade 1 Separate cable connection for ...

Page 145: ...ed for Management WfM ver 2 2 Alert On LAN AOL and Wake On LAN WOL ACPI and OnNow SMBIOS 2 3 1 PC98 99 00 and NetPC Intel PXE boot ROM for the integrated LAN controller BIOS Boot Specification 1 01 Enhanced Disk Drive Specification 3 0 El Torito Bootable CD ROM Format Specification 1 0 ATAPI Removeable Media Device BIOS Specification 1 0 The BIOS ROM is a 512KB Intel Firmware Hub or Firmware Hub c...

Page 146: ... check the boot block code provides the minimum amount of support necessary to allow booting the system from the diskette drive and re flashing the system ROM with a ROMPAQ diskette Note that if an administrator password has been set in the system the boot block will prompt for this password by illuminating the caps lock keyboard LED and displaying a message if video support is available A PS 2 ke...

Page 147: ...ge searching and pre viewing Background and foreground colors can be chosen from the selected image s palette The splash screen image requirements are as follows Format Windows bitmap with 4 bit RLE encoding Size 424 width x 320 height pixels Colors 16 4 bits per pixel File Size 64 KB The Image Flash utility can be invoked at a command line for quickly flashing a known image as follows Flashi exe ...

Page 148: ...ayed even if no USB storage devices are present The hot IPL option is available through the F9 utility which allows the user to select a hot IPL boot device 8 3 2 NETWORK BOOT F12 SUPPORT The BIOS supports booting the system to a network server The function is accessed by pressing the F12 key when prompted at the lower right hand corner of the display during POST Booting to a network server allows...

Page 149: ...liant DIMMS will be indicated by BIOS reading 75h from byte 9 and 64h or 85h from byte 126 For PC133 operation to occur the FSB of the processor must be running at 133 MHz and all installed DIMMs must be PC133 compliant and total no more than four sides Refer to Chapter 3 for more details on PC133 operation 8 3 4 BOOT ERROR CODES The BIOS provides visual and audible indications of a failed system ...

Page 150: ...e Restore from Diskette Restores system configuration including CMOS from a diskette Set Defaults and Exit Restores factory default settings which includes clearing any established passwords Ignore Changes and Exit Exits Computer Setup without applying or saving any changes Save Changes and Exit Saves changes to system configuration and exits Computer Setup Storage Device Configuration Lists all i...

Page 151: ... sector PIO operation Options subject to device capabilities are Disabled 8 and 16 Quiet Drive available on select drives only Performance Allows the drive to operate at maximum performance Quiet will not be displayed if not supported by drive Reduces noise from the drive during operation When set to Quiet the drive will not operate at maximum performance Storage Options Removable Media Boot Enabl...

Page 152: ...C if any devices are attached NOTE This election will not appear if all hard drives are attached to the embedded IDE controllers Security Setup Password Allows user to set and enable setup administrator password Note If the setup password is set it is required to change Computer Setup options flash the ROM and make changes to certain plug and play settings under Windows Also this password must be ...

Page 153: ... MBR Security is enabled Restore Master Boot Record Restores the backup Master Boot Record to the current bootable disk Note Only appears if all of the following conditions are true MBR Security is enabled A backup copy of the MBR has been previously saved The current bootable disk is the same disk from which the backup copy of the MBR was saved Device Security Enables disables serial parallel and...

Page 154: ...e energy saver mode is disabled Advanced Advanced users only Power On Options Allows user to set POST mode QuickBoot FullBoot or FullBoot every 1 30 days POST messages enable disable Safe POST enable disable F10 prompt enable disable F12 prompt enable disable Option ROM prompt enable disable Remote wakeup boot sequence remote server local hard drive After power loss off on If you connect your comp...

Page 155: ...r on off on PME power management event wakeup events enable disable Processor cache enable disable Processor Number enable disable for Pentium III processors ACPI S3 support enable disable S3 is an ACPI advanced configuration and power interface sleep state that some add in hardware options may not support AGP Aperture size options vary depending on platform allows you to modify the size of your A...

Page 156: ...Real E81Eh Get hard drive ID Real E827h DIMM EEPROM Access Real 16 32 bit Prot NOTE 1 Industry standard function All 32 bit protected mode functions are accessed by using the industry standard BIOS32 Service Directory Using the service directory involves three steps 1 Locating the service directory 2 Using the service directory to obtain the entry point for the client management functions 3 Callin...

Page 157: ...encompass the physical page holding entry point as well as the immediately following physical page It must have the same base CS is execute read DS Data selector set to encompass the physical page holding entry point as well as the immediately following physical page It must have the same base DS is read only SS Stack selector must provide at least 1K of stack space and be 32 bit I O permissions m...

Page 158: ...lay identification data EDID Two subfunctions are provided AX E813h BH 00h retrieves the EDID information while AX E813h BX 01h determines the level of DDC support Input AX E813h BH 00 Get EDID BH 01 Get DDC support level If BH 00 then DS E SI Pointer to a buffer 128 bytes where ROM will return block If 32 bit protected mode then DS E SI Pointer to DDC location Output Successful If BH 0 DS SI Buff...

Page 159: ... message 50h Get SMBIOS Structure Information 51h Get Specific SMBIOS Structure The BIOS call INT 15 AX E841h BH 01h can be used by an application to retrieve the default settings of PnP devices for the user The application should use the following steps for the display function 1 Call PnP function 01 get System Device Node for each devnode with bit 1 of the control flag set get static configurati...

Page 160: ...rmation 16 Physical Memory Array 17 Memory Devices 19 Memory Array Mapped Addresses 20 Memory Device Mapped Addresses 31 Boot Integrity Service Entry Point 32 System Boot Information 128 OEM Defined Structure with Intel Alert On LAN AOL Information NOTE System information on these systems is handled exclusively through the SMBIOS The System Information Table SIT method and it s associated BIOS fun...

Page 161: ...ts the time out minute countdown The system timer can be configured through the Setup utility for counting down 0 5 10 15 20 30 40 50 60 120 180 or 240 minutes The following devices are checked for activity Keyboard Mouse Serial port s Parallel port IDE primary controller NOTE The secondary controller is NOT included This is done to support auto sense of a CD ROM insertion auto run in case Windows...

Page 162: ... mode 8 7 1 4 System OFF When the system is turned Off but still plugged into a live AC outlet the NIC ICH2 and I O components continue to receive auxiliary power in order to power up as the result of a Magic Packet being received over a network Some NICs are able to wake up a system from Standby in PM most require their Windows NT driver to reset them after one wake up 8 7 1 5 Waking Up in Indepe...

Page 163: ...SB keyboard This allows a system with only a USB keyboard to be used during ROM based setup and also on a system with an OS that does not include a USB driver On such a system a keystroke will generate an SMI and the SMI handler will retrieve the data from the device and convert it to PS 2 data The data will be passed to the keyboard controller and processed as in the PS 2 interface Changing the d...

Page 164: ...Chapter 8 BIOS ROM hp compaq d330 and d530 Series of Personal Computers Featuring the Intel Pentium 4 Processor First Edition June 2003 8 20 This page is intentionally blank ...

Page 165: ...Chapter 8 for beep LED indications on HP branded models Table A 1 Beep Keyboard LED Codes Table A 1 Beep Keyboard LED Codes Beeps LED 1 Probable Cause 1 short 2 long NUM lock blinking Base memory failure 1 long 2 short CAP lock blinking Video graphics controller failure 2 long 1 short Scroll lock blinking System failure prior to video initialization 1 long 3 short None Boot block executing None Al...

Page 166: ...ad Device ID of embedded NIC 510 Splash Image Corrupt Corrupted splash screen image Restore default image w ROMPAQ 511 CPU Fan Not Detected Processor heat sink fan is not connected 512 Chassis Fan Not Detected Chassis fan is not connected 601 Diskette Controller Error Diskette drive removed since previous boot 912 Computer Cover Removed Since Last System Start Up Cover hood removal has been detect...

Page 167: ...able to enter Auto mode in speed test 105 07 Port 61 bit 3 not at one 112 09 Unable to enter High mode in speed test 105 08 Port 61 bit 1 not at one 112 10 Speed test High mode out of range 105 09 Port 61 bit 0 not at one 112 11 Speed test Auto mode out of range 105 10 Port 61 I O test failed 112 12 Speed test variable speed mode inop 105 11 Port 61 bit 7 not at zero 113 01 Protected mode test fai...

Page 168: ...ing increment pattern test 211 01 Memory random pattern test 211 02 Error while saving memory during random memory pattern test 211 03 Error while restoring memory during random memory pattern test 213 xx Incompatible DIMM in slot x 214 xx Noise test failed 215 xx Random address test A 6 KEYBOARD ERROR MESSAGES 30x xx Table A 5 Keyboard Error Messages Table A 5 Keyboard Error Messages Message Prob...

Page 169: ...3 xx Printer pattern test failed 402 08 Interrupt test failed 404 xx Parallel port address conflict 402 09 Interrupt test and data reg failed 498 00 Printer failed or not connected 402 10 Interrupt test and control reg failed A 8 VIDEO GRAPHICS ERROR MESSAGES 5xx xx Table A 7 Video Graphics Error Messages Table A 7 Video Graphics Error Messages Message Probable Cause Message Probable Cause 501 01 ...

Page 170: ...diskette drive port addr conflict 604 xx Diskette drive random seek test 694 00 Pin 34 not cut on 360 KB drive 605 xx Diskette drive ID media 697 00 Diskette type error 606 xx Diskette drive speed test 698 00 Drive speed not within limits 607 xx Diskette drive wrap test 699 00 Drive media ID error run Setup 608 xx Diskette drive write protect test A 10 SERIAL INTERFACE ERROR MESSAGES 11xx xx Table...

Page 171: ...long 1201 17 Tone detect failure 1205 08 Modem time out waiting for remote response 1202 XX Modem internal test 1205 09 Modem exceeded maximum redial limit 1202 01 Time out waiting for SYNC 1 1205 10 Line quality prevented remote response 1202 02 Time out waiting for response 1 1205 11 Modem time out waiting for remote connection 1202 03 Data block retry limit reached 1 1206 XX Dial multi frequenc...

Page 172: ...66 Failed to initialize drive parameter 17xx 43 Failed to format a bad track 17xx 67 Failed to write long 17xx 44 Failed controller diagnostics 17xx 68 Failed to read long 17xx 45 Failed to get drive parameters from ROM 17xx 69 Failed to read drive size 17xx 46 Invalid drive parameters from ROM 17xx 70 Failed translate mode 17xx 47 Failed to park heads 17xx 71 Failed non translate mode 17xx 48 Fai...

Page 173: ...ad test failed 1902 xx Tape format failed 1906 xx Tape R W compare test failed 1903 xx Tape drive sensor test failed 1907 xx Tape write protect failed A 15 VIDEO GRAPHICS ERROR MESSAGES 24xx xx Table A 14 Video Graphics Error Messages Table A 14 Video Graphics Error Messages Message Probable Cause Message Probable Cause 2402 01 Video memory test failed 2418 02 EGA shadow RAM test failed 2403 01 Vi...

Page 174: ...es A 18 NETWORK INTERFACE ERROR MESSAGES 60xx xx Table A 17 Network Interface Error Messages Table A 17 Network Interface Error Messages Message Probable Cause Message Probable Cause 6000 xx Pointing device interface error 6054 xx Token ring configuration test failed 6014 xx Ethernet configuration test failed 6056 xx Token ring reset test failed 6016 xx Ethernet reset test failed 6068 xx Token rin...

Page 175: ...o data detected 6nyy 60 Controller CONFIG 1 register fault 6nyy 21 Drive command aborted 6nyy 61 Controller CONFIG 2 register fault 6nyy 24 Media hard error 6nyy 65 Media not unloaded 6nyy 25 Reserved 6nyy 90 Fan failure 6nyy 30 Controller timed out 6nyy 91 Over temperature condition 6nyy 31 Unrecoverable error 6nyy 92 Side panel not installed 6nyy 32 Controller drive not connected 6nyy 99 Autoloa...

Page 176: ...Appendix A Error Messages and Codes hp Compaq Personal Computers Changed April 2003 A 12 This page is intentionally blank ...

Page 177: ...Symbol 0 00 Blank 32 20 Space 64 40 96 60 1 01 33 21 65 41 A 97 61 a 2 02 34 22 66 42 B 98 62 b 3 03 35 23 67 43 C 99 63 c 4 04 36 24 68 44 D 100 64 d 5 05 37 25 69 45 E 101 65 e 6 06 38 26 70 46 F 102 66 f 7 07 39 27 71 47 G 103 67 g 8 08 40 28 72 48 H 104 68 h 9 09 41 29 73 49 I 105 69 I 10 0A 42 2A 74 4A J 106 6A j 11 0B 43 2B 75 4B K 107 6B k 12 0C 44 2C 76 4C L 108 6C l 13 0D 45 2D 77 4D M 10...

Page 178: ...6 151 97 ù 183 B7 215 D7 247 F7 152 98 ÿ 184 B8 216 D8 248 F8 153 99 Ö 185 B9 217 D9 249 F9 154 9A Ü 186 BA 218 DA 250 FA 155 9B 187 BB 219 DB 251 FB 156 9C 188 BC 220 DC 252 FC ⁿ 157 9D 189 BD 221 DD 253 FD 158 9E 190 BE 222 DE 254 FE 159 9F ƒ 191 BF 223 DF 255 FF Blank NOTES 1 Symbol not displayed Keystroke Guide Dec Keystroke s 0 Ctrl 2 1 26 Ctrl A thru Z respectively 27 Ctrl 28 Ctrl 29 Ctrl 30...

Page 179: ...Standard enhanced keyboard Space Saver Windows version keyboard featuring additional keys for specific support of the Windows operating system Easy Access keyboard with additional buttons for internet accessibility functions Only one type of keyboard is supplied with each system Other types may be available as an option NOTE This appendix discusses only the keyboard unit The keyboard interface is ...

Page 180: ...When the system is turned on the keyboard processor generates a Power On Reset POR signal after a period of 150 ms to 2 seconds The keyboard undergoes a Basic Assurance Test BAT that checks for shorted keys and basic operation of the keyboard processor The BAT takes from 300 to 500 ms to complete If the keyboard fails the BAT an error code is sent to the CPU and the keyboard is disabled until an i...

Page 181: ...the clock signal low The keyboard checks the clock line every 60 µs to verify the state of the signal If a low is detected the keyboard will finish the current transmission if the rising edge of the clock pulse for the parity bit has not occurred The system uses the same timing relationships during reads typically with slightly reduced time periods The enhanced keyboard has three operating modes M...

Page 182: ... leaving the keyboard to comply with the USB I F specification discussed in chapter 5 of this guide Packets received at the system s USB I F and decoded as originating from the keyboard result in an SMI being generated An SMI handler routine is invoked that decodes the data and transfers the information to the 8042 keyboard controller where normal legacy keyboard processing takes place hp Compaq P...

Page 183: ...67 66 65 64 63 62 61 60 59 51 50 49 30 48 47 46 45 44 43 42 41 40 38 37 36 35 34 33 32 39 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure C 3 U S English 101 Key Keyboard Key Positions 103 71 104 101 99 98 97 87 91 58 100 90 89 88 74 73 72 57 56 55 54 53 52 96 95 94 93 92 86 85 84 83 82 81 80 79 78 77 76 75 70 69 68 67 66 65 64 63 62 61 60 59 51 50 49 48 47 ...

Page 184: ...16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Figure C 5 U S English Windows 101W Key Keyboard Key Positions 71 112 111 110 96 95 94 93 92 103 104 101 99 98 97 87 91 58 100 90 89 88 74 73 72 57 56 55 54 53 52 86 85 84 83 82 81 80 79 78 77 76 75 70 69 68 67 66 65 64 63 62 61 60 59 51 50 49 48 47 46 45 44 43 42 41 40 38 37 36 35 34 33 32 39 31 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8...

Page 185: ...er a legacy PS 2 type connection or a Universal Serial Bus USB type connection Btn 1 Btn 2 Btn 3 Btn 4 Btn 5 Btn 6 Btn 7 NOTE Main key positions same as Windows Enhanced Figures C 5 or C 6 Figure C 7 7 Button Easy Access Keyboard Layout The 8 button Easy Access Keyboard uses the layout shown in Figure C 8 and uses the PS 2 type connection Btn 8 Btn 7 Btn 6 Btn 5 Btn 4 Btn 3 Btn 2 Btn 1 NOTE Main k...

Page 186: ...n pressed and released invokes a BIOS routine that turns on the num lock LED and shifts into upper case key positions 55 57 72 74 88 90 100 and 101 When pressed and released again these keys revert to the lower case state and the LED is turned off The following keys provide special functions that require specific support by the application Print Scrn The Print Scrn pos 14 key can when pressed gene...

Page 187: ...uted It is up to the application to use or not use this BIOS function The Ctrl and Alt keys can be used together in conjunction with keys in positions 1 13 17 34 39 54 60 71 and 76 84 The Ctrl and Alt key positions used and the sequence in which they are pressed make no difference as long as they are held down at the time the third key is pressed The Ctrl Alt and Delete keystroke combination requi...

Page 188: ...Go to favorite web site AltaVista web site 5 Internet search Search 6 Instant answer Travel expenses 7 E commerce Shopping 8 Button Easy Access Keyboard Button Description Default Function 1 Go to favorite web site Customer web site of choice 2 Go to AltaVista AltaVista web site 3 Search AltaVista search engine 4 Check Email Launches user Email 5 Business Community Industry specification info 6 Ma...

Page 189: ...operation the keyboard generates scan codes compatible with 8088 8086 based systems To enter Mode 1 the scan code translation function of the keyboard controller must be disabled Since translation is not performed the scan codes generated in Mode 1 are identical to the codes required by BIOS Mode 1 is initiated by sending command F0h with the 01h option byte Applications can obtain system codes an...

Page 190: ...2E F0 2E 23 6 07 87 36 F0 36 36 F0 36 24 7 08 88 3D F0 3D 3D F0 3D 25 8 09 89 3E F0 3E 3E F0 3E 26 9 0A 8A 46 F0 46 46 F0 46 27 0 0B 8B 45 F0 45 45 F0 45 28 0C 8C 4E F0 4E 4E F0 4E 29 0D 8D 55 F0 55 55 F0 55 30 2B AB 5D F0 5D 5C F0 5C 31 Backspace 0E 8E 66 F0 66 66 F0 66 32 Insert E0 52 E0 D2 E0 AA E0 52 E0 D2 E0 2A 4 E0 2A E0 52 E0 D2 E0 AA 6 E0 70 E0 F0 70 E0 F0 12 E0 70 E0 F0 70 E0 12 5 E0 12 E...

Page 191: ...D1 E0 AA 6 E0 7A E0 F0 7A E0 F0 12 E0 7A E0 F0 7A E0 12 5 E0 12 E0 7A E0 F0 7A E0 F0 12 6 6D F0 6D 55 7 47 C7 6 6C F0 6C 6 6C na 6 56 8 48 C8 6 75 F0 75 6 75 na 6 57 9 49 C9 6 7D F0 7D 6 7D na 6 58 4E CE 6 79 F0 79 6 7C F0 7C 59 Caps Lock 3A BA 58 F0 58 14 F0 14 60 A 1E 9E 1C F0 1C 1C F0 1C 61 S 1F 9F 1B F0 1B 1B F0 1B 62 D 20 A0 23 F0 23 23 F0 23 63 F 21 A1 2B F0 2B 2B F0 2B 64 G 22 A2 34 F0 34 3...

Page 192: ...F0 6B E0 F0 12 6 61 F0 61 98 E0 50 E0 D0 E0 AA E0 50 E0 D0 E0 2A 4 E0 2A E0 50 E0 D0 E0 AA 6 E0 72 E0 F0 72 E0 F0 12 E0 72 E0 F0 72 E0 12 5 E0 12 E0 72 E0 F0 72 E0 F0 12 6 60 F0 60 99 E0 4D E0 CD E0 AA E0 4D E0 CD E0 2A 4 E0 2A E0 4D E0 CD E0 AA 6 E0 74 E0 F0 74 E0 F0 12 E0 74 E0 F0 74 E0 12 5 E0 12 E0 74 E0 F0 74 E0 F0 12 6 6A F0 6A 100 0 52 D2 6 70 F0 70 6 70 na 6 101 53 D3 6 71 F0 71 6 71 na 6 ...

Page 193: ...E E0 9E E0 1C E0 F0 1C 95 F0 95 Btn 5 9 E0 13 E0 93 E0 2D E0 F0 2D 0C F0 0C Btn 6 9 E0 14 E0 94 E0 2C E0 F0 2C 9D F0 9D Btn 7 9 E0 15 E0 95 E0 35 E0 F0 35 96 F0 96 Btn 8 9 E0 1B E0 9B E0 5B E0 F0 5B 97 F0 97 Make Break Codes Hex NOTES All codes assume Shift Ctrl and Alt keys inactive unless otherwise noted NA Not applicable 1 Shift left key active 2 Ctrl key active 3 Alt key active 4 Left Shift ke...

Page 194: ... keyboard Systems that do not provide a PS 2 interface will ship with a USB keyboard For a detailed description of the PS 2 and USB interfaces refer to Chapter 5 Input Output of this guide The keyboard cable connectors and their pinouts are described in the following figures Pin Function 1 Data 2 Not connected 3 Ground 4 5 VDC 5 Clock 6 Not connected 1 2 3 4 5 6 Figure C 9 PS 2 Keyboard Cable Conn...

Page 195: ...p 4 29 chipsets 2 17 IDSEL 4 4 Client Management 8 12 index addressing 1 3 CMOS 4 22 interface CMOS archive 4 23 audio 2 20 5 28 CMOS clearing 4 22 diskette drive 5 6 CMOS restoring 4 23 IDE 5 1 codec audio 5 31 keyboard pointing device 5 18 Configuration Cycle 4 4 parallel 2 18 5 13 configuration cycle PCI 4 4 serial 2 18 5 10 configuration memory 4 22 USB 2 18 2 19 5 24 configuration space PCI 4...

Page 196: ...2 18 RDRAM 3 5 reference sources 1 2 remote flashing 8 2 restoring CMOS 4 23 RIMM 3 5 ROM BIOS 8 1 ROM flashing 8 2 ROM option 4 7 RS 232 5 10 RTC 4 22 scan codes keyboard C 11 security functions 4 24 security chassis 4 25 security interface 4 25 sensor thermal 4 28 serial interface 2 18 5 10 sideband addressing 4 10 signal distribution 7 11 7 13 Smart Cover Lock 4 25 Smart Cover Sensor 4 25 SMBIO...

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