HP A8002A, Installation Manual

Page: 11 / 32

1 HBA features
This chapter describes the following features of the A8002A and A8003A HBAs:
• Performance speci fi cations , page 11
• Environmental speci fi cations , page 12
• Physical speci fi cations , page 13
• Media speci fi cations , page 13
Performance speci fi cations
The HBAs are 4.25 gigabit per second (Gb/s), Fibre Channel PCIe HBAs. The HBAs’ FC controller
incorporates a multifunction native PCI Express (PCIe) core that is compliant to the PCIe Base Speci fi cation
1.0a and PCI Express CEM Speci fi cation 1.0a. The HBAs support packet transfers up to 2048 bytes on
the PCIe link with support for x1 or x4 lane negotiation. The supported physical PCIe connector is
x4, x8, or x16.
The PCI-Express architecture is an open speci
fi cation designed to address the wide range of current
and future system interconnection requirements. It also de fi nes a fl exible, scalable, high-speed, serial,
point-to-point, hot pluggable/hot swappable interconnect that is software-compatible with PCI. This
architecture allows the HBAs to use the same drivers and management tools as the HBAs for PCI and
PCI-X systems.
These HBAs have the following performance features:
• Compliance with the PCI-Express1.0a speci fi cation and PCI Express CEM Speci fi cation 1.0a:
• x1 or x4 lane link interface at 2.5Gb/s per lane (auto-negotiated with system)
• VC0 (1 Virtual Channel) and TC0 (1 Traf fi c Class) support
• Con fi guration, IO, memory read/write, completion, and message support
• 64-bit addressing support
• 32-bit CRC for all transmitted data packets
• 16-bit CRC on all link message information
• Auto-negotiation between 1Gb, 2Gb, or 4Gb link attachments
• High performance Fibre Channel host adapter
• Full support for all Fibre Channel topologies: point-to-point, arbitrated loop, and fabric
• Full support for Fibre Channel service class 2 and 3
• Maximum Fibre Channel, which is throughput achieved through full-duplex hardware support
• End-to-end data path-parity and CRC protection, including internal data path RAMs
• Architectural support for multiple upper-layer protocols
• State-of-the-art circuitry:
•
All PCIe and Fibre Channel functionality contained within a single, custom, high-density, fully
integrated Fibre Channel controller
• Internal ARM 1136J-S processors with instruction and data cache for each port
• Internal serializer deserializer (SerDes) 1-Gb/2-Gb/4-Gb cores for Fibre Channel and 2.5-Gb
cores for PCIe
• Compliance with the PCIe base and CEM 1.0a speci fi cations:
• x1 or x4 lane link interface (auto-negotiated with system) at 2.5-Gb/s
• Support for VC0 (1 Virtual Channel) and TC0 (1 Traf
fi c Class)
• Con fi guration, IO, memory, read/write, completion, and message support
• Support for 64-bit addressing
A8002A PCI-e single-port 4Gb FC adapter and A8003A PCI-e dual-port 4Gb FC adapter for Linux and
Windows systems installation guide
11