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4-Key Enhanced Touch I/O Flash MCU

BS83A04C

Revision: V1.00 Date: March 24, 2020

Summary of Contents for BS83A04C

Page 1: ...4 Key Enhanced Touch I O Flash MCU BS83A04C Revision V1 00 Date March 24 2020 ...

Page 2: ...r Characteristics LIRC 11 Operating Frequency Characteristic Curves 12 System Start Up Time Characteristics 12 Input Output Characteristics 13 Memory Characteristics 13 LVR Electrical Characteristics 14 Power on Reset Characteristics 14 System Architecture 14 Clocking and Pipelining 14 Program Counter 15 Stack 16 Arithmetic and Logic Unit ALU 16 Flash Program Memory 17 Structure 17 Special Vectors...

Page 3: ...stem Clock Configurations 31 Internal High Speed RC Oscillator HIRC 32 Internal 32kHz Oscillator LIRC 32 Operating Modes and System Clocks 32 System Clocks 32 System Operation Modes 33 Control Registers 34 Operating Mode Switching 36 Standby Current Considerations 39 Wake up 39 Watchdog Timer 40 Watchdog Timer Clock Source 40 Watchdog Timer Control Register 40 Watchdog Timer Operation 41 Reset and...

Page 4: ... Operation 80 I2 C Registers 81 I2 C Bus Communication 84 I2 C Time out Control 87 Interrupts 89 Interrupt Registers 89 Interrupt Operation 92 External Interrupt 93 I2 C Interrupt 93 Time Base Interrupt 93 Multi function Interrupt 94 Touch Key TKRCOV Interrupt 95 Touch Key Threshold TKTH Interrupt 95 TM Interrupt 95 Interrupt Wake up Function 96 Programming Considerations 96 Application Circuits 9...

Page 5: ...ced Touch I O Flash MCU Instruction Definition 102 Package Information 111 8 pin SOP 150mil Outline Dimensions 112 10 pin DFN 3mm 3mm 0 75mm Outline Dimensions 113 10 pin MSOP 118mil Outline Dimensions 114 16 pin NSOP 150mil Outline Dimensions 115 ...

Page 6: ... instructions executed in one or two instruction cycles Table read instructions 63 powerful instructions 4 level subroutine nesting Bit manipulation instruction Peripheral Features Flash Program Memory 1K 16 RAM Data Memory 128 8 Touch Key Data Memory 24 8 Emulated EEPROM Memory 32 16 Watchdog Timer function 8 bidirectional I O lines Single external interrupt line shared with I O pin Single 10 bit...

Page 7: ...vironments This device includes fully integrated low and high speed oscillators which require no external components for their implementation The ability to operate and switch dynamically between a range of operating modes using different clock sources gives users the ability to optimise microcontroller operation and minimise power consumption Easy communication with the outside world is provided ...

Page 8: ...e is only for OCDS EV chips The OCDSDA and OCDSCK pins are the OCDS dedicated pins 3 For less pin count package types there will be unbonded pins which should be properly configured to avoid unwanted current consumption resulting from floating input conditions Refer to the Standby Current Considerations and Input Output Ports sections Pin Descriptions With the exception of the power pins all pins ...

Page 9: ... Register enabled pull up and wake up KEY3 PAS0 AN Touch key input PA4 KEY4 PA4 PAPU PAWU PAS1 ST CMOS General purpose I O Register enabled pull up and wake up KEY4 PAS1 AN Touch key input PA5 KEY1 PA5 PAPU PAWU PAS1 ST CMOS General purpose I O Register enabled pull up and wake up KEY1 PAS1 AN Touch key input PA6 CTCK INT PA6 PAPU PAWU ST CMOS General purpose I O Register enabled pull up and wake ...

Page 10: ...nstruction type etc can all exert an influence on the measured values Operating Voltage Characteristics Ta 40 C 85 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Operating Voltage HIRC fSYS fHIRC 8MHz 1 8 5 5 V Operating Voltage LIRC fSYS fLIRC 32kHz 1 8 5 5 V Standby Current Characteristics Ta 25 C Symbol Standby Mode Test Conditions Min Typ Max Max 85 C Unit VDD Conditions ISTB SLEEP Mo...

Page 11: ...he measured values High Speed Internal Oscillator HIRC Frequency Accuracy During the program writing operation the writer will trim the HIRC oscillator at a user selected HIRC frequency and user selected voltage of either 3V or 5V Symbol Parameter Test Conditions Min Typ Max Unit VDD Temp fHIRC 8MHz Writer Trimmed HIRC Frequency 3V 5V 25 C 1 8 1 MHz 40 C 85 C 2 8 2 2 2V 5 5V 25 C 2 5 8 2 5 40 C 85...

Page 12: ...set RRPOR 5V ms 42 48 54 ms System Reset Delay Time WDTC RSTC software reset System Reset Delay Time Reset source from WDT overflow 14 16 18 ms tSRESET Minimum Software Reset Width to Reset 45 90 120 μs Note 1 For the System Start up time values whether fSYS is on or off depends upon the mode type and the chosen fSYS system oscillator Details are provided in the System Operating Modes section 2 Th...

Page 13: ...stor and then measuring the pin current at the specified supply voltage level Dividing the voltage by this measured current provides the RPH value Memory Characteristics Ta 40 C 85 C unless otherwise specified Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions Flash Program Memory Emulated EEPROM Memory VDD Operating Voltage for Read 1 8 5 5 V Operating Voltage for Erase Write Flash ...

Page 14: ...ching and instruction execution are overlapped hence instructions are effectively executed in one cycle with the exception of branch or call instructions An 8 bit wide ALU is used in practically all instruction set operations which carries out arithmetic operations logic operations rotation increment decrement branch decisions etc The internal data path is simplified by moving data through the Acc...

Page 15: ...1 Execute Inst PC Fetch Inst PC 2 Execute Inst PC 1 System Clocking and Pipelining Fetch Inst 1 1 MOV A 12H 2 CALL DELAY 3 CPL 12H 4 5 6 DELAY NOP Execute Inst 1 Fetch Inst 2 Execute Inst 2 Fetch Inst 3 Flush Pipeline Fetch Inst 6 Execute Inst 6 Fetch Inst 7 Instruction Fetching Program Counter During program execution the Program Counter is used to keep track of the address of the next instructio...

Page 16: ... interrupt takes place the interrupt request flag will be recorded but the acknowledge signal will be inhibited When the Stack Pointer is decremented by RET or RETI the interrupt will be serviced This feature prevents stack overflow allowing the programmer to use the structure more easily However when the stack is full a CALL subroutine instruction can still be executed which will result in a stac...

Page 17: ... location 0000H is reserved for use by the device reset for program initialisation After a device reset is initiated the program will jump to this location and begin execution Look up Table Any location within the Program Memory can be defined as a look up table where programmers can store fixed data To use the look up table the table pointer must first be setup by placing the address of the look ...

Page 18: ...ltaneous use cannot be avoided the interrupts should be disabled prior to the execution of any main routine table read instructions Note that all table related instructions require two instruction cycles to complete their operation Table Read Program Example tempreg1 db temporary register 1 tempreg2 db temporary register 2 mov a 06h initialise low table pointer note that this address is referenced...

Page 19: ...onnector Signals MCU Programming Pins Note may be resistor or capacitor The resistance of must be greater than 1kΩ or the capacitance of must be less than 1nF On Chip Debug Support OCDS There is an EV chip named BS83AV04C which is used to emulate the BS83A04C device The EV chip device also provides an On Chip Debug function to debug the real MCU device during the development process The EV chip an...

Page 20: ...n Bank 0 The Touch Key Data Memory is located in Bank 5 Bank 7 Switching between the different Data Memory banks is achieved by setting the Bank Pointer to the correct value The start address of the Data Memory for the device is the address 00H Special Purpose Data Memory General Purpose Data Memory Touch Key Data Memory Available Bank Capacity Bank Capacity Banks 0 128 8 Bank 0 80H FFH 24 8 Bank ...

Page 21: ...TATUS TBHP TBLH TBLP PCL ACC BP MP1 IAR1 MP0 IAR0 IICA IICD IICC1 IICC0 ED3L ED2H ED2L ED1H ED1L ED0H ED0L TKM0THS TKM0TH16H TKM0TH16L TKC2 TKM0C2 TKM0C1 TKM0C0 TKM0ROH TKM0ROL TKM016DH TKM016DL TKC1 TK16DH TK16DL TKC0 TKTMR EAR 40H 41H 42H 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 59H 58H 5BH 5AH 5DH 5CH 5FH 53H 54H 55H 56H 57H 5EH 60H 61H 62H 69H 68H 6BH 6AH 6DH 6CH 6FH 6EH...

Page 22: ...Pointers MP0 MP1 Two Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing Registers is carried out the actual address that the microcontroller is directed to...

Page 23: ...he temporary storage function of the Accumulator for example when transferring data between one user defined register and another it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted Program Counter Low Register PCL To provide additional program control functions the low byte of the Program Counter is made accessible to pro...

Page 24: ... high nibble into the low nibble in subtraction otherwise AC is cleared Z is set if the result of an arithmetic or logical operation is zero otherwise Z is cleared OV is set if an operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa otherwise OV is cleared PDF is cleared by a system power up or executing the CLR WDT instruction PDF is s...

Page 25: ...igner The availability of the Emulated EEPROM storage allows information such as product identification numbers calibration values specific user data system setup data or other product information to be stored directly within the product microcontroller Emulated EEPROM Data Memory Structure The Emulated EEPROM Data Memory capacity is 32 16 bits for the device The Emulated EEPROM Erase operation is...

Page 26: ...9 D8 ECR EWRTS1 EWRTS0 EEREN EER EWREN EWR ERDEN ERD Emulated EEPROM Register List EAR Register Bit 7 6 5 4 3 2 1 0 Name EAR4 EAR3 EAR2 EAR1 EAR0 R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 5 Unimplemented read as 0 Bit 4 0 EAR4 EAR0 Emulated EEPROM address bit 4 bit 0 ED0L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 ...

Page 27: ... W POR 0 0 0 0 0 0 0 0 Bit 7 0 D15 D8 The third Emulated EEPROM data bit 15 bit 8 ED3L Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 The fourth Emulated EEPROM data bit 7 bit 0 ED3H Register Bit 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D15 D8 T...

Page 28: ...d 1 Activate a write cycle When this bit is set high by the application program a write cycle will be activated This bit will be automatically reset to zero by the hardware after the write cycle has finished Setting this bit high will have no effect if the EWREN has not first been set high Bit 1 ERDEN Emulated EEPROM Read enable 0 Disable 1 Enable This bit is used to enable the Emulated EEPROM rea...

Page 29: ...ss is only specified by the EAR4 EAR2 bits in the EAR register and the content of EAR1 EAR0 in the EAR register is not used to specify the unit address To write data to the Emulated EEPROM the EWREN bit in the ECR register must first be set high to enable the write function After this the EWR bit in the ECR register must be immediately set high to initiate a write cycle These two instructions must...

Page 30: ...operation is totally complete Otherwise Emulated EEPROM read write or erase operation will fail Programming Examples Erase a Data Page of the Emulated EEPROM polling method MOV A EEPROM_ADRES user defined page MOV EAR A MOV A 00H Erase time 2ms 40H for 4ms 80H for 8ms C0H for 16ms MOV ECR A CLR EMI SET EEREN set EEREN bit enable erase operation SET EER start Erase Cycle set EER bit executed immedi...

Page 31: ...cillator Overview In addition to being the source of the main system clock the oscillators also provide clock sources for the Watchdog Timer and Time Base Interrupts Two fully integrated internal oscillators requiring no external components are provided to form a wide range of both fast and slow system oscillators The high frequency oscillator provides higher performance but carries with it the di...

Page 32: ...lation frequency are minimised Operating Modes and System Clocks Present day applications require that their microcontrollers have high performance but often still demand that they consume as little power as possible conflicting requirements that are especially true in battery powered portable applications The fast clocks required for high performance will by their nature increase current consumpt...

Page 33: ...controller each one with its own special characteristics and which can be chosen according to the specific performance and power requirements of the application There are two modes allowing normal operation of the microcontroller the FAST Mode and SLOW Mode The remaining four modes the SLEEP IDLE0 IDLE1 and IDLE2 Mode are used when the microcontroller CPU is switched off to conserve power Operatio...

Page 34: ...ction will also be stopped too However the fLIRC clock still continue to operate since the WDT function is always enabled IDLE0 Mode The IDLE0 Mode is entered when a HALT instruction is executed and when the FHIDEN bit in the SCC register is low and the FSIDEN bit in the SCC register is high In the IDLE0 Mode the CPU will be switched off but the low speed oscillator will be turned on to drive some...

Page 35: ... 1 Enable This bit is used to control whether the high speed oscillator is activated or stopped when the CPU is switched off by executing a HALT instruction Bit 0 FSIDEN Low Frequency oscillator control when CPU is switched off 0 Disable 1 Enable This bit is used to control whether the low speed oscillator is activated or stopped when the CPU is switched off by executing a HALT instruction HIRCC R...

Page 36: ...SIDEN bits in the SCC register FAST fSYS fH fH 64 fH on CPU run fSYS on fSUB on SLOW fSYS fSUB fSUB on CPU run fSYS on fH on off IDLE0 HALT instruction executed CPU stop FHIDEN 0 FSIDEN 1 fH off fSUB on IDLE1 HALT instruction executed CPU stop FHIDEN 1 FSIDEN 1 fH on fSUB on IDLE2 HALT instruction executed CPU stop FHIDEN 1 FSIDEN 0 fH on fSUB off SLEEP HALT instruction executed CPU stop FHIDEN 0 ...

Page 37: ...set to 000 110 and then the system clock will respectively be switched to fH fH 64 However if fH is not used in SLOW mode and thus switched off it will take some time to re oscillate and stabilise when switching to the FAST mode from the SLOW Mode This is monitored using the HIRCF bit in the HIRCC register The time duration required for the high speed system oscillator stabilization is specified i...

Page 38: ...tus register the Power Down flag PDF will be set and the Watchdog time out flag TO will be cleared The WDT will be cleared and resume counting as the WDT function is always enabled Entering the IDLE1 Mode There is only one way for the device to enter the IDLE1 Mode and that is to execute the HALT instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal ...

Page 39: ...woken up again it will take a considerable time for the original system oscillator to restart stabilise and allow normal operation to resume After the system enters the SLEEP or IDLE Mode it can be woken up from one of various sources listed as follows An external falling edge on Port A A system interrupt A WDT overflow When the device executes the HALT instruction it will enter the SLEEP or IDLE ...

Page 40: ...t period as well as the enable and reset operation WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 0 1 1 Bit 7 3 WE4 WE0 WDT function software control 01010 10101 Enable Other values Reset MCU When these bits are changed to any other values due to environmental noise the microcontroller will be reset this reset operation will...

Page 41: ...ll reset the device after a delay time tSRESET After power on these bits will have a value of 01010B WE4 WE0 Bits WDT Function 01010B 10101B Enable Any other value Reset MCU Watchdog Timer Function Control Under normal program operation a Watchdog Timer time out will initialise a device reset and set the status bit TO However if the system is in the SLEEP or IDLE Mode when a Watchdog Timer time ou...

Page 42: ...erflows and resets the microcontroller All types of reset operations result in different register conditions being setup Reset Functions There are several ways in which a microcontroller reset can occur through events occurring internally Power on Reset The most fundamental and unavoidable reset is the one that occurs after power is first applied to the microcontroller As well as ensuring that the...

Page 43: ...1 Unimplemented read as 0 Bit 0 WRF WDT control register software reset flag Described elsewhere Low Voltage Reset LVR The microcontroller contains a low voltage reset circuit in order to monitor the supply voltage of the device and provides an MCU reset should the value fall below a certain predefined level The LVR function is always enabled in the FAST or SLOW mode with a specific LVR voltage VL...

Page 44: ...dog time out flag TO will be set to 1 WDT Time out Internal Reset tRSTD WDT Time out Reset during Normal Operation Timing Chart Watchdog Time out Reset during SLEEP or IDLE Mode The Watchdog time out Reset during SLEEP or IDLE Mode is a little different from other kinds of reset Most of the conditions remain unchanged except that the Program Counter and the Stack Pointer will be cleared to 0 and t...

Page 45: ...table will reflect the situation for the larger package type Register Power On Reset LVR Reset Normal Operation WDT Time out Normal Operation WDT Time out IDLE SLEEP IAR0 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u MP0 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u IAR1 x x x x x x x x u u u u u u u u u u u u u u u u u u u u u u u u MP1 x x x x x x x x u u u u ...

Page 46: ...6DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKC1 0 0 0 0 0 11 0 0 0 0 0 11 0 0 0 0 0 11 u u u u u u u TKM016DL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM016DH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM0ROL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM0ROH 0 0 0 0 0 0 u u TKM0C0 0 0 0 0 0 0 0 0 0 0 0 0 0...

Page 47: ...PAC5 PAC4 PAC3 PAC2 PAC1 PAC0 PAPU PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 PAWU PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 I O Logic Function Register List Pull high Resistors Many product applications require pull high resistors for their switch inputs usually requiring the use of an external resistor To eliminate the need for these external resistors all I O pins when configured as ...

Page 48: ...feature using the PAWU register Note that the wake up function can be controlled by the wake up control registers only when the pin is selected as a general purpose input and the MCU enters the SLEEP or IDLE Mode PAWU Register Bit 7 6 5 4 3 2 1 0 Name PAWU7 PAWU6 PAWU5 PAWU4 PAWU3 PAWU2 PAWU1 PAWU0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 PAWU7 PAWU0 PA7 PA0 wake up function...

Page 49: ...abeled as IFS which can select the desired functions of the multi function pin shared pins The most important point to note is to make sure that the desired pin shared function is properly selected and also deselected For most pin shared functions to select the desired pin shared function the pin shared function should first be correctly selected using the corresponding pin shared control register...

Page 50: ...01 PAS00 PA0 Pin Shared function selection 00 01 10 PA0 CTCK INT 11 SCL PAS1 Register Bit 7 6 5 4 3 2 1 0 Name PAS17 PAS16 PAS13 PAS12 PAS11 PAS10 R W R W R W R W R W R W R W POR 0 0 0 0 0 0 Bit 7 6 PAS17 PAS16 PA7 Pin Shared function selection 00 01 10 PA7 11 CTP Bit 5 4 Unimplemented read as 0 Bit 3 2 PAS13 PAS12 PA5 Pin Shared function selection 00 01 10 PA5 11 KEY1 Bit 1 0 PAS11 PAS10 PA4 Pin ...

Page 51: ... an input state the level of which depends on the other connected circuitry and whether pull high selections have been chosen If the port control registers are then programmed to setup some pins as outputs these output pins will have an initial high output value unless the associated port data registers are first programmed Selecting which pins are inputs and which are outputs can be achieved byte...

Page 52: ...grammed internal comparators When the free running counter has the same value as the pre programmed comparator known as a compare match situation a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin The internal TM counter is driven by a user selectable clock source which can be an internal clock or an external pin TM Clock ...

Page 53: ...ernal 8 bit buffer reading or writing to these register pairs must be carried out in a specific way The important point to note is that data transfer to and from the 8 bit buffer and its related low byte only takes place when a write or read operation to its corresponding high byte is executed As the CCRA registers are implemented in the way shown in the following diagram and accessing this regist...

Page 54: ...by a user selectable internal or external clock source There are also two internal comparators with the names Comparator A and Comparator P These comparators will compare the value in the counter with CCRP and CCRA registers The CCRP is three bits wide whose value is compared with the highest three bits in the counter while the CCRA is the ten bits and therefore compares with all counter bits The ...

Page 55: ...H 16 011 fH 64 100 fSUB 101 fSUB 110 CTCK rising edge clock 111 CTCK falling edge clock These three bits are used to select the clock source for the CTM The external pin clock source can be chosen to be active on the rising or falling edge The clock source fSYS is the system clock while fH and fSUB are other internal clocks the details of which can be found in the Operating Modes and System Clocks...

Page 56: ...M1 CTM0 Select CTM Operating Mode 00 Compare Match Output Mode 01 Undefined 10 PWM Output Mode 11 Timer Counter Mode These bits setup the required operating mode for the CTM To ensure reliable operation the CTM should be switched off before any changes are made to the CTM1 and CTM0 bits In the Timer Counter Mode the CTM output pin state is undefined Bit 5 4 CTIO1 CTIO0 Select CTM external pin CTP ...

Page 57: ...tch occurs In the PWM Output Mode it determines if the PWM signal is active high or active low Bit 2 CTPOL CTM CTP Output polarity Control 0 Non invert 1 Invert This bit controls the polarity of the CTM output pins When the bit is set high the CTM output pins will be inverted and not inverted when the bit is zero It has no effect if the CTM is in the Timer Counter Mode Bit 1 CTDPX CTM PWM period d...

Page 58: ...ce the counter is enabled and running it can be cleared by three methods These are a counter overflow a compare match from Comparator A and a compare match from Comparator P When the CTCCLR bit is low there are two ways in which the counter can be cleared One is when a compare match from Comparator P the other is when the CCRP bits are all zero which allows the counter to overflow Here both CTMAF ...

Page 59: ...ng the CTOC bit Note that if the CTIO1 and CTIO0 bits are zero then no pin change will take place Counter Value 0x3FF CCRP CCRA CTON CTPAU CTPOL CCRP Int Flag CTMPF CCRA Int Flag CTMAF CTM O P Pin Time CCRP 0 CCRP 0 Counter overflow CCRP 0 Counter cleared by CCRP value Pause Resume Stop Counter Restart CTCCLR 0 CTM 1 0 00 Output pin set to initial Level Low if CTOC 0 Output Toggle with CTMAF flag ...

Page 60: ...Output not affected by CTMAF flag Remains High until reset by CTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when CTPOL is high CTMPF not generated No CTMAF flag generated on CCRA overflow Output does not change CTCCLR 1 CTM 1 0 00 CCRA Int Flag CTMAF CCRP Int Flag CTMPF Compare Match Output Mode CTCCLR 1 Note 1 With CTCCLR 1 a Comparator A...

Page 61: ...ne register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers An interrupt fla...

Page 62: ...ty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRP CTM O P Pin CTOC 0 CCRA Int Flag CTMAF CCRP Int Flag CTMPF CTDPX 0 CTM 1 0 10 PWM Output Mode CTDPX 0 Note 1 Here CTDPX 0 Counter cleared by CCRP 2 A counter clear sets PWM Period 3 The internal PWM function continues running even when CTIO 1 0 00 or 01 4 The...

Page 63: ... Counter Reset when CTON returns high PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRA CTM O P Pin CTOC 0 CTDPX 1 CTM 1 0 10 PWM Output Mode CTDPX 1 Note 1 Here CTDPX 1 Counter cleared by CCRA 2 A counter clear sets PWM Period 3 The internal PWM function continues even when CTIO 1 0 00 or 01 4 The CTC...

Page 64: ...eload register TKC0 Touch key function control register 0 TKC1 Touch key function control register 1 TKC2 Touch key function control register 2 TK16DL Touch key function 16 bit counter low byte TK16DH Touch key function 16 bit counter high byte TKM016DL Touch key module 0 16 bit C F counter low byte TKM016DH Touch key module 0 16 bit C F counter high byte TKM0ROL Touch key module 0 reference oscil...

Page 65: ...USY R W R W R W R W R W R W R W R W R POR 0 0 0 0 0 0 1 0 Bit 7 TKRAMC Touch key data memory access control 0 Accessed by MCU 1 Accessed by touch key module This bit determines that the touch key data memory is used by the MCU or the touch key module However the touch key module will have the priority to access the touch key data memory when the touch key module operates in the auto scan mode or t...

Page 66: ...tection start control 0 Stopped or no operation 0 1 Start detection The touch key module 0 16 bit C F counter touch key function 16 bit counter and 5 bit time slot unit period counter will automatically be cleared when this bit is cleared to zero However the 8 bit programmable time slot counter will not be cleared When this bit is changed from low to high the touch key module 0 16 bit C F counter ...

Page 67: ...en the touch key scan operation is completed In the periodic auto scan mode this bit is cleared to 0 automatically when the last scan operation in the WDT time out cycle is completed or when any key C F counter value is less than the lower threshold if M0KnTHS 0 or when the value is larger than the upper threshold if M0KnTHS 1 TKC1 Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 TK16S1 TK16S0 TKFS1 TKF...

Page 68: ...y function 16 bit counter value This 16 bit counter can be used to calibrate the reference or key oscillator frequency When the touch key time slot counter overflows in the manual scan mode this 16 bit counter will be stopped and the counter content will be unchanged However this 16 bit counter content will be cleared to zero at the end of the time slot 0 slot 1 and slot 2 but kept unchanged at th...

Page 69: ...ol the touch key oscillator frequency doubling function When this bit is set to 1 the key oscillator frequency will be doubled Bit 4 Unimplemented read as 0 Bit 3 M0SOFC Touch key module 0 C F oscillator frequency hopping function control selection 0 Controlled by the M0SOF2 M0SOF0 1 Controlled by hardware circuit This bit is used to select the touch key oscillator frequency hopping function contr...

Page 70: ...reference oscillator is selected as the time slot clock source The combination of the M0TSS and M0K4EN M0K1EN bits determines whether the reference oscillator is used or not When the TKBUSY bit is changed from high to low the M0ROEN bit will automatically be cleared to zero to disable the reference oscillator In the manual scan mode the reference oscillator should first be enabled before setting t...

Page 71: ...ttings for these bits are invalid when TKMOD1 TKMOD0 01 or TSC 1 Bit 1 0 M0SK01 M0SK00 Touch key module 0 time slot 0 key scan select 00 KEY1 01 KEY2 10 KEY3 11 KEY4 These bits are used to select the desired scan key in time slot 0 in the auto scan mode or the periodic auto scan mode or used as the multiplexer for scan key select in the manual mode TKM0TH16H TKM0TH16L Touch Key Module 0 16 bit Thr...

Page 72: ...son flag 0 Not less than lower threshold or not larger than upper threshold 1 Less than lower threshold or larger than upper threshold Bit 4 M0K1THF Touch key module 0 KEY1 upper lower threshold comparison flag 0 Not less than lower threshold or not larger than upper threshold 1 Less than lower threshold or larger than upper threshold Bit 3 M0K4THS Touch key module 0 KEY4 upper or lower threshold ...

Page 73: ...e 0 contains four touch key inputs namely KEY1 KEY4 which are shared with logical I O pins and the desired function is selected using register bits The touch key has its own independent sense oscillator There are therefore four sense oscillators within the touch key module 0 During this reference clock fixed interval the number of clock cycles generated by the sense oscillator is measured and it i...

Page 74: ...o Scan Mode There are three scan modes contained for the touch key function The auto scan mode the periodic auto scan mode and the manual scan mode are selected using the TKMOD1 TKMOD0 bits in the TKC0 register The auto scan mode can minisize the load of the application program and improve the touch key scan operation performance When the TKMOD1 TKMOD0 bits are set to 00 the auto scan mode is selc...

Page 75: ...alue for the next selected key will be read from the touch key data memory and loaded into the TKM0ROH TKM0ROL registers Then the 16 bit C F counter value of the current scanned key will be written into the corresponding touch key data memory The whole auto scan operation will sequentially be carried out in the above specific way from time slot 0 to time slot 3 At the end of the time slot 3 key sc...

Page 76: ... threshold if M0KnTHS 1 this indicates that the touch key state changes then the M0KnTHF flag will be set high by the hardware and an interrupt signal will be generated Note that if the touch key threshold TKTH interrupt occurs 1 byte data will be written to the TKM0ROL register because the TKM0ROH TKM0ROL register pair will be loaded with the corresponding next time slot capacitor value from the ...

Page 77: ...t Start bit TKST 0 1 Busy flag TKBUSY 1 All Time Slot Counter overflow TKRCOV 0 Initiate Time Slot 16 bit C F Counter All Time Slot 16 bit C F Counter start to count Time Slot 16 bit C F Counter keep counting TKRCOV 1 Touch key busy flag TKBUSY 0 Generate Interrupt request flag Read C F counter value from TKM016DH TKM016DL Touch key scan end Set TKST bit 1 0 End Touch Key Manual Scan Mode Flowchar...

Page 78: ...ot 16 bit C F Counter All Time Slot counter 16 bit C F counter start to count Time Slot 16 bit C F Counter keep counting Yes TKRCOV 1 Generate Interrupt request flag Read C F counter value from Data Memory Bank 5 Touch key scan end Set TKST bit 1 0 End Load Ref OSC internal Capacitor value from Data Memory Bank 6 Store C F counter value to Data Memory Bank 5 All key scan finish Yes No Touch key bu...

Page 79: ...COV flag which is the time slot counter flag will go high when the counter overflows in the manual scan mode When this happens an interrupt signal will be generated In the auto scan mode if the time slot counter overflows but the touch key auto scan operation is not completed the TKRCOV bit will not be set When the touch key auto scan operation is completed the TKRCOV bit and the Touch Key TKRCOV ...

Page 80: ...as each device on the I2 C bus is identified by a unique address which will be transmitted and received on the I2 C bus When two devices communicate with each other on the bidirectional I2 C bus one is known as the master device and one as the slave device Both master and slave can transmit and receive data however it is the master device that has overall control of the bus For the device which on...

Page 81: ...on shown in the following table I2 C Debounce Time Selection I2 C Standard Mode 100kHz I2 C Fast Mode 400kHz No Debounce fSYS 2MHz fSYS 5MHz 2 system clock debounce fSYS 4MHz fSYS 10MHz 4 system clock debounce fSYS 8MHz fSYS 20MHz I2 C Minimum fSYS Frequency Requirement I2 C Registers There are three control registers associated with the I2 C bus IICC0 IICC1 and IICTOC one address register IICA an...

Page 82: ...r is used to control the enable disable function and to set the data transmission clock frequency The IICC1 register contains the relevant flags which are used to indicate the I2 C communication status Another register IICTOC is used to control the I2 C time out function and is described in the corresponding section IICC0 Register Bit 7 6 5 4 3 2 1 0 Name IICDEB1 IICDEB0 IICEN R W R W R W R W POR ...

Page 83: ...I2 C slave device is transmitter or receiver selection 0 Slave device is the receiver 1 Slave device is the transmitter Bit 3 TXAK I2 C Bus transmit acknowledge flag 0 Slave send acknowledge flag 1 Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag After the slave device receipt of 8 bits of data this bit will be transmitted to the bus on the 9th clock from the slave ...

Page 84: ...address the HAAS bit in the IICC1 register will be set and an I2 C interrupt will be generated After entering the interrupt service routine the slave device must first check the condition of the HAAS and IICTOF bits to determine whether the interrupt source originates from an address match or from the completion of an 8 bit data transfer completion or from the I2 C bus time out occurrence During a...

Page 85: ...a byte transfer or from the I2 C bus time out occurrence When a slave address is matched the device must be placed in either the transmit mode and then write data to the IICD register or in the receive mode where it must implement a dummy read from the IICD register to release the SCL line I2 C Bus Read Write Signal The SRW bit in the IICC1 register defines whether the master device wishes to read...

Page 86: ...as a receiver the slave device must read the transmitted data from the IICD register When the slave receiver receives the data byte it must generate an acknowledge bit known as TXAK on the 9th clock The slave device which is setup as a transmitter will check the RXAK bit in the IICC1 register to determine if it is to send another data byte if not then it will release the SDA line and await the rec...

Page 87: ... ISR Flowchart I2 C Time out Control In order to reduce the problem of I2 C lockup due to reception of erroneous clock sources a time out function is provided If the clock source to the I2 C is not received for a while then the I2 C circuitry and registers will be reset after a certain time out period The time out counter starts counting on an I2 C bus START address match condition and is cleared ...

Page 88: ... the following condition Registers After I2 C Time out IICD IICA IICC0 No change IICC1 Reset to POR condition I2 C Registers after Time out The IICTOF flag can be cleared by the application program There are 64 time out periods which can be selected using IICTOS bit field in the IICTOC register The time out time is given by the formula 1 64 32 fSUB This gives a time out period which ranges from ab...

Page 89: ...e Data Memory as shown in the accompanying table The number of registers falls into three categories The first is the INTC0 INTC1 registers which setup the primary interrupts the second is the MFI0 MFI1 registers which setup the Multi function interrupts Finally there is an INTEG register to setup the external interrupt trigger edge type Each register contains a number of enable bits to enable or ...

Page 90: ...6 MF1F Multi function interrupt 1 request flag 0 No request 1 Interrupt request Bit 5 MF0F Multi function interrupt 0 request flag 0 No request 1 Interrupt request Bit 4 INTF INT interrupt request flag 0 No request 1 Interrupt request Bit 3 MF1E Multi function interrupt 1 control 0 Disable 1 Enable Bit 2 MF0E Multi function interrupt 0 control 0 Disable 1 Enable Bit 1 INTE INT interrupt control 0 ...

Page 91: ...h key TKRCOV interrupt request flag 0 No request 1 Interrupt request Bit 3 2 Unimplemented read as 0 Bit 1 TKTHE Touch key threshold TKTH interrupt control 0 Disable 1 Enable Bit 0 TKRCOVE Touch key TKRCOV interrupt control 0 Disable 1 Enable MFI1 Register Bit 7 6 5 4 3 2 1 0 Name CTMAF CTMPF CTMAE CTMPE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 CTMAF CTM Comparator A m...

Page 92: ...companying diagrams with their order of priority Some interrupt sources have their own individual vector while others share the same multi function interrupt vector Once an interrupt subroutine is serviced all the other interrupts will be blocked as the global interrupt enable bit EMI bit will be cleared automatically This will prevent any further interrupt nesting from occurring However if other ...

Page 93: ...sed to disable the external interrupt function I2 C Interrupt An I2 C interrupt request will take place when the I2 C Interrupt request flag I2CF is set which occurs when a byte of data has been received or transmitted by the I2 C interface or an I2 C slave address match occurs or an I2 C bus time out occurs To allow the program to branch to its respective interrupt vector address the global inter...

Page 94: ...ction interrupts Unlike the other independent interrupts these interrupts have no independent source but rather are formed from other existing interrupt sources namely the touch key TKRCOV interrupt touch key threshold TKTH interrupt and TM interrupts A Multi function interrupt request will take place when any of the Multi function interrupt request flags MFnF are set The Multi function interrupt ...

Page 95: ... the upper threshold if M0KnTHS 1 To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI Touch Key Threshold TKTH Interrupt enable bit TKTHE and associated Multi function interrupt enable bit must first be set When the interrupt is enabled the stack is not full and any of the above described threshold comparison conditions occurs a subroutine ...

Page 96: ...as only the Multi function interrupt request flags MFnF will be automatically cleared the individual request flag for the function needs to be cleared by the application program It is recommended that programs do not use the CALL instruction within the interrupt service subroutine Interrupts often occur in an unpredictable manner or need to be serviced immediately If only one stack is left and the...

Page 97: ... March 24 2020 BS83A04C 4 Key Enhanced Touch I O Flash MCU Application Circuits VDD VSS VDD 0 1μF PA3 KEY3 PA4 KEY4 PAD PAD PA5 KEY1 PA1 KEY2 PAD PAD PA2 CTPB SDA ICPCK PA0 CTCK INT SCL ICPDA PA7 CTP PA6 CTCK INT ...

Page 98: ...cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only one ...

Page 99: ...h instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the condition of ...

Page 100: ...ote Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1Note Z AND A x Logical AND immediat...

Page 101: ... A x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page or current page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR m Clear Data Memory 1Note None SET m Set Data Memory 1Note None CLR WDT Clear Watchdog T...

Page 102: ...tor and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description Data i...

Page 103: ... PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Repetitively executing this instruction without alternately executing CLR WDT2 will have n...

Page 104: ...this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C DEC m Decrement Data Memory Description Data in the specified Data Memory is decremented by 1 Operation m m 1 Affected flag s Z DECA m Decrement Data Memory with result in ACC Description Data in...

Page 105: ...m ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation The result is stored in the Accumulator Operation ACC ACC OR m Affected flag s Z OR A ...

Page 106: ...a Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 m 7 Affected flag s None RLC m Rotate Data Memory left through Carry Description The contents of the specified Data Memory...

Page 107: ...ract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or zero the C flag will be set to 1 Operation ACC ACC m C Affected flag s OV ...

Page 108: ...e program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped The result is stored in the Accumulator but the specified Data Memory contents remain unchanged As t...

Page 109: ...re interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetched it ...

Page 110: ...d the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation The result is stored in the Accumulator Operation ACC ACC XOR m Affected flag s Z XORM A m Logical XOR ACC to Data Memory Description Data in ...

Page 111: ...intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Package Information include Outline Dimensions Product Tape and Reel Specifications The Operation Instruction of Packing Material...

Page 112: ...sions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 020 C 0 193 BSC D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 00 BSC B 3 90 BSC C 0 31 0 51 C 4 90 BSC D 1 75 E 1 27 BSC F 0 10 0 25 G 0 40 1 27 H 0 10 0 25 α 0 8 ...

Page 113: ...0 028 0 030 0 031 A1 0 000 0 001 0 002 A3 0 080 BSC b 0 007 0 010 0 012 D 0 118 BSC E 0 118 BSC e 0 020 BSC D2 0 087 0 091 0 093 E2 0 061 0 065 0 067 L 0 012 0 016 0 020 K 0 008 Symbol Dimensions in mm Min Nom Max A 0 700 0 750 0 800 A1 0 000 0 020 0 050 A3 0 203 BSC b 0 180 0 250 0 300 D 3 000 BSC E 3 000 BSC e 0 500 BSC D2 2 200 2 300 2 350 E2 1 550 1 650 1 700 L 0 300 0 400 0 450 K 0 200 ...

Page 114: ...0 043 A1 0 000 0 006 A2 0 030 0 033 0 037 B 0 007 0 013 C 0 003 0 009 D 0 118 BSC E 0 193 BSC E1 0 118 BSC e 0 020 BSC L 0 016 0 024 0 031 L1 0 037 BSC y 0 004 θ 0 8 Symbol Dimensions in mm Min Nom Max A 1 10 A1 0 00 0 15 A2 0 75 0 85 0 95 B 0 17 0 33 C 0 08 0 23 D 3 00 BSC E 4 90 BSC E1 3 00 BSC e 0 50 BSC L 0 40 0 60 0 80 L1 0 95 BSC y 0 10 θ 0 8 ...

Page 115: ...nsions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 020 C 0 390 BSC D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 00 BSC B 3 90 BSC C 0 31 0 51 C 9 90 BSC D 1 75 E 1 27 BSC F 0 10 0 25 G 0 40 1 27 H 0 10 0 25 α 0 8 ...

Page 116: ...used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek reser...

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