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Holtek BS83A02L Manual Download Page 113

Rev. 1.10

112

March 02, 2020

Rev. 1.10

113

March 02, 2020

BS83A02L/BS83B04L

Ultra-Low Power Touch Key Flash MCU

BS83A02L/BS83B04L

Ultra-Low Power Touch Key Flash MCU

a STOP signal to release the I

2

C Bus. The corresponding data will be stored in the IICD register. 

If setup as a transmitter, the slave device must first write the data to be transmitted into the IICD 
register. If setup as a receiver, the slave device must read the transmitted data from the IICD register.
When the slave receiver receives the data byte, it must generate an acknowledge bit, known as 
TXAK, on the 9th clock. The slave device, which is setup as a transmitter will check the RXAK bit 
in the IICC1 register to determine if it is to send another data byte, if not then it will release the SDA 
line and await the receipt of a STOP signal from the master.

Start

SCL

SDA

SCL

SDA

1

S=Start (1 bit)

SA=Slave Address (7 bits)

SR=SRW bit (1 bit)

M=Slave device send acknowledge bit (1 bit)

D=Data (8 bits)

A=ACK (RXAK bit for transmitter, TXAK bit for receiver, 1 bit)

P=Stop (1 bit)

0

ACK

Slave Address

SRW

Stop

Data

ACK

1

1

0

1

0

1

0

1

0

0

1

0

1

0

0

S SA SR M D A D A

……

S SA SR M D A D A

……

P

I

2

C Communication Timing Diagram

Note: When a slave address is matched, the device must be placed in either the transmit mode and 

then write data to the IICD register, or in the receive mode where it must implement a dummy 

read from the IICD register to release the SCL line.

Summary of Contents for BS83A02L

Page 1: ...Ultra Low Power Touch Key Flash MCU BS83A02L BS83B04L Revision V1 10 Date March 02 2020 ...

Page 2: ...aracteristics 13 A C Characteristics 14 High Speed Internal Oscillator HIRC Frequency Accuracy 14 Low Speed Internal Oscillator Characteristics LIRC 15 Operating Frequency Characteristic Curves 15 System Start Up Time Characteristics 15 Input Output Characteristics 16 Memory Characteristics 17 LVR Electrical Characteristics 17 Power on Reset Characteristics 17 System Architecture 18 Clocking and P...

Page 3: ...rite Protection 33 EEPROM Interrupt 33 Programming Considerations 34 Oscillators 35 Oscillator Overview 35 System Clock Configurations 35 Internal High Speed RC Oscillator HIRC 36 Internal 2kHz Oscillator LIRC 36 Operating Modes and System Clocks 37 System Clocks 37 System Operation Modes 38 Control Registers 39 Operating Mode Switching 40 Standby Current Considerations 43 Wake up 44 Watchdog Time...

Page 4: ...ey Function BS83A02L 77 Touch Key Structure 77 Touch Key Register Definition 77 Touch Key Operation 85 Touch Key Scan Operation Flowchart 88 Touch Key Interrupts 90 Programming Considerations 90 Touch Key Function BS83B04L 91 Touch Key Structure 91 Touch Key Register Definition 91 Touch Key Operation 99 Touch Key Data Memory 103 Touch Key Scan Operation Flowchart 104 Touch Key Interrupts 105 Progr...

Page 5: ... Transferring Data 128 Arithmetic Operations 128 Logical and Rotate Operation 129 Branches and Control Transfer 129 Bit Operations 129 Table Read Operations 129 Other Operations 129 Instruction Set Summary 130 Table Conventions 130 Instruction Definition 132 Package Information 141 6 pin DFN 2mm 2mm 0 35mm Outline Dimensions 142 6 pin DFN 2mm 2mm 0 75mm Outline Dimensions 143 6 pin SOT23 6 Outline...

Page 6: ...nipulation instruction Peripheral Features Flash Program Memory 1K 14 RAM Data Memory 64 8 2 touch key functions fully integrated without requiring external components Watchdog Timer function 4 bidirectional I O lines Single external interrupt line shared with I O pin Single 8 bit programmable Timer Event Counter with overflow interrupt and prescaler Single Time Base function for generation of fix...

Page 7: ... means of implementing Touch Keyes within their products applications The touch key functions are fully integrated completely eliminating the need for external components In addition to the flash program memory other memory includes an area of RAM Data Memory as well as an area of true EEPROM memory for storage of non volatile data such as serial numbers calibration data etc Protective features su...

Page 8: ...evices exist in more than one package format the table reflects the situation for the package with the most pins Block Diagram BS83A02L Bus MUX Reset Circuit Stack 2 level RAM 64 8 ROM 1K 14 Watchdog Timer Port A Driver VDD HIRC 8MHz LIRC 2kHz Timer Pin Shared Function PA0 PA3 Clock System Digital Peripherals HT8 MCU Core Time Base I O VSS Interrupt Controller VDD VSS INT Pin Shared With Port A Pi...

Page 9: ...T SCL ICPDA PA6 CTCK INT PA7 CTP 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 OCDSCK NC NC NC NC VSS VDD PA0 INT ICPDA OCDSDA NC NC NC NC PA1 KEY1 PA3 KEY2 PA2 TC ICPCK BS83AV02L 16 NSOP A NC PA6 CTCK INT BS83BV04L 16 NSOP A 16 15 14 13 12 11 10 9 1 2 3 4 5 6 7 8 VDD PA5 KEY1 PA1 KEY2 PA3 KEY3 PA4 KEY4 OCDSCK NC PA0 CTCK INT SCL ICPDA PA2 CTPB SDA ICPCK PA7 CTP OCDSDA NC NC VSS Note 1 If the pin shared ...

Page 10: ...T ICPDA PA0 PAPU PAWU ST CMOS General purpose I O Register enabled pull up and wake up INT ST External interrupt input ICPDA ST CMOS ICP data address PA1 KEY1 PA1 PAPU PAWU PAS0 ST CMOS General purpose I O Register enabled pull up and wake up KEY1 PAS0 AN Touch key input PA2 TC ICPCK PA2 PAPU PAWU ST CMOS General purpose I O Register enabled pull up and wake up TC ST Timer Event Counter external c...

Page 11: ...rpose I O Register enabled pull up and wake up KEY3 PAS0 AN Touch key input PA4 KEY4 PA4 PAPU PAWU PAS1 ST CMOS General purpose I O Register enabled pull up and wake up KEY4 PAS1 AN Touch key input PA5 KEY1 PA5 PAPU PAWU PAS1 ST CMOS General purpose I O Register enabled pull up and wake up KEY1 PAS1 AN Touch key input PA6 CTCK INT PA6 PAPU PAWU ST CMOS General purpose I O Register enabled pull up ...

Page 12: ...uence on the measured values Note that the 2MHz or 4MHz operating frequency is used for the BS83B04L only Operating Voltage Characteristics Ta 40 C 85 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Operating Voltage HIRC fSYS fHIRC 2MHz 1 8 5 5 V fSYS fHIRC 4MHz 1 8 5 5 fSYS fHIRC 8MHz 1 8 5 5 Operating Voltage LIRC fSYS fLIRC 2kHz 1 8 5 5 V Operating Current Characteristics Ta 40 C 85 C ...

Page 13: ...y Current values are taken after a HALT instruction execution thus stopping all instruction execution BS83B04L Ta 25 C Symbol Standby Mode Test Conditions Min Typ Max Unit VDD Conditions ISTB SLEEP Mode 1 8V WDT on 90 150 nA 3V 90 150 5V 160 320 SLEEP Mode 1 Key Wake up 3V WDT on fSUB on 150 250 nA IDLE0 Mode LIRC 1 8V fSUB on 1 2 2 4 μA 3V 1 5 3 0 5V 2 5 5 0 IDLE1 Mode HIRC 1 8V fSUB on fSYS 2MHz...

Page 14: ...VDD range operating voltage It is recommended that the trim voltage is fixed at 3V for application voltage ranges from 1 8V to 3 6V and fixed at 5V for application voltage ranges from 3 3V to 5 5V BS83B04L Symbol Parameter Test Conditions Min Typ Max Unit VDD Temp fHIRC 2MHz Writer Trimmed HIRC Frequency 3V 5V 25 C 1 2 1 MHz 40 C 85 C 4 2 4 2 2V 5 5V 25 C 6 2 6 40 C 85 C 7 2 7 1 8V 5 5V 25 C 10 2 ...

Page 15: ... 85 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions tSST System Start up Time Wake up from condition where fSYS is off fSYS fH fH 64 fH fHIRC 16 tHIRC fSYS fSUB fLIRC 2 tLIRC System Start up Time Wake up from condition where fSYS is on fSYS fH fH 64 fH fHIRC 2 tH fSYS fSUB fLIRC 2 tSUB System Speed Switch Time FAST to SLOW Mode or SLOW to FAST Mode fHIRC switches from off on 16 ...

Page 16: ...t for I O Pins BS83A02L 1 8V VOL 0 1VDD 2 5 5 0 mA 3V 5 10 5V 10 20 Sink Current for I O Pins BS83B04L 3V VOL 0 1VDD 16 32 mA 5V 32 65 IOH Source Current for I O Pins BS83A02L 1 8V VOH 0 9VDD 1 5 2 0 mA 3V 4 5 5V 8 10 Source Current for I O Pins BS83B04L 3V VOH 0 9VDD 4 8 mA 5V 8 16 ILEAK Input Leakage Current 5V VIN VDD or VIN VSS 1 μA RPH Pull high Resistance for I O Ports Note 3V LVPU 0 For BS8...

Page 17: ...0K tRETD ROM Data Retention time Ta 25 C 40 Year RAM Data Memory VDR RAM Data Retention Voltage Device in SLEEP Mode 1 0 V LVR Electrical Characteristics Ta 40 C 85 C Symbol Parameter Test Conditions Min Typ Max Unit VDD Conditions VLVR Low Voltage Reset Voltage LVR enable voltage is 1 7V 5 1 7 5 V ILVR Operating Current 3V LVR enable VLVR 1 7V 15 μA 5V 15 25 tLVR Minimum Low Voltage Width to Rese...

Page 18: ...tions Clocking and Pipelining The main system clock derived from either an HIRC or LIRC oscillator is subdivided into four internally generated non overlapping clocks T1 T4 The Program Counter is incremented at the beginning of the T1 clock during which time a new instruction is fetched The remaining T2 T4 clocks carry out the decoding and execution functions In this way one T1 T4 clock cycle form...

Page 19: ... into this register a short program jump can be executed directly however as only this low byte is available for manipulation the jumps are limited to the present page of memory that is 256 locations When such program jumps are executed it should also be noted that a dummy cycle will be inserted Manipulating the PCL register may cause program branching so an extra cycle is needed to pre fetch Stac...

Page 20: ...DCM SUB SUBM SBC SBCM DAA Logic operations AND OR XOR ANDM ORM XORM CPL CPLA Rotation RRA RR RRCA RRC RLA RL RLCA RLC Increment and Decrement INCA INC DECA DEC Branch decision JMP SZ SZA SNZ SIZ SDZ SIZA SDZA CALL RET RETI Flash Program Memory The Program Memory is the location where the user code or program is stored For these devices the Program Memory is Flash type which means it can be program...

Page 21: ...able The TBHP table pointer register is used for the BS83B04L only After setting up the table pointer the table data can be retrieved from the Program Memory using the TABRD m or TABRDL m instructions respectively When the instruction is executed the lower order table byte from the Program Memory will be transferred to the user defined Data Memory register m as specified in the instruction The hig...

Page 22: ...in situations where simultaneous use cannot be avoided the interrupts should be disabled prior to the execution of any main routine table read instructions Note that all table related instructions require two instruction cycles to complete their operation Table Read Program Example tempreg1 db temporary register 1 tempreg2 db temporary register 2 mov a 06h initialise low table pointer note that th...

Page 23: ...DS There are EV chips named BS83AV02L and BS83BV04L which are used to emulate the real MCU devices named BS83A02L and BS83B04L respectively The EV chip devices also provide an On Chip Debug function to debug the real MCU devices during the development process The EV chips and the real MCU devices are almost functionally compatible except for On Chip Debug function and package type Users can use th...

Page 24: ... Data Memory reserved for the Touch Key Data Memory Structure The overall Data Memory is subdivided into several banks The Special Purpose Data Memory registers are accessible in bank 0 with the exception of the EEC register at address 40H which is accessible in Bank 1 For the BS83B04L the Touch Key Data Memory is located in Bank 5 Bank 7 Switching among the different Data Memory banks is achieved...

Page 25: ...mporary data can be stored and retrieved for use later It is this area of RAM memory that is known as General Purpose Data Memory This area of Data Memory is fully accessible by the user programing for both reading and writing operations By using the bit operation instructions individual bits can be set or reset under program control giving the user a large range of flexibility for bit manipulatio...

Page 26: ...0 TKM0C1 TKM0C0 TKM0ROH TKM0ROL TKM016DH TKM016DL TKC1 TK16DH TK16DL TKC0 TKTMR TKM0C2 TKC2 TD5 TMR TMRC TD2 20H 21H 22H 23H 24H 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 39H 38H 3BH 3AH 3DH 3CH 3FH 33H 34H 35H 36H 37H 3EH TD3 Bank 0 Bank 0 SCC WDTC TKM0K2CNTH TBLH HIRCC INTEG INTC1 LVRC LVPUC PSC0R TD1 TK1M0TH16H TK1M0TH16L TK2M0TH16H TK2M0TH16L TKM0K1ROCH TKM0K1ROCL TKM0K2ROCH TKM0...

Page 27: ... 43H 44H 45H 46H 47H 48H 49H 4AH 4BH 4CH 4DH 4EH 4FH 50H 51H 52H 59H 58H 5BH 5AH 5DH 5CH 5FH 53H 54H 55H 56H 57H 5EH 60H 61H 62H 69H 68H 6BH 6AH 6DH 6CH 6FH 6EH 63H 64H 65H 66H 67H 70H 71H 72H 78H 7CH 73H 74H 75H 76H 77H 7BH 79H 7AH 7DH 7FH 7EH Bank 0 Bank 0 00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 19H 18H 1BH 1AH 1DH 1CH 1FH 13H 14H 15H 16H 17H 1EH 20H 21H 22H 2...

Page 28: ...only Memory Pointers MP0 MP1 Two Memory Pointers known as MP0 and MP1 are provided These Memory Pointers are physically implemented in the Data Memory and can be manipulated in the same way as normal registers providing a convenient way with which to address and track data When any operation to the relevant Indirect Addressing Registers is carried out the actual address that the microcontroller is...

Page 29: ... storage function of the Accumulator for example when transferring data between one user defined register and another it is necessary to do this by passing the data through the Accumulator as no direct transfer between two registers is permitted Program Counter Low Register PCL To provide additional program control functions the low byte of the Program Counter is made accessible to programmers by ...

Page 30: ...m the high nibble into the low nibble in subtraction otherwise AC is cleared Z is set if the result of an arithmetic or logical operation is zero otherwise Z is cleared OV is set if an operation results in a carry into the highest order bit but not a carry out of the highest order bit or vice versa otherwise OV is cleared PDF is cleared by a system power up or executing the CLR WDT instruction PDF...

Page 31: ...r Capacity Address 32 8 00H 1FH EEPROM Data Memory Structure The EEPROM Data Memory capacity varies from 32 8 bits according to the device selected Unlike the Program Memory and RAM Data Memory the EEPROM Data Memory is not directly mapped into memory space and is therefore not directly addressable in the same way as the other types of memory Read and Write operations to the EEPROM are carried out...

Page 32: ...ata EEPROM Write Control Bit and when set high by the application program will activate a write cycle This bit will be automatically reset to zero by the hardware after the write cycle has finished Setting this bit high will have no effect if the WREN has not first been set high Bit 1 RDEN Data EEPROM Read Enable 0 Disable 1 Enable This is the Data EEPROM Read Enable Bit which must be set high bef...

Page 33: ...n set As the EEPROM write cycle is controlled using an internal timer whose operation is asynchronous to microcontroller system clock a certain time will elapse before the data will have been written into the EEPROM Detecting when the write cycle has finished can be implemented either by polling the WR bit in the EEC register or by using the EEPROM interrupt When the write cycle terminates the WR ...

Page 34: ...y complete Otherwise the EEPROM read or write operation will fail Programming Examples Reading data from the EEPROM polling method MOV A EEPROM_ADRES user defined address MOV EEA A MOV A 040H setup memory pointer MP1 MOV MP1 A MP1 points to EEC register MOV A 01H setup Bank Pointer MOV BP A SET IAR1 1 set RDEN bit enable read operations SET IAR1 0 start Read Cycle set RD bit BACK SZ IAR1 0 check f...

Page 35: ...nd slow system clock the devices have the flexibility to optimize the performance power ratio a feature especially important in power sensitive portable applications Device Type Name Frequency BS83A02L Internal High Speed RC HIRC 8MHz Internal Low Speed RC LIRC 2kHz BS83B04L Internal High Speed RC HIRC 2 4 8MHz Internal Low Speed RC LIRC 2kHz Oscillator Types System Clock Configurations There are ...

Page 36: ...so be setup to match the selected configuration option frequency Setting up these bits is necessary to ensure that the HIRC frequency accuracy specified in the A C Characteristics is achieved Device trimming during the manufacturing process and the inclusion of internal frequency compensation circuits are used to ensure that the influence of the power supply voltage temperature and process variati...

Page 37: ...r programming a clock system can be configured to obtain maximum application performance The main system clock can come from either a high frequency fH or low frequency fSUB source and is selected using the CKS2 CKS0 bits in the SCC register The high speed system clock is sourced from the HIRC oscillator The low speed system clock source can be sourced from the LIRC oscillator The other choice whi...

Page 38: ...ng modes where the microcontroller has all of its functions operational and where the system clock is provided by one of the high speed oscillators This mode operates allowing the microcontroller to operate normally with a clock source will come from HIRC oscillator The high speed oscillator will however first be divided by a ratio ranging from 1 to 64 the actual ratio being selected by the CKS2 C...

Page 39: ...S2 CKS1 CKS0 FHIDEN FSIDEN HIRCC BS83A02L HIRCF HIRCEN HIRCC BS83B04L HIRC1 HIRC0 HIRCF HIRCEN System Operating Mode Control Register List SCC Register Bit 7 6 5 4 3 2 1 0 Name CKS2 CKS1 CKS0 FHIDEN FSIDEN R W R W R W R W R W R W POR 0 0 0 0 0 Bit 7 5 CKS2 CKS0 System clock selection 000 fH 001 fH 2 010 fH 4 011 fH 8 100 fH 16 101 fH 32 110 fH 64 111 fSUB These three bits are used to select which ...

Page 40: ...he A C characteristics Bit 1 HIRCF HIRC oscillator stable flag 0 HIRC unstable 1 HIRC stable This bit is used to indicate whether the HIRC oscillator is stable or not When the HIRCEN bit is set to 1 to enable the HIRC oscillator the HIRCF bit will first be cleared to 0 and then set to 1 after the HIRC oscillator is stable Bit 0 HIRCEN HIRC oscillator enable control 0 Disable 1 Enable Operating Mod...

Page 41: ...m oscillator and therefore consumes more power the system clock can switch to run in the SLOW Mode by set the CKS2 CKS0 bits to 111 in the SCC register This will then use the low speed system oscillator which will consume less power Users may decide to do this for certain operations which do not require high performance and can subsequently reduce power consumption The SLOW Mode is sourced from th...

Page 42: ...the device to enter the SLEEP Mode and that is to execute the HALT instruction in the application program with both the FHIDEN and FSIDEN bits in the SCC register equal to 0 In this mode all the clocks and functions will be switched off except the WDT function When this instruction is executed under the conditions described above the following will occur The system clock will be stopped and the ap...

Page 43: ...s described above the following will occur The fH clock will be on but the fSUB clock will be off and the application program will stop at the HALT instruction The Data Memory contents and registers will maintain their present condition The I O ports will maintain their present conditions In the status register the Power Down flag PDF will be set and the Watchdog time out flag TO will be cleared T...

Page 44: ...hdog Timer reset will be initiated and the TO flag will be set to 1 The TO flag is set if a WDT time out occurs and causes a wake up that only resets the Program Counter and Stack Pointer other flags remain in their original status Each pin on Port A can be setup using the PAWU register to permit a negative transition on the pin to wake up the system When a Port A pin wake up occurs the program wi...

Page 45: ...peration WDTC Register Bit 7 6 5 4 3 2 1 0 Name WE4 WE3 WE2 WE1 WE0 WS2 WS1 WS0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 0 1 1 Bit 7 3 WE4 WE0 WDT function software control 01010 10101 Enable Other values Reset MCU When these bits are changed to any other values due to environmental noise the microcontroller will be reset this reset operation will be activated after a delay time tSRESET a...

Page 46: ...ting a reset This is done using the clear watchdog instruction If the program malfunctions for whatever reason jumps to an unknown location or enters an endless loop the clear instruction will not be executed in the correct manner in which case the Watchdog Timer will overflow and reset the device There are five bits WE4 WE0 in the WDTC register to offer the enable and reset control of the Watchdo...

Page 47: ... ready to execute the first program instruction After this power on reset certain important internal registers will be set to defined states before the program commences One of these registers is the Program Counter which will be reset to zero forcing the microcontroller to begin program execution from the lowest Program Memory address In addition to the power on reset another reset exists in the ...

Page 48: ...STC3 RSTC2 RSTC1 RSTC0 R W R W R W R W R W R W R W R W R W POR 0 1 0 1 0 1 0 1 Bit 7 0 RSTC7 RSTC0 Reset function control 01010101 No operation 10101010 No operation Other values Reset MCU If these bits are changed due to adverse environmental conditions the microcontroller will be reset The reset operation will be activated after a delay time tSRESET and the RSTF bit in the RSTFC register will be...

Page 49: ...anged to some different values by environmental noise the LVR will reset the device after a delay time tSRESET When this happens the LRF bit in the RSTFC register will be set high After power on the register will have the value of 01011010B For the BS83B04L the LVR function is always enabled in the FAST or SLOW mode with a specific LVR voltage VLVR which is fixed at 1 7V Note that the LVR function...

Page 50: ...tion program Bit 0 WRF WDT control register software reset flag Refer to the Watchdog Timer Control Register section RSTFC Register BS83B04L Bit 7 6 5 4 3 2 1 0 Name RSTF LVRF WRF R W R W R W R W POR 0 x 0 x Unknown Bit 7 4 Unimplemented read as 0 Bit 3 RSTF Reset control register software reset flag Describe elsewhere Bit 2 LVRF LVR function reset flag 0 Not occur 1 Occurred This bit is set to 1 ...

Page 51: ...ents of the microcontroller are affected after a power on reset occurs Item Condition after Reset Program Counter Reset to zero Interrupts All interrupts will be disabled WDT Time Base Clear after reset WDT begins counting Timers Timers will be turned off Input Output Ports I O ports will be setup as inputs Stack Pointer Stack Pointer will point to the top of the stack The different kinds of reset...

Page 52: ... 0 0 0 0 0 0 u u u u u u LVRC 0 1 0 1 1 0 1 0 u u u u u u u u 0 1 0 1 1 0 1 0 u u u u u u u u LVPUC 0 0 0 u PA 1 1 1 1 1 1 1 1 1 1 1 1 u u u u 1111 1111 1111 1111 1111 1111 u u u u u u u u PAC 1 1 1 1 1 1 1 1 1 1 1 1 u u u u 1111 1111 1111 1111 1111 1111 u u u u u u u u PAPU 0 0 0 0 0 0 0 0 0 0 0 0 u u u u 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u PAWU 0 0 0 0 0 0 0 0 0 0 0 0...

Page 53: ...K2ROCH 0 0 0 0 0 0 u u TKM0K1CNTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM0K1CNTH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM0K2CNTL 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM0K2CNTH 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM0TH16L 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 u u u u u u u u TKM...

Page 54: ...eds of a wide range of application possibilities The device provides bidirectional input output lines labeled with a port name PA The I O port is mapped to the RAM Data Memory with specific addresses as shown in the Special Purpose Data Memory table The I O port can be used for input and output operations For input operation the port is non latching which means the inputs must be ready at the T2 r...

Page 55: ...Name PAPU3 PAPU2 PAPU1 PAPU0 R W R W R W R W R W POR 0 0 0 0 Bit 7 4 Unimplemented read as 0 Bit 3 0 PAPU3 PAPU0 PA3 PA0 pull high function control 0 Disable 1 Enable PAPU Register BS83B04L Bit 7 6 5 4 3 2 1 0 Name PAPU7 PAPU6 PAPU5 PAPU4 PAPU3 PAPU2 PAPU1 PAPU0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 PAPU7 PAPU0 PA7 PA0 pull high function control 0 Disable 1 Enable LVPUC R...

Page 56: ...trol register known as PAC it controls the input output configuration With this control register each I O pin with or without pull high resistors can be reconfigured dynamically under software control For the I O pin to function as an input the corresponding bit of the control register must be written as a 1 This will then allow the logic state of the input pin to be directly read by instructions ...

Page 57: ...IFS which can select the desired functions of the multi function pin shared pins The most important point to note is to make sure that the desired pin shared function is properly selected and also deselected For most pin shared functions to select the desired pin shared function the pin shared function should first be correctly selected using the corresponding pin shared control register After tha...

Page 58: ...R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 PAS07 PAS06 PA3 Pin Shared function selection 00 01 10 PA3 11 KEY3 Bit 5 4 PAS05 PAS04 PA2 Pin Shared function selection 00 01 PA2 10 CTPB 11 SDA Bit 3 2 PAS03 PAS02 PA1 Pin Shared function selection 00 01 10 PA1 11 KEY2 Bit 1 0 PAS01 PAS00 PA0 Pin Shared function selection 00 01 10 PA0 CTCK INT 11 SCL PAS1 Register BS83B04L Bit 7 6 5 4 3 2 1 0 Name PAS17 PAS16 ...

Page 59: ...nction Input Output Structure Programming Considerations Within the user program one of the things first to consider is port initialisation After a reset all of the I O data and port control registers will be set high This means that all I O pins will be defaulted to an input state the level of which depends on the other connected circuitry and whether pull high selections have been chosen If the ...

Page 60: ... Base Interrupt section for details on the fPSC clock 8 bit Timer Event Counter Timer Event Counter Input Clock Source The Timer Event Counter clock source can originate from various sources an internal clock or an external pin The internal clock source is used when the timer is in the Timer Mode and Pulse Width Measurement Mode For the Timer Event Counter this internal clock source is the divided...

Page 61: ...ler Timer Event Counter are implemented by operating in three different modes the options of which are determined by the contents of control register bits The Timer Control Register is known as TMRC It is the Timer Control Register together with its corresponding timer register that controls the full operation of the Timer Event Counter Before the timer can be used it is essential that the Timer C...

Page 62: ...me the Timer Event Counter overflows When operating in this mode the internal clock is used as the timer clock The internal clock source is from the Prescaler and is selected by the TPSC2 TPSC0 bits in the TMRC register The timer on bit TON must be set high to enable the timer to run Each time an internal clock high to low transition occurs the timer increases by one When the timer reaches its max...

Page 63: ... TC pin If the active Edge Selection bit TEG is low once a high to low transition has been received on the TC pin the Timer Event Counter will start counting based on the internal selected clock source until the TC pin returns to its original high level At this point the enable bit will be automatically reset to zero and the Timer Event Counter will stop counting If the Active Edge Selection bit i...

Page 64: ...ister the clock is inhibited to avoid errors however as this may result in a counting error it should be taken into account by the programmer Care must be taken to ensure that the timers are properly initialised before using them for the first time The associated timer interrupt enable bit in the interrupt control register must be properly set otherwise the internal interrupt associated with the t...

Page 65: ...value is then compared with the value of pre programmed internal comparators When the free running counter has the same value as the pre programmed comparator known as a compare match situation a TM interrupt signal will be generated which can clear the counter and perhaps also change the condition of the TM output pin The internal TM counter is driven by a user selectable clock source which can b...

Page 66: ... all have a low and high byte structure The high bytes can be directly accessed but as the low bytes can only be accessed via an internal 8 bit buffer reading or writing to these register pairs must be carried out in a specific way The important point to note is that data transfer to and from the 8 bit buffer and its related low byte only takes place when a write or read operation to its correspon...

Page 67: ...Clear 0 1 Output Control Polarity Control Pin Control CTP CTOC CTM1 CTM0 CTIO1 CTIO0 CTMAF Interrupt CTMPF Interrupt CTPOL PASn CCRA CTCCLR fSUB CTPB Note CTPB is the inverted output of CTP Compact Type TM Block Diagram Compact TM Operation At its core is a 10 bit count up counter which is driven by a user selectable internal or external clock source There are also two internal comparators with th...

Page 68: ...a Pause condition the CTM will remain powered up and continue to consume power The counter will retain its residual value when this bit changes from low to high and resume counting from this value when the bit changes to a low value again Bit 6 4 CTCK2 CTCK0 Select CTM Counter clock 000 fSYS 4 001 fSYS 010 fH 16 011 fH 64 100 fSUB 101 fSUB 110 CTCK rising edge clock 111 CTCK falling edge clock The...

Page 69: ...o zero is in effect allowing the counter to overflow at its maximum value CTMC1 Register Bit 7 6 5 4 3 2 1 0 Name CTM1 CTM0 CTIO1 CTIO0 CTOC CTPOL CTDPX CTCCLR R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 6 CTM1 CTM0 Select CTM Operating Mode 00 Compare Match Output Mode 01 Undefined 10 PWM Output Mode 11 Timer Counter Mode These bits setup the required operating mode for the CTM ...

Page 70: ...n the Compare Match Output Mode or in the PWM Output Mode It has no effect if the CTM is in the Timer Counter Mode In the Compare Match Output Mode it determines the logic level of the CTM output pin before a compare match occurs In the PWM Output Mode it determines if the PWM signal is active high or active low Bit 2 CTPOL CTM CTP Output polarity control 0 Non invert 1 Invert This bit controls th...

Page 71: ...0 CTM 10 bit CCRA bit 9 bit 8 Compact Type TM Operating Modes The Compact Type TM can operate in one of three operating modes Compare Match Output Mode PWM Output Mode or Timer Counter Mode The operating mode is selected using the CTM1 and CTM0 bits in the CTMC1 register Compare Match Output Mode To select this mode bits CTM1 and CTM0 in the CTMC1 register should be set to 00 respectively In this ...

Page 72: ... in the CTMC1 register The CTM output pin can be selected using the CTIO1 and CTIO0 bits to go high to go low or to toggle from its present condition when a compare match occurs from Comparator A The initial condition of the CTM output pin which is setup after the CTON bit changes from low to high is setup using the CTOC bit Note that if the CTIO1 and CTIO0 bits are zero then no pin change will ta...

Page 73: ...lect Output not affected by CTMAF flag Remains High until reset by CTON bit Output Pin Reset to Initial value Output controlled by other pin shared function Output Inverts when CTPOL is high CTMPF not generated No CTMAF flag generated on CCRA overflow Output does not change CTCCLR 1 CTM 1 0 00 CCRA Int Flag CTMAF CCRP Int Flag CTMPF Compare Match Output Mode CTCCLR 1 Note 1 With CTCCLR 1 a Compara...

Page 74: ...orm one register is used to clear the internal counter and thus control the PWM waveform frequency while the other one is used to control the duty cycle Which register is used to control either frequency or duty cycle is determined using the CTDPX bit in the CTMC1 register The PWM waveform frequency and duty cycle can therefore be controlled by the values in the CCRA and CCRP registers An interrup...

Page 75: ...WM Duty Cycle set by CCRA PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRP CTM O P Pin CTOC 0 CCRA Int Flag CTMAF CCRP Int Flag CTMPF CTDPX 0 CTM 1 0 10 PWM Output Mode CTDPX 0 Note 1 Here CTDPX 0 Counter cleared by CCRP 2 A counter clear sets PWM Period 3 The internal PWM function continues running even when CTIO 1 0 00 or 01 ...

Page 76: ...t low Counter Reset when CTON returns high PWM Duty Cycle set by CCRP PWM resumes operation Output controlled by other pin shared function Output Inverts when CTPOL 1 PWM Period set by CCRA CTM O P Pin CTOC 0 CTDPX 1 CTM 1 0 10 PWM Output Mode CTDPX 1 Note 1 Here CTDPX 1 Counter cleared by CCRA 2 A counter clear sets PWM Period 3 The internal PWM function continues even when CTIO 1 0 00 or 01 4 Th...

Page 77: ...unter low byte TK16DH Touch key function 16 bit counter high byte TKM016DL Touch key module 0 16 bit C F counter low byte TKM016DH Touch key module 0 16 bit C F counter high byte TKM0ROL Touch key module 0 reference oscillator capacitor selection low byte TKM0ROH Touch key module 0 reference oscillator capacitor selection high byte TKM0C0 Touch key module 0 control register 0 TKM0C1 Touch key modu...

Page 78: ...TKM0K1CNTL D7 D6 D5 D4 D3 D2 D1 D0 TKM0K1CNTH D15 D14 D13 D12 D11 D10 D9 D8 TKM0K2CNTL D7 D6 D5 D4 D3 D2 D1 D0 TKM0K2CNTH D15 D14 D13 D12 D11 D10 D9 D8 TKMTHS M0K2THF M0K1THF M0K2THS M0K1THS Touch Key Function Register List TKTMR Register Bit 7 6 5 4 3 2 1 0 Name D7 D6 D5 D4 D3 D2 D1 D0 R W R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 0 Bit 7 0 D7 D0 Touch key time slot 8 bit counter preload ...

Page 79: ...ro during the auto scan operation period Only at the end of the last scan operation in the WDT time out cycle the 16 bit C F counter content will be written into the TKM0KnCNTH TKM0KnCNTL registers and then the TKRCOV bit will be set high by the hardware circuit The other actions in this mode are the same as those in the auto scan mode except the above mentioned In the manual scan mode if the time...

Page 80: ...alue is less than the lower threshold if M0KnTHS 0 or larger than the upper threshold if M0KnTHS 1 the TKTH signal will be set high The other actions in this mode are the same as those in the auto scan mode except the above mentioned Bit 0 TKBUSY Touch key scan operation busy flag 0 Not busy no scan operation is executed or scan operation is completed 1 Busy scan operation is executing This bit in...

Page 81: ...s TK16DH TK16DL Touch Key Function 16 bit Counter Register Pair Register TK16DH TK16DL Bit 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 Name D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 R W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key function 16 bit counter value This 16 bit counter can be used to calibrate the reference or key ...

Page 82: ... as 0 Bit 5 M0DFEN Touch key module 0 multi frequency control 0 Disable 1 Enable This bit is used to control the touch key oscillator frequency doubling function When this bit is set to 1 the key oscillator frequency will be doubled Bit 4 Unimplemented read as 0 Bit 3 M0SOFC Touch key module 0 C F oscillator frequency hopping function control selection 0 Controlled by the M0SOF2 M0SOF0 1 Controlle...

Page 83: ...bit from low to high if the reference oscillator is selected to be used and will be disabled when the TKBUSY bit is changed from high to low Bit 4 M0KOEN Touch key module 0 key oscillator control 0 Disable 1 Enable This bit is used to enable the touch key module 0 key oscillator In the auto scan mode or the periodic auto scan mode the key oscillator will automatically be enabled by setting the M0K...

Page 84: ...the 16 bit C F counter content TKM016DH TKM016DL will be compared with the TKnM0TH16H TKnM0TH16L value by the hardware When this value is less than the the lower threshold if M0KnTHS 0 or larger than the upper threshold if M0KnTHS 1 then the M0KnTHF flag will be set high and an interrupt signal will be generated TKM0KnROCH TKM0KnROCL Touch Key Module 0 KEYn Reference Oscillator Capacitor Selection...

Page 85: ...omparison 1 Upper threshold comparison Bit 0 M0K1THS Touch key module 0 KEY1 upper or lower threshold comparison selection 0 Lower threshold comparison 1 Upper threshold comparison Touch Key Operation When a finger touches or is in proximity to a touch pad the capacitance of the pad will increase By using this capacitance variation to change slightly the frequency of the internal sense oscillator ...

Page 86: ...counter 5 bit time slot unit period counter and 8 bit time slot timer counter will be automatically switched off when the time slot counter overflows The clock source for the time slot counter is sourced from the reference oscillator or fLIRC which is selected using the M0TSS bit in the TKM0C1 register The reference oscillator and key oscillator will be enabled by setting the M0ROEN bit and M0KOEN...

Page 87: ...Mode In addition to those actions mentioned in the auto scan mode the periodic auto scan mode provides periodic auto scan and C F counter upper lower threshold comparison functions When the TKMOD1 TKMOD0 bits are set to 10 or 11 the periodic auto scan mode is selected to scan the module keys automatically and periodically Note that this mode is generally used in the IDLE mode in order to monitor t...

Page 88: ...L Register Array Touch Key Register Allocation Touch Key Scan Operation Flowchart Start Write Ref OSC Capacitor value to TKM0ROH TKM0ROL Touch Key Manual Scan Operation Start Set Start bit TKST 0 1 Busy flag TKBUSY 1 All Time Slot Counter overflow TKRCOV 0 Initiate Time Slot 16 bit C F Counter All Time Slot 16 bit C F Counter start to count Time Slot 16 bit C F Counter keep counting TKRCOV 1 Touch...

Page 89: ...Slot 16 bit C F Counter All Time Slot counter 16 bit C F counter start to count Time Slot 16 bit C F Counter keep counting Yes TKRCOV 1 Generate Interrupt request flag Read C F counter value from TKM0KnCNTH TKM0KnCNTL Touch key scan end Set TKST bit 1 0 End Load Ref OSC internal Capacitor value from TKM0KnROCH TKM0KnROCL Store C F counter value to TKM0KnCNTH TKM0KnCNTL All key scan finish Yes No T...

Page 90: ...The TKRCOV flag which is the time slot counter flag will go high when the counter overflows in the manual scan mode When this happens an interrupt signal will be generated In the auto scan mode if the time slot counter overflows but the touch key auto scan operation is not completed the TKRCOV bit will not be set When the touch key auto scan operation is completed the TKRCOV bit and the Touch Key ...

Page 91: ...t 8 bit counter preload register TKC0 Touch key function control register 0 TKC1 Touch key function control register 1 TKC2 Touch key function control register 2 TK16DL Touch key function 16 bit counter low byte TK16DH Touch key function 16 bit counter high byte TKM016DL Touch key module 0 16 bit C F counter low byte TKM016DH Touch key module 0 16 bit C F counter high byte TKM0ROL Touch key module...

Page 92: ... TKC0 Register Bit 7 6 5 4 3 2 1 0 Name TKRAMC TKRCOV TKST TKCFOV TK16OV TKMOD1 TKMOD0 TKBUSY R W R W R W R W R W R W R W R W R POR 0 0 0 0 0 0 1 0 Bit 7 TKRAMC Touch key data memory access control 0 Accessed by MCU 1 Accessed by touch key module This bit determines that the touch key data memory is used by the MCU or the touch key module However the touch key module will have the priority to acce...

Page 93: ...er 5 bit time slot unit period counter and 8 bit time slot counter will be automatically switched off Bit 5 TKST Touch key detection start control 0 Stopped or no operation 0 1 Start detection The touch key module 0 16 bit C F counter touch key function 16 bit counter and 5 bit time slot unit period counter will automatically be cleared when this bit is cleared to zero However the 8 bit programmab...

Page 94: ...s cleared to 0 automatically when the touch key time slot counter overflows In the auto scan mode this bit is cleared to 0 automatically when the touch key scan operation is completed In the periodic auto scan mode this bit is cleared to 0 automatically when the last scan operation in the WDT time out cycle is completed or when any key C F counter value is less than the lower threshold if M0KnTHS ...

Page 95: ...D3 D2 D1 D0 R W R R R R R R R R R R R R R R R R POR 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 This register pair is used to store the touch key function 16 bit counter value This 16 bit counter can be used to calibrate the reference or key oscillator frequency When the touch key time slot counter overflows in the manual scan mode this 16 bit counter will be stopped and the counter content will be unchanged ...

Page 96: ...control the touch key oscillator frequency doubling function When this bit is set to 1 the key oscillator frequency will be doubled Bit 4 Unimplemented read as 0 Bit 3 M0SOFC Touch key module 0 C F oscillator frequency hopping function control selection 0 Controlled by the M0SOF2 M0SOF0 1 Controlled by hardware circuit This bit is used to select the touch key oscillator frequency hopping function ...

Page 97: ... the reference oscillator is selected as the time slot clock source The combination of the M0TSS and M0K4EN M0K1EN bits determines whether the reference oscillator is used or not When the TKBUSY bit is changed from high to low the M0ROEN bit will automatically be cleared to zero to disable the reference oscillator In the manual scan mode the reference oscillator should first be enabled before sett...

Page 98: ...he settings for these bits are invalid when TKMOD1 TKMOD0 01 or TSC 1 Bit 1 0 M0SK01 M0SK00 Touch key module 0 time slot 0 key scan select 00 KEY1 01 KEY2 10 KEY3 11 KEY4 These bits are used to select the desired scan key in time slot 0 in the auto scan mode or the periodic auto scan mode or used as the multiplexer for scan key select in the manual mode TKM0TH16H TKM0TH16L Touch Key Module 0 16 bi...

Page 99: ...an upper threshold 1 Less than lower threshold or larger than upper threshold Bit 3 M0K4THS Touch key module 0 KEY4 upper or lower threshold comparison selection 0 Lower threshold comparison 1 Upper threshold comparison Bit 2 M0K3THS Touch key module 0 KEY3 upper or lower threshold comparison selection 0 Lower threshold comparison 1 Upper threshold comparison Bit 1 M0K2THS Touch key module 0 KEY2 ...

Page 100: ...key module 0 16 bit C F counter 16 bit counter 5 bit time slot unit period counter in the module will be automatically cleared when the TKST bit is cleared to zero but the 8 bit programmable time slot counter will not be cleared The overflow time is setup by user When the TKST bit changes from low to high the 16 bit C F counter 16 bit counter 5 bit time slot unit period counter and 8 bit time slot...

Page 101: ...are set to 00 the auto scan mode is selcted to scan the module keys in a specific sequence determined by the M0SK3 1 0 M0SK0 1 0 bits in the TKM0C2 register The TSC bit in the TKC2 register is used to configure time slot TKST Module 0 Time slot 0 Time slot 1 Time slot 2 Time slot 3 TKBUSY TKRCOV Clear to zero by software Time slot 1 Time slot 2 Time slot 3 Touch Key Data Memory Access Set Touch Ke...

Page 102: ...tor value for the next selected key will be read from the touch key data memory and loaded into the TKM0ROH TKM0ROL registers Then the 16 bit C F counter value of the current scanned key will be written into the corresponding touch key data memory The whole auto scan operation will sequentially be carried out in the above specific way from time slot 0 to time slot 3 At the end of the time slot 3 k...

Page 103: ...0 or larger than the upper threshold if M0KnTHS 1 this indicates that the touch key state changes then the M0KnTHF flag will be set high by the hardware and an interrupt signal will be generated Note that if the touch key threshold TKTH interrupt occurs 1 byte data will be written to the TKM0ROL register because the TKM0ROH TKM0ROL register pair will be loaded with the corresponding next time slot...

Page 104: ...art Set Start bit TKST 0 1 Busy flag TKBUSY 1 All Time Slot Counter overflow TKRCOV 0 Initiate Time Slot 16 bit C F Counter All Time Slot 16 bit C F Counter start to count Time Slot 16 bit C F Counter keep counting TKRCOV 1 Touch key busy flag TKBUSY 0 Generate Interrupt request flag Read C F counter value from TKM016DH TKM016DL Touch key scan end Set TKST bit 1 0 End Touch Key Manual Scan Mode Fl...

Page 105: ...t key Touch Key Auto Scan Mode Flowchart Touch Key Interrupts The touch key has two independent interrupts known as touch key TKRCOV interrupt and touch key threshold TKTH interrupt In the manual scan mode when the touch key module 0 time slot counter overflows an actual touch key TKRCOV interrupt will take place In the auto scan mode when the touch key auto scan operation is completed the Touch K...

Page 106: ...n threshold comparison condition occurs When this happens an interrupt signal will also be generated As the TKRCOV flag will not be automatically cleared it has to be cleared by the application program The TKCFOV flag which is the 16 bit C F counter overflow flag will go high when any of the Touch Key Module 0 16 bit C F counter overflows As this flag will not be automatically cleared it has to be...

Page 107: ...ernal pull high register could be controlled by its corresponding pull high control register Shift Register Transmit Receive Control Unit fSYS fSUB Data Bus I2 C Address Register IICA I2 C Data Register IICD Address Comparator Read Write Slave SRW Detect Start or Stop HBB Time out Control IICTOF Address Match HAAS I2 C Interrupt Debounce Circuitry SCL Pin M U X TXAK Data out MSB IICTOEN Address Ma...

Page 108: ...S HBB HTX TXAK SRW IAMWU RXAK IICD D7 D6 D5 D4 D3 D2 D1 D0 IICA IICA6 IICA5 IICA4 IICA3 IICA2 IICA1 IICA0 IICTOC IICTOEN IICTOF IICTOS5 IICTOS4 IICTOS3 IICTOS2 IICTOS1 IICTOS0 I2 C Register List I2 C Data Register The IICD register is used to store the data being transmitted and received Before the device writes data to the I2 C bus the actual data to be transmitted must be placed in the IICD regi...

Page 109: ... 0 Bit 7 4 Unimplemented read as 0 Bit 3 2 IICDEB1 IICDEB0 I2 C Debounce Time Selection 00 No debounce 01 2 system clock debounce 10 11 4 system clock debounce Note that the I2 C debounce circuit will operate normally if the system clock fSYS is derived from the fH clock or the IAMWU bit is equal to 0 Otherwise the debounce circuit will have no effect and be bypassed Bit 1 IICEN I2 C Enable Contro...

Page 110: ...g 1 Slave do not send acknowledge flag The TXAK bit is the transmit acknowledge flag After the slave device receipt of 8 bits of data this bit will be transmitted to the bus on the 9th clock from the slave device The slave device must always set TXAK bit to 0 before further data is received Bit 2 SRW I2 C Slave Read Write flag 0 Slave device should be in receive mode 1 Slave device should be in tr...

Page 111: ...and an I2 C interrupt will be generated After entering the interrupt service routine the slave device must first check the condition of the HAAS and IICTOF bits to determine whether the interrupt source originates from an address match or from the completion of an 8 bit data transfer completion or from the I2 C bus time out occurrence During a data transfer note that after the 7 bit slave address ...

Page 112: ...ster to release the SCL line I2 C Bus Read Write Signal The SRW bit in the IICC1 register defines whether the master device wishes to read data from the I2 C bus or write data to the I2 C bus The slave device should examine this bit to determine if it is to be a transmitter or a receiver If the SRW flag is 1 then this indicates that the master device wishes to read data from the I2 C bus therefore...

Page 113: ... RXAK bit in the IICC1 register to determine if it is to send another data byte if not then it will release the SDA line and await the receipt of a STOP signal from the master Start SCL SDA SCL SDA 1 S Start 1 bit SA Slave Address 7 bits SR SRW bit 1 bit M Slave device send acknowledge bit 1 bit D Data 8 bits A ACK RXAK bit for transmitter TXAK bit for receiver 1 bit P Stop 1 bit 0 ACK Slave Addre...

Page 114: ... C Bus ISR Flowchart I2 C Time out Control In order to reduce the problem of I2 C lockup due to reception of erroneous clock sources a time out function is provided If the clock source to the I2 C is not received for a while then the I2 C circuitry and registers will be reset after a certain time out period The time out counter starts counting on an I2 C bus START address match condition and is cl...

Page 115: ... into the following condition Registers After I2 C Time out IICD IICA IICC0 No change IICC1 Reset to POR condition I2 C Registers after Time out The IICTOF flag can be cleared by the application program There are 64 time out periods which can be selected using IICTOS bit field in the IICTOC register The time out time is given by the formula 1 64 32 fSUB This gives a time out period which ranges fr...

Page 116: ...ich setup the primary interrupts the second is the MFI0 MFI1 registers which setup the Multi function interrupts Finally there is an INTEG register to setup the external interrupt trigger edge type Each register contains a number of enable bits to enable or disable individual registers as well as interrupt flags to indicate the presence of an interrupt request The naming convention of these follow...

Page 117: ...VE INTE EMI R W R W R W R W R W R W R W R W POR 0 0 0 0 0 0 0 Bit 7 Unimplemented read as 0 Bit 6 TKTHF Touch key threshold TKTH interrupt request flag 0 No request 1 Interrupt request Bit 5 TKRCOVF Touch key TKRCOV interrupt request flag 0 No request 1 Interrupt request Bit 4 INTF INT interrupt request flag 0 No request 1 Interrupt request Bit 3 TKTHE Touch key threshold TKTH interrupt control 0 ...

Page 118: ...st Bit 3 MF1E Multi function interrupt 1 control 0 Disable 1 Enable Bit 2 MF0E Multi function interrupt 0 control 0 Disable 1 Enable Bit 1 INTE INT interrupt control 0 Disable 1 Enable Bit 0 EMI Global interrupt control 0 Disable 1 Enable INTC1 Register BS83A02L Bit 7 6 5 4 3 2 1 0 Name TBF TF TBE TE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 TBF Time Base interrupt requ...

Page 119: ...ed read as 0 Bit 2 DEE Data EEPROM interrupt control 0 Disable 1 Enable Bit 1 TBE Time Base interrupt control 0 Disable 1 Enable Bit 0 I2CE I2 C interrupt control 0 Disable 1 Enable MFI0 Register BS83B04L Bit 7 6 5 4 3 2 1 0 Name TKTHF TKRCOVF TKTHE TKRCOVE R W R W R W R W R W POR 0 0 0 0 Bit 7 6 Unimplemented read as 0 Bit 5 TKTHF Touch key threshold TKTH interrupt request flag 0 No request 1 Int...

Page 120: ...which will be the value of the corresponding interrupt vector The microcontroller will then fetch its next instruction from this interrupt vector The instruction at this vector will usually be a JMP which will jump to another section of program which is known as the interrupt service routine Here is located the code to control the appropriate interrupt The interrupt service routine must be termina...

Page 121: ... EMI auto disabled in ISR Priority High Low Interrupts contained within Multi Function Interrupts Interrupt Name Request Flags Enable Bits Touch Key TKRCOV TKRCOVF TKRCOVE Touch Key Threshold TKTH TKTHF TKTHE CTM P CTMPF CTMPE CTM A CTMAF CTMAE Time Base TBF TBE EMI 14H 10H I2 C I2CF I2CE EMI 0CH EMI MF1F MF1E M Funct 1 08H MF0F MF0E EMI M Funct 0 04H INT Pin INTF INTE EMI xxE Enable Bits xxF Requ...

Page 122: ...t DEE must first be set When the interrupt is enabled the stack is not full and an EEPROM Write cycle ends a subroutine call to the respective interrupt vector will take place When the EEPROM Write Interrupt is serviced the DEF flag will be automatically cleared and the EMI bit will also be automatically cleared to disable other interrupts Timer Event Counter Interrupt An actual Timer Event Counte...

Page 123: ...SYS 4 or fSUB and then passes through a divider the division ratio of which is selected by programming the appropriate bits in the TBC register to obtain longer interrupt periods whose value ranges The clock source which in turn controls the Time Base interrupt period is selected using the CLKSEL1 CLKSEL0 bits in the PSCR register M U X fSYS 4 fSYS fSUB Prescaler CLKSEL 1 0 fPSC fPSC 28 fPSC 215 M...

Page 124: ...st first be set When the interrupt is enabled the stack is not full and the touch key time slot counter overflows or all the scan operations are completed a subroutine call to its interrupt vector will take place When the interrupt is serviced the Touch Key TKRCOV Interrupt request flag TKRCOVF will be automatically cleared The EMI bit will also be automatically cleared to disable other interrupts...

Page 125: ... are set a situation which occurs when a TM comparator P or A match situation happens To allow the program to branch to its respective interrupt vector address the global interrupt enable bit EMI respective TM Interrupt enable bit and relevant Multi function Interrupt enable bit MFnE must first be set When the interrupt is enabled the stack is not full and a TM comparator match situation occurs a ...

Page 126: ... altered by the interrupt service program their contents should be saved to the memory at the beginning of the interrupt service routine To return from an interrupt subroutine either a RET or RETI instruction may be executed The RETI instruction in addition to executing a return to the main program also automatically sets the EMI bit high to allow further interrupts The RET instruction however onl...

Page 127: ...Touch Key Flash MCU Application Circuits VDD VSS VDD 0 1μF PA3 KEY2 PAD PA1 KEY1 PAD PA0 INT ICPDA PA2 TC ICPCK BS83A02L VDD VSS VDD 0 1μF PA3 KEY3 PA4 KEY4 PAD PAD PA5 KEY1 PA1 KEY2 PAD PAD PA2 CTPB SDA ICPCK PA0 CTCK INT SCL ICPDA PA7 CTP PA6 CTCK INT BS83B04L ...

Page 128: ...more cycle to implement As instructions which change the contents of the PCL will imply a direct jump to that new address one more cycle will be required Examples of such instructions would be CLR PCL or MOV PCL A For the case of skip instructions it must be noted that if the result of the comparison involves a skip operation then this will also take one more cycle if no skip is involved then only...

Page 129: ...branch instructions are the conditional branches Here a decision is first made regarding the condition of a certain data memory or individual bits Depending upon the conditions the program will continue with the next instruction or skip over it and jump to the following instruction These instructions are the key to decision making and branching within the program perhaps determined by the conditio...

Page 130: ...ry 1Note Z C AC OV DAA m Decimal adjust ACC for Addition with result in Data Memory 1Note C Logic Operation AND A m Logical AND Data Memory to ACC 1 Z OR A m Logical OR Data Memory to ACC 1 Z XOR A m Logical XOR Data Memory to ACC 1 Z ANDM A m Logical AND ACC to Data Memory 1Note Z ORM A m Logical OR ACC to Data Memory 1Note Z XORM A m Logical XOR ACC to Data Memory 1Note Z AND A x Logical AND imm...

Page 131: ...e RET A x Return from subroutine and load immediate data to ACC 2 None RETI Return from interrupt 2 None Table Read Operation TABRD m Read table specific page or current page to TBLH and Data Memory 2Note None TABRDL m Read table last page to TBLH and Data Memory 2Note None Miscellaneous NOP No operation 1 None CLR m Clear Data Memory 1Note None SET m Set Data Memory 1Note None CLR WDT Clear Watch...

Page 132: ...umulator and the specified immediate data are added The result is stored in the Accumulator Operation ACC ACC x Affected flag s OV Z AC C ADDM A m Add ACC to Data Memory Description The contents of the specified Data Memory and the Accumulator are added The result is stored in the specified Data Memory Operation m ACC m Affected flag s OV Z AC C AND A m Logical AND Data Memory to ACC Description D...

Page 133: ...he TO PDF flags and the WDT are all cleared Operation WDT cleared TO 0 PDF 0 Affected flag s TO PDF CLR WDT1 Pre clear Watchdog Timer Description The TO PDF flags and the WDT are all cleared Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect Repetitively executing this instruction without alternately executing CLR WDT2 will h...

Page 134: ...d by this instruction which indicates that if the original BCD sum is greater than 100 it allows multiple precision decimal addition Operation m ACC 00H or m ACC 06H or m ACC 60H or m ACC 66H Affected flag s C DEC m Decrement Data Memory Description Data in the specified Data Memory is decremented by 1 Operation m m 1 Affected flag s Z DECA m Decrement Data Memory with result in ACC Description Da...

Page 135: ...tion m ACC Affected flag s None NOP No operation Description No operation is performed Execution continues with the next instruction Operation No operation Affected flag s None OR A m Logical OR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation The result is stored in the Accumulator Operation ACC ACC OR m Affected flag s Z ...

Page 136: ...e Data Memory left with result in ACC Description The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit 0 The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged Operation ACC i 1 m i i 0 6 ACC 0 m 7 Affected flag s None RLC m Rotate Data Memory left through Carry Description The contents of the specified Data M...

Page 137: ... Subtract Data Memory from ACC with Carry Description The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator The result is stored in the Accumulator Note that if the result of subtraction is negative the C flag will be cleared to 0 otherwise if the result is positive or zero the C flag will be set to 1 Operation ACC ACC m C Affected flag ...

Page 138: ... 0 the program proceeds with the following instruction Operation m m 1 Skip if m 0 Affected flag s None SIZA m Skip if increment Data Memory is zero with result in ACC Description The contents of the specified Data Memory are first incremented by 1 If the result is 0 the following instruction is skipped The result is stored in the Accumulator but the specified Data Memory contents remain unchanged...

Page 139: ...ory are interchanged The result is stored in the Accumulator The contents of the Data Memory remain unchanged Operation ACC 3 ACC 0 m 7 m 4 ACC 7 ACC 4 m 3 m 0 Affected flag s None SZ m Skip if Data Memory is 0 Description If the contents of the specified Data Memory is 0 the following instruction is skipped As this requires the insertion of a dummy instruction while the next instruction is fetche...

Page 140: ...ry and the high byte moved to TBLH Operation m program code low byte TBLH program code high byte Affected flag s None XOR A m Logical XOR Data Memory to ACC Description Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation The result is stored in the Accumulator Operation ACC ACC XOR m Affected flag s Z XORM A m Logical XOR ACC to Data Memory Description Dat...

Page 141: ...ular intervals users are reminded to consult the Holtek website for the latest version of the Package Carton Information Additional supplementary information with regard to packaging is listed below Click on the relevant section to be transferred to the relevant website page Package Information include Outline Dimensions Product Tape and Reel Specifications The Operation Instruction of Packing Mat...

Page 142: ... Min Nom Max A 0 012 0 014 0 016 A1 0 000 0 001 0 002 A3 0 005 BSC b 0 010 0 012 0 014 D 0 079 BSC E 0 079 BSC e 0 026 BSC D2 0 053 0 055 0 057 E2 0 022 0 024 0 026 L 0 010 0 012 0 014 K 0 008 Symbol Dimensions in mm Min Nom Max A 0 30 0 35 0 40 A1 0 00 0 02 0 05 A3 0 127 BSC b 0 25 0 30 0 35 D 2 00 BSC E 2 00 BSC e 0 65 BSC D2 1 35 1 40 1 45 E2 0 55 0 60 0 65 L 0 25 0 30 0 35 K 0 20 ...

Page 143: ...ax A 0 028 0 030 0 031 A1 0 000 0 001 0 002 A3 0 008 BSC b 0 010 0 012 0 014 D 0 079 BSC E 0 079 BSC e 0 026 BSC D2 0 053 0 055 0 057 E2 0 022 0 024 0 026 L 0 010 0 012 0 014 K 0 008 Symbol Dimensions in mm Min Nom Max A 0 700 0 750 0 800 A1 0 000 0 020 0 050 A3 0 200 BSC b 0 250 0 300 0 350 D 2 00 BSC E 2 00 BSC e 0 65 BSC D2 1 350 1 400 1 450 E2 0 550 0 600 0 650 L 0 250 0 300 0 350 K 0 200 ...

Page 144: ...s in inch Min Nom Max A 0 057 A1 0 006 A2 0 035 0 045 0 051 b 0 012 0 020 C 0 003 0 009 D 0 114 BSC E 0 063 BSC e 0 037 BSC e1 0 075 BSC H 0 110 BSC L1 0 024 BSC θ 0 8 Symbol Dimensions in mm Min Nom Max A 1 45 A1 0 15 A2 0 90 1 15 1 30 b 0 30 0 50 C 0 08 0 22 D 2 90 BSC E 1 60 BSC e 0 95 BSC e1 1 90 BSC H 2 80 BSC L1 0 60 BSC θ 0 8 ...

Page 145: ...Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 020 C 0 193 BSC D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 00 BSC B 3 90 BSC C 0 31 0 51 C 4 90 BSC D 1 75 E 1 27 BSC F 0 10 0 25 G 0 40 1 27 H 0 10 0 25 α 0 8 ...

Page 146: ...ax A 0 028 0 030 0 031 A1 0 000 0 001 0 002 A3 0 080 BSC b 0 007 0 010 0 012 D 0 118 BSC E 0 118 BSC e 0 020 BSC D2 0 087 0 091 0 093 E2 0 061 0 065 0 067 L 0 012 0 016 0 020 K 0 008 Symbol Dimensions in mm Min Nom Max A 0 700 0 750 0 800 A1 0 000 0 020 0 050 A3 0 203 BSC b 0 180 0 250 0 300 D 3 000 BSC E 3 000 BSC e 0 500 BSC D2 2 200 2 300 2 350 E2 1 550 1 650 1 700 L 0 300 0 400 0 450 K 0 200 ...

Page 147: ...ax A 0 043 A1 0 000 0 006 A2 0 030 0 033 0 037 B 0 007 0 013 C 0 003 0 009 D 0 118 BSC E 0 193 BSC E1 0 118 BSC e 0 020 BSC L 0 016 0 024 0 031 L1 0 037 BSC y 0 004 θ 0 8 Symbol Dimensions in mm Min Nom Max A 1 10 A1 0 00 0 15 A2 0 75 0 85 0 95 B 0 17 0 33 C 0 08 0 23 D 3 00 BSC E 4 90 BSC E1 3 00 BSC e 0 50 BSC L 0 40 0 60 0 80 L1 0 95 BSC y 0 10 θ 0 8 ...

Page 148: ... Dimensions Symbol Dimensions in inch Min Nom Max A 0 236 BSC B 0 154 BSC C 0 012 0 020 C 0 390 BSC D 0 069 E 0 050 BSC F 0 004 0 010 G 0 016 0 050 H 0 004 0 010 α 0 8 Symbol Dimensions in mm Min Nom Max A 6 00 BSC B 3 90 BSC C 0 31 0 51 C 9 90 BSC D 1 75 E 1 27 BSC F 0 10 0 25 G 0 40 1 27 H 0 10 0 25 α 0 8 ...

Page 149: ... are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise Holtek s products are not authorized for use as critical components in life support devices or systems Holtek ...

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