HT98R068-1 Two-way Radio OTP MCU
PLL Control Flow - for MCU
Flow description:
<Set … PLL>: Setup the PLL divider and PLL enable.
<Delay10ms>: Delay 10ms which is to wait the PLL to stabilise.
<CLKMOD=0>: Set the MCU to be in the PLL mode.
Controlling Audio Processor
Audio Processor Reset
After the PLL is setup, the next step is to enable the audio processor by setting the
CTRL2 [4] bit, which is the audio processor reset signal control bit. Use a 1
0
1
sequence, which drives POR=0. Also do not set CTRL[4]= 1 when configuring the PLL.
After a reset, it is necessary to wait for 200ms~300ms (f
SYS
_Audo=16MHz
(Note)
) before
sending the control command. This waiting perios is for the audio processor internal
initialisation, including RAM initialisation, ADC, DAC ...etc. Any SPI commands during
this period will be invalid as shown below:
5