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HT98R068-1 Two-way Radio OTP MCU

In-band Signal Level Adjustment Function

The output modulation differs between different system applications. The device provides

multi-level modulating settings for different paths and also provides a mixer. The

modulation diagram and description are as follows:

Modulation Path Block Diagram



VR1: The internal audio generator modulation level select (I/O CMD-11h [4-2: b’010]),

256 levels. Default: 00h.



VR2: Sub-tone modulation level select, 256 levels. Defaul: 00h.



VR3: Mixer modulation option/setting. When VR3=0, it means no MIX function, 256

levels. Default: 00h.



VR4: The MOD (pin) in-band output modulation select, 1024 levels. Default: 3FFh.



VR5: The SMOD (pin) sub-tone output modulation select, 1024 levels. Default: 3FFh.

The MOD output depends on the VR1 setting (if a tone generator is used), VR4 and the

system operating voltages. The SMOD output depends on VR2, VR5 and the system

operating voltages. However, there may be some distortion in the actual output (RC

filter etc.). For example, in a 3V system, MOD Output (max) ~= 2780mv, SMOD Output

(max) ~= 1920mv due to the default value of the audio processor. Users must enable or

change the path modulation level for their application.

In the high frequency modulation mechanism TX mode, CTCSS and DCS always

seperate the signals to access so that the digital signal of the DCS high and low fast

changing can be processed efficiently. The device ouput by using the same SMOD pin, so

the mixer mechanism is designed specially for output the DCS to be modulated by the

MOD signal. The generic method is that the CTCSS sub-audio is output by SMOD and

VR3 is disabled (CLI CMD-04D2h=0000h). The CTCSS signal is determined by VR2 and

VR5. However, the DCS signal is output by MOD mixed with the audio signal. VR3 is

enabled and has a numerical value to scale while VR5 is diabled (CLI CMD-04D5=0000h)

or it’s OK to disable the DAC2 output. At this time, the DCS is determined by VR2 and

VR3. All are aiming at taking advantages of the TX DCS function. Note that: Whether the

system can applicate in this way or not is depending on the actual condition.

Ex: Operating voltage = 3V, setup and enable the maximum modulation of the sub-audio

path, VR5 = default (3FFh):

Summary of Contents for AN0305E

Page 1: ...le descramble VOX etc transmitted to the other port by a radio frequency carrier Using the code to mark the product extended series but it s still avalible in this text such as the HT98R068 1 Operating Principles Sub tone CTCSS encode decode DCS encode decode In band tone processor DTMF encode decode Selective call tone EEA standard In band tone user define Other signals DCS turn off tone Advanced...

Page 2: ...provides selectable audio and modulation signal input such as MICO AUX BEEP1 and DEMI Output unit MOD SMOD The signal output port includes MODO for the in band signal output and SMODO for the sub tone signal output can use this port if you want to decode sub tone Output unit Audio The audio output port with selective DAC1 and BEEP0 multiplexer outputs MCU unit The MCU control unit is applied to co...

Page 3: ...e input signal must be limited in signal PGA amplification ratio VDD 0 7 AD maximum MOD SMOD AUDO In band sub tone audio output port The MOD output can generate in band signals connected to the RF input port The SMOD generates sub tone signals to be applied in applications requiring sub tones AUDO The audio signals after demodulation can generate tones through a LPF circuit connected to the speake...

Page 4: ...rol Register 0 CTRL0 Bit 7 6 5 4 3 2 1 0 CTRL0 PCFG PFDCS PFDC LXTLP CLKMOD POR 0 0 0 0 1 The CTRL0 0 bit selects the MCU high speed mode If CTRL0 0 1 the MCU operates in the low speed mode 32 768kHz If CTRL0 0 0 the MCU operates in the PLL mode When using the PLL mode it is important to note that when the PLL is enabled the PLL ascending frequency ratio MCU and audio processor divider ratio must ...

Page 5: ...xt step is to enable the audio processor by setting the CTRL2 4 bit which is the audio processor reset signal control bit Use a 1 0 1 sequence which drives POR 0 Also do not set CTRL 4 1 when configuring the PLL After a reset it is necessary to wait for 200ms 300ms fSYS_Audo 16MHz Note before sending the control command This waiting perios is for the audio processor internal initialisation includi...

Page 6: ...t sequence is 1 0 1 with two nope instructions in between Delay This is the audio processor initial time Any SPI data transmitted during this period may be overwritten by the audio processor and become invalid which may waste 250ms 300ms Audio Processor Turn on Timing Note fSYS_Audo is audio processor fSYS Audio processor Turn on Timing 6 ...

Page 7: ...frequencies are 16MHz and 150kHz When designing it s recommended that the frequency should be less than 150kHz that the SPI receive and transmit program can be shared The I O command is applied in some application areas such as for circuit control sharing data etc marked as I O CMD NNh in this document The CLI Control layer interface command can access the audio processor related parameters such a...

Page 8: ...e in a Don t Care condition during a read command execution A7 A0 are the register addresses D7 D0 are the access datas Write I O CMD Master write SPI 19 16 SPI 15 8 SPI 7 0 4 b1000 Address A7 A0 Data D7 D0 Audio processor reply SPI 19 16 SPI 15 8 SPI 7 0 x No signal x No signal x No signal Read I O CMD Master Write SPI 19 16 SPI 15 8 SPI 7 0 4 b1001 Address A7 A0 x Don t care Audio processor repl...

Page 9: ...ad Write 14181 14082 must be correct so that the audio processor will continue to receive successive data When the data is written the audio processor will reply with 14000 which means that the data is correctly written otherwise it means no data written Write CLI CMD Master Write CLI_CMD Major Minor Multi Length 4 b0001 4 b0100 4 b0000 4 b1000 4 b0010 4 b0001 Address 15 0 4 b0001 Data 15 0 Audio ...

Page 10: ...ter No data response will be provided 1FFFF Set the data FFFFh Write data to the register A data response of 14000 means that it is correctly written otherwise it means that no data has been correctly written Read 04CBh Flow Flow description 14181 The CLI read ID code To execute a read operation with the CLI command it is necessary to execute this command first No data response will be provided 10...

Page 11: ...r functions at this time SPICK MOSI MISO SPISS SPIRQ SPICR 7 1 SPICR 3 SPICR 2 SPICR 1 SPICR 4 SPICR 0 SPICR 7 0 PC6 PC4 PA5 PC7 PC5 SPI Control Signal Table Points to note when using external control when required to reduce the PLL frequency or entering the sleep mode when the SPI is returned to the internal MCU control Usable pins decrease When 1 or 2 problems of those described above occurs it ...

Page 12: ...lied in a radio walkie talkie application the ON OFF circuit and function for different modes are different as well as the ON OFF timing Switch to the correct input or output source and disable any unnecessary circuits so as to save power and eliminate interference among signals Note that turning on the circuit needs a stable time according to the circuit it is usually about 250ms except that the ...

Page 13: ...or after the signal is identified as shown below IDLE Mode Setup Flow Flow description When there is no output or input signal are waiting to be processed the audio processor can be disabled After it s enabled operating can be restarted without needing re initialise 81E3F Enable the audio circuit power supply or select to enable the needed circuit only 851FA Enable the audio processor pulse freque...

Page 14: ...F path select mode switch so as to decrease the generation of error signals The following illustrates the PTT processing Ex Setup the TX mode Input MIC Output MOD No Sub tone Tx Mode Setup Flow Flow description 81E97 Enable the DDAC1 AMP1 MIC and PGA circuits Setup the circuit switch first DAC1 AMP1 on enable the MOD output MIC on enable the microphone circuit PGA on enable the PGA input source 81...

Page 15: ... SPI command settings are as follows Ex RX mode Input DEMOD Output AUDO source DAC1 No Sub tone RX Mode Setup Flow Flow description RSSI OK Confirm if the RF signal is OK 81E8B Enable the DAC1 buffer and PGA circuits Setup the circuit switches first DAC1 on enable DAC1 output AUDO output buffer on enable the audio output circuit PGA on enable the PGA input source 81B25 Select the PGA and audio inp...

Page 16: ...on and is used as an interrupt request The main interrupt source must be enabled I O CMD 22h 6 1 This application does not need to use a polling method Managing after the interrupt generation makes the MCU more efficient The format description is as follows Event Interrupt Mask 22h Address Bit 7 6 5 4 3 2 1 0 Name IRQ DTMF INT Selective call INT CTCSS INT DCS INT Off_Tone INT VOX INT Audio Process...

Page 17: ...rrupt enabled selection Select the CTCSS interrupt enable the interrupt source Flow description 2 Is received 10008 Confirm this interrupt signal is CTCSS event 92300 Poll event status Flow description 3 Is received 92308 Confirm this interrupt signal is approved by CTCSS 92308 or don t decode CTCSS 92300 correctly 17 ...

Page 18: ...ff tone the I O CMD 30h 0 1 this status will be remained because it is belong to respective decode so we must load I O CMD 12000 and make it reset sub audio tail tone decoding detection set I O CMD 30h 0 0 or I O CMD 23h 1 0 Hence take it to consider that at the moment decoding the tail tone it excutes the command immediately when designing Internal Audio Function In the open public radio system s...

Page 19: ...MD 04E0 04FF If the comparision is successful locate the decoding frequency channel number in I O CMD 2Eh 3 0 and set the status bit I O CMD 23h 4 In addition note that the threshold setting when decoding the generally accepted threshold is CLI CMD 0324 and the published threshold is CLI CMD 0325 They respectively control the decoding low value and the non decoding high value which are described a...

Page 20: ...DAO2 are DAC common mode bias voltage 81168 Enter Rx mode Select RX mode and enable in band audio selective call function Is Selective event Acknowledge that the signal a steady frenquency in the selective call frequency channel list 92E00 Read the selective call detection data Read the frenquency channel of this selective call detection data Save SelCal finder Store the number after detection Sto...

Page 21: ...hannel number in the I O CMD 2Fh 3 0 and set the status bit I O CMD 23h 5 In addition there is a power threshold CLI CMD 01C4 It selects the minimum amplitude one of the two frequencies as the measurement standard which is described in the following note Ex RX mode Input MOD DTMF tone 00h Set DTMF TX Mode Flow Flow description 82D00 Select DTMF channel Select DTMF zeroth group frenquency channel 8...

Page 22: ...noise DAO1 and DAO2 are DAC common mode bias voltage 81170 Enter the TX mode Select the TX mode and enable the in band audio DTMF function Is DTMF event Acknowledge that the signal a steady frenquency in the DTM frequency channel list 92F00 Read the DTMF detection data Read the frenquency channel of this DTMF detection data Save DTMF finder Store the number after detection Store this number data t...

Page 23: ... the same as the setup channel The table below provides relevant table and design descriptions Tone number CTCSS freq Hz Tone number CTCSS freq Hz Tone number CTCSS freq Hz 01h 67 12h 123 23h 225 7 02h 71 9 13h 127 3 24h 233 6 03h 74 4 14h 131 8 25h 241 8 04h 77 15h 136 5 26h 250 3 05h 79 7 16h 141 3 27h 69 3 06h 82 5 17h 146 2 28h 62 5 07h 85 4 18h 151 4 29h 159 8 08h 88 5 19h 156 7 2Ah 165 5 09h...

Page 24: ...ow Flow description 82B01 Setup the sub tone channel by selecting the first group of the CTCSS channel 81E37 Enable the DAC1 DAC2 AMP1 AMP2 MIC and PGA circuits DAC1 AMP1 on enable the MOD output DAC2 AMP2 on enable the SMOD output MIC on enable the microphone circuit PGA on enable the PGA input source 81B10 Select the PGA and audio input source locations Select the PGA input source to be MIC and ...

Page 25: ...oise 81162 Enter the RX mode Select the RX mode and enable the Sub tone CTCSS function Is CTCSS event To be confirmed that the signal has the CTCSS sub tone of the same channel 81E8B Enable the DAC1 buffer and PGA circuits DAC1 on and enable the DAC1 output AUDO output buffer on and enable the audio output circuit PGA on and enable the PGA input source 81B25 Select the PGA and audio input source p...

Page 26: ...mation some systems provide this function to disable the audio output The related configuration is shown in the table below Tone Number DCS Code Tone Number DCS Code Tone Number DCS Code Tone Number DCS Code Inverted Tone Number DCS Code Inverted Tone Number DCS Code Inverted 01h 023 1Dh 174 39h 445 81h 023 9Dh 174 B9h 445 02h 025 1Eh 205 3Ah 464 82h 025 9Eh 205 BAh 464 03h 026 1Fh 223 3Bh 465 83h...

Page 27: ... by selecting the first DCS channel group 81E37 Enable the DAC1 DAC2 AMP1 AMP2 and PGA circuits DAC1 AMP1 on enable the MOD output DAC2 AMP2 on enable the SMOD output PGA on enable the PGA input source 81B10 Select the PGA and audio input source paths Select the PGA input source to be AUX with the audio out to be DAC common mode bias voltage to reduce noise 81142 Enter the TX mode Select the TX mo...

Page 28: ...DCS and return to the standby status Ex RX mode No audio tone signal DCS sub tone AUDO sources DAC1 DAC2 off MIC off DCS tone 01h All are implemented using interrupts IRQs in this example When a DCS event interrupt is received add an additional command to read the I O CMD 23h for event status judgment DCS RX Mode Setup Flow 1 RF Signal Detection 2 Audio Processor IRQ Management 28 ...

Page 29: ... 10004 Confirm the interrupt is the DCS sub tone signal of the same channel 92300 Check again the event status Confirm the DCS status is 1 or 0 Flow description 3 Is DCS event To be confirmed that the signal contains a DCS sub tone of same channel 81E8B Enable the DAC1 Buffer PGA circuits DAC1 on enable the DAC1 output AUDO output buffer on enable the audio output circuit PGA on enable the PGA inp...

Page 30: ... EN_Comp EN_Emp EN_NBW EN_WBW EN_HPF300 EN_VOX EN_AGC Advanced Audio Process Control Register Audio Low Pass Filter High Pass Filter Function Set In a communication system signal interference and noise from adjacent channels will destroy the data to be transmitted or received Suitable filtering can improve this problem The device provides a 3 0kHz broad band and a 2 55kHz narrow band for a low pas...

Page 31: ... and a better S N ratio The high frequency power spectrum of a typical signal tends to reduce while noise will increase rapidly as the frequency rises This is quite opposite to the signals and will cause a bad S N ratio so emphasis will be used to improve this unbalanced situation The control bit I O CMD 2Ch 5 is setup as follows Emphasis Enabe Flow Flow description 82C20 Setup data 220h 2Ch 5 1 e...

Page 32: ...after the descrambler is used the scrambled signals will be returned back to their original signals The device provides eight reversion frequencies selection CLI CMD 013A 013B Disable the scrambler before changing the frequency setting and set the reversion frequency to be changed enable the scrambler function to complete the frequency change This function is controlled by the I O CMD 2Ch 7 bit by...

Page 33: ... 9873h Write data to the register A data response of 14000 means that it is correctly written otherwise it means that no data has been correctly written 14082 The CLI wrote ID code To execute a write operation with the CLI Command it is necessary to execute this command first No data response will be provided 1013B Select the 013B register Setup it as a write register No data response will be prov...

Page 34: ...at does not belong to the original signals will be eliminated after the expansion and will thus greatly reduce the noise in the output Set the companding amplitude turning point by CLI CMD 012A in the TX mode and CLI CMD 012B in the RX mode It s important to note that the TX RX setting value is different in the same turning point For example in the turning point of 100mV the 1V signal in the TX mo...

Page 35: ...mple in a 3V system MOD Output max 2780mv SMOD Output max 1920mv due to the default value of the audio processor Users must enable or change the path modulation level for their application In the high frequency modulation mechanism TX mode CTCSS and DCS always seperate the signals to access so that the digital signal of the DCS high and low fast changing can be processed efficiently The device oup...

Page 36: ... Sub audio Path Modulating Flow Flow description 14082 The CLI wrote ID code 104CB Select the register 04CB 100FF Setup data 00FFh VR2 FFh enables the maximum VR2 level Is reply 14000 The audio processor writes an acknowledge reply 36 ...

Page 37: ... 0 01h The control bit is I O CMD 2Ch 1 Audio Control 2Ch Address Bit 7 6 5 4 3 2 1 0 Name EN_Scram EN_Comp EN_Emp EN_NBW EN_WBW EN_HPF300 EN_VOX EN_AGC VOX Selection Register VOX Detection Status Chart In this mode setup the slow mode then lower the audio processor operating frequency 16MHz 4MHz and disable any unused circuits output related components to meet the minimum power consumption 16mA 1...

Page 38: ...de CTRL2 7 6 b 00 CTRL2 5 b 1 Set the audio processor to the lowest frequency 4MHz 82C02 Setup data 02h 2Ch 1 1 enable the VOX function Flow description 2 Is VOX event To be confirmed it is a VOX event 92900 The VOX high low threshold status Read the VOX threshold status 29h 1 0 b 10 above the high threshold a VOX event 29h 1 0 b 01 below the low threshold end a VOX event 81120 Go back to the slow...

Page 39: ...with a fixed gain of 5 and digital control The range is selected by using the control bit I O CMD 2Ch 0 Audio Control 2Ch Address Bit 7 6 5 4 3 2 1 0 Name EN_Scra m EN_Comp EN_Emp EN_NBW EN_WBW EN_HPF300 EN_VOX EN_AG C AGC Selection Register AGC Enable Flow Flow description 82C01 Setup data 01h 2Ch 0 1 enable the AGC function Ex With 3 3V voltage try to select OPA ratio standard MIC 16rms Sol Step...

Page 40: ...e the HT98R068 1_AppProgNote_Vxx pdf Tool Development Considerations Use the development tool specifically for the HT98R068 1 Real ICE MEV Lot No M1001C DEV Lot No D1044A or the update version To meet with the stabilish requirement it s recommended that be used by connecting with power externally to provide correct detection voltage See e ICE manual Some modifications should be made to the ICE cir...

Page 41: ... NC 36 35 NC NC 36 35 NC NC 34 33 NC NC 34 33 PA7 RESB 50 NC 32 31 NC 51 PA6 32 31 PA5 52 NC 30 29 NC 53 PA4 30 29 PC4 54 NC 28 27 NC 55 PC5 28 27 PC6 56 NC 26 25 VDD 27 28 29 57 PC7 26 25 PD0 58 24 XOUT 24 23 VSS 25 26 59 PD1 24 23 NC 22 PLLC 22 21 XIN 23 NC 22 21 VSS 60 61 20 PB4 20 19 PB5 21 NC 20 19 NC 18 PD2 18 17 PD3 19 NC 18 17 NC 16 PB2 16 15 PB3 17 63 MIC_O 16 15 MIC_I 64 14 PB0 14 13 PB1...

Page 42: ... NC 36 35 NC NC 36 35 NC NC 34 33 NC NC 34 33 PA7 RESB 36 NC 32 31 NC 37 PA6 32 31 PA5 38 NC 30 29 NC 39 PA4 30 29 PC4 40 NC 28 27 NC 41 PC5 28 27 PC6 42 NC 26 25 VDD 25 43 PC7 26 25 PD0 44 23 XOUT 24 23 VSS 24 45 PD1 24 23 NC 21 PLLC 22 21 XIN 22 NC 22 21 VSS 46 19 PB4 20 19 PB5 20 NC 20 19 NC 17 PD2 18 17 PD3 18 NC 18 17 NC 15 PB2 16 15 PB3 16 47 MIC_O 16 15 MIC_I 48 13 PB0 14 13 PB1 14 1 DEMOD ...

Page 43: ... ˇ 12M ˇ ˇ ˇ ˇ 12M None ˇ ˇ ˇ ˇ ˇ 16M ˇ ˇ 12M ˇ ˇ ˇ 12M DTMF ˇ ˇ ˇ 12M None Audio Band ˇ ˇ 16M ˇ ˇ 12M ˇ ˇ ˇ 12M ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 16M ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 16M None ˇ ˇ ˇ ˇ ˇ 16M ˇ ˇ 16M ˇ ˇ ˇ 16M CTCSS DTMF ˇ ˇ ˇ 16M ˇ ˇ 12M ˇ ˇ ˇ 12M ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 16M ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 16M None ˇ ˇ ˇ ˇ ˇ 16M ˇ ˇ 16M ˇ ˇ ˇ 16M DCS DTMF ˇ ˇ ˇ 16M VOX 4M Rx Functional Combination Capability...

Page 44: ...2M ˇ ˇ ˇ 12M ˇ ˇ ˇ 12M None DTMF Audio Band tone ˇ ˇ ˇ ˇ 16M ˇ ˇ 12M ˇ ˇ ˇ 12M ˇ ˇ ˇ 16M ˇ ˇ ˇ ˇ 16M ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 16M None ˇ ˇ ˇ ˇ ˇ 16M ˇ ˇ 16M ˇ ˇ ˇ 16M CTCSS DTMF Audio Band tone ˇ ˇ ˇ 16M ˇ ˇ 12M ˇ ˇ ˇ 12M ˇ ˇ ˇ 16M ˇ ˇ ˇ ˇ 16M ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 12M ˇ ˇ ˇ ˇ 16M None ˇ ˇ ˇ ˇ ˇ 16M ˇ ˇ 16M ˇ ˇ ˇ 16M DCS DTMF Audio Band tone ˇ ˇ ˇ 16M Tx Functional Combination Capability Table ...

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