5
5
4
4
3
3
2
2
1
1
D
D
C
C
B
B
A
A
PA16
nPCS0
PA15 SCK
PA17 nTSTSS
PA13 MISO
PA14 MOSI
PC25 nMR
MEM_MOSI
MEM_SCK
MEM_MISO
nECS1
nECS2
PC25 nMR
3V3
3V3
3V3
3V3
3V3
nCE
PA[31:0]
EMISO
nECS
PC[31:0]
EMOSI
ESCK
nECS
EMISO
EMOSI
ESCK
PC[31:0]
Title
Size
Document Number
Rev
Date:
Sheet
of
6131 EVAL TOP.DSN
A
HI-6131 EVAL PCB (Use With Std ARM CM3 Lower PCB)
A
4
4
Thursday, October 06, 2011
Title
Size
Document Number
Rev
Date:
Sheet
of
6131 EVAL TOP.DSN
A
HI-6131 EVAL PCB (Use With Std ARM CM3 Lower PCB)
A
4
4
Thursday, October 06, 2011
Title
Size
Document Number
Rev
Date:
Sheet
of
6131 EVAL TOP.DSN
A
HI-6131 EVAL PCB (Use With Std ARM CM3 Lower PCB)
A
4
4
Thursday, October 06, 2011
HI-6131 PQFP & 1553 BUS
HOLT INTEGRATED CIRCUITS, Mission Viejo, CA, USA
IN DIAGNOSTIC MODE, HI-6131
CHIP ENABLE IS DISABLED.
HOST
SPI PORT
A B C
AUTO-INIT
SELECT
--------
DEMO
EEPROM
USER
EEPROM
FOR DIAGNOSTIC TESTS,
JUMPERS SPAN COLUMNS
B-C SO THE MCU SPI CAN
READ/WRITE THE SERIAL
EEPROM. THE C PROGRAM
CONTROLS TEST SLAVE
SELECT SIGNAL, nTSTSS.
HI-6120
SPI TO
EEPROM
JUMPERS NORMALLY
SPAN COLUMNS A-B
FOR HI-613X CONTROL
OF SERIAL EEPROM.
DECOUPLING
U2 & U3
DUAL EEPROM CIRCUIT FOR EVALUATION BOARD ONLY. SW2 SELECTS EEPROM.
JP1 JUMPER ALSO PROVIDES MCU READ/WRITE ACCESS TO SELECTED EEPROM.
TYPICAL APPLICATION REPLACES ABOVE EEPROM
CIRCUIT WITH THIS SIMPLE CONFIGURATION
HI-6120
SPI TO
EEPROM
U2
EEPROM 25LC512 8-SOIC
U2
EEPROM 25LC512 8-SOIC
CS
1
SO
2
WP
3
GND
4
SI
5
SCK
6
HOLD
7
VCC
8
R30
10K
R30
10K
U3
EEPROM AT25512 8-SOIC
U3
EEPROM AT25512 8-SOIC
CS
1
SO
2
WP
3
GND
4
SI
5
SCK
6
HOLD
7
VCC
8
R31
10K
R31
10K
C11
100nF
C11
100nF
SW2
Switch SPDT
SW2
Switch SPDT
1
2
3
C10
100nF
C10
100nF
JP1
Header 5x3
JP1
Header 5x3
A1
A2
A3
B1
B2
B3
C1
C2
C3
C4
B4
A4
C5
A5
B5
R30
10K
R30
10K
C10
100nF
C10
100nF
R19
47K
R19
47K
U2
EEPROM 25LC512 8-SOIC
U2
EEPROM 25LC512 8-SOIC
CS
1
SO
2
WP
3
GND
4
SI
5
SCK
6
HOLD
7
VCC
8
