
Integration Manual
HW 86010
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© Höft & Wessel AG
page 26/46
AM
30.07.04
1.22
IM86010-1-22_.doc
Subject to amendment, errors excepted
3.4.6.3
Reset timing (external reset)
In order to make sure that an external reset is detected correctly by the
firmware, the host must pull RSTBI down sufficiently long time. The exact
timing requirements are indicated in Figure 11.
T
SH
T
RS
T
RA
RSTNO
Program
Execution
RSTBI
T
SD
Figure 11: Reset timing
Parameter
min.
max.
T
RA
11µs
T
RS
100ms
860ms
T
SD
18µs
100ms
T
SH
100µs
The host hardware can be sure to generate external reset pulses of
sufficient length, if
•
either it observes the RSTNO signal and keeps the RSTBI signal LOW
at least 100ms after the rising edge of RSTNO, or
•
it applies a RSTBI pulse of at least 970ms.
The latter method is simpler but also slower.
T
RS
depends on component tolerances, temperature and operating voltage.
It may be variable.
T
SD
depends on the firmware implementation and may vary between
different firmware versions. However the maximum value of 100ms shall not
be exceeded by any firmware version.