Hitachi HDT722516DLA380 Specifications Download Page 226

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Deskstar T7K250 Hard Disk Drive Specification

212

12.43.7 Error reporting

The following table shows the values returned in the Status and Error Registers when specific error conditions are
encountered by a device.

Table 137: S.M.A.R.T. Error Codes

Error condition

Status Register

Error Register

A S.M.A.R.T. FUNCTION SET command was received by the

device without the required key being loaded into the

Cylinder High and Cylinder Low registers.

51h

04h

A S.M.A.R.T. FUNCTION SET command was received by the

device with a subcommand value in the Features Regis-

ter that is either invalid or not supported by this

device.

51h

04h

A S.M.A.R.T. FUNCTION SET command subcommand other

than S.M.A.R.T. ENABLE OPERATIONS was received by the

device while the device was in a "S.M.A.R.T. Disabled"

state.

51h

04h

The device is unable to read its Attribute Values or

Attribute Thresholds data structure

51h

10h or 40h

The device is unable to write to its Attribute Values

data structure.

51h

10h or 01h

Summary of Contents for HDT722516DLA380

Page 1: ...ion Deskstar T7K250 3 5 inch Ultra ATA 133 hard disk drive 3 5 inch Serial ATA hard disk drive Models HDT722516DLAT80 HDT722516DLA380 HDT722525DLAT80 HDT722525DLA380 HDT722520DLAT80 HDT722520DLA380 Version 1 8 12 September 2006 ...

Page 2: ......

Page 3: ...ion Deskstar T7K250 3 5 inch Ultra ATA 133 hard disk drive 3 5 inch Serial ATA hard disk drive Models HDT722516DLAT80 HDT722516DLA380 HDT722525DLAT80 HDT722525DLA380 HDT722520DLAT80 HDT722520DLA380 Version 1 8 12 September 2006 ...

Page 4: ...ographical errors Changes are periodically made to the information herein these changes will be incorporated in new editions of the publication Hitachi may make improvements or changes in any products or programs described in this publication at any time It is possible that this publication may contain reference to or information about Hitachi products machines and programs programming or services...

Page 5: ...ion 13 4 4 1 Drive format 13 4 4 2 Cylinder allocation 13 4 5 Performance characteristics 15 4 5 1 Command overhead 15 4 5 2 Mechanical positioning 15 4 5 3 Drive ready time 17 4 5 4 Data transfer speed 18 4 5 5 Throughput 19 4 5 6 Operating modes 20 5 0 Defect flagging strategy 21 6 0 Electrical interface specification 23 6 1 Connector location 23 6 1 1 DC power connector 24 6 1 2 AT signal conne...

Page 6: ...n location 47 7 1 2 Jumper pin identification 47 7 1 3 Jumper pin assignment 48 7 1 4 Jumper positions 49 7 2 Environment 53 7 2 1 Temperature and humidity 53 7 2 2 Corrosion test 54 7 3 DC power requirements 54 7 3 1 Input voltage 54 7 3 2 Power supply current typical 55 7 3 3 Power supply generated ripple at drive power connector 56 7 4 Reliability 57 7 4 1 Data integrity 57 7 4 2 Cable noise in...

Page 7: ...ackaging 67 8 0 General 69 8 1 Introduction 69 8 2 Terminology 69 8 3 Deviations from standard 69 9 0 Registers 71 9 1 Register set 71 9 2 Alternate Status Register 72 9 3 Command Register 72 9 4 Cylinder High Register 72 9 5 Cylinder Low Register 72 9 6 Data Register 73 9 7 Device Control Register 73 9 8 Drive Address Register 74 9 9 Device Head Register 74 9 10 Error Register 75 9 11 Features Re...

Page 8: ... 10 8 4 Operation example 89 10 8 5 Command table 92 10 9 Host Protected Area Feature 93 10 9 1 Example for operation In LBA Mode 93 10 9 2 Security extensions 94 10 10 Seek overlap 95 10 11 Write cache function 96 10 12 Reassign function 97 10 12 1 Auto Reassign function 97 10 13 Power Up in Standby feature set 98 10 14 Advanced Power Management feature set APM 99 10 15 Automatic Acoustic Managem...

Page 9: ...C8h C9h 140 12 15 Read DMA Ext 25h 142 12 16 Read DMA Queued C7h 144 12 17 Read DMA Queued Ext 26h 146 12 18 Read Log Ext 2Fh 148 12 18 1 General Purpose Log Directory 149 12 18 2 Extended Comprehensive SMART Error Log 150 12 18 3 Extended Self test log sector 152 12 19 Read Long 22h 23h 154 12 20 Read Multiple C4h 156 12 21 Read Multiple Ext 29h 158 12 22 Read Native Max ADDRESS F8h 160 12 23 Rea...

Page 10: ...tribute Data Structure 203 12 43 3 Device Attribute Thresholds data structure 206 12 43 4 S M A R T Log Directory 208 12 43 5 S M A R T summary error log sector 208 12 43 6 Self test log data structure 210 12 43 7 Error reporting 211 12 44 Standby E2h 96h 212 12 45 Standby Immediate E0h 94h 213 12 46 Write Buffer E8h 214 12 47 Write DMA Queued CAh CBh 215 12 48 Write DMA FUA Ext 3Dh 217 12 49 Writ...

Page 11: ...minating Read 37 Table 23 Ultra DMA cycle timings Host Terminating Read 37 Table 24 Ultra DMA cycle timing chart Device terminating Read 38 Table 25 Ultra DMA cycle timings Device Terminating Read 38 Table 26 Ultra DMA cycle timing chart Initiating Write 39 Table 27 Ultra DMA cycle timings Initiating Write 39 Table 28 Ultra DMA cycle timing chart Device Pausing Write 40 Table 29 Ultra DMA cycle ti...

Page 12: ...lay Data structure 120 Table 65 DCO error information definition 121 Table 66 Execute Device Diagnostic command 90h 122 Table 67 Flush Cache command E7h 123 Table 68 Flush Cache Ext Command EAh 124 Table 69 Format Track command 50h 125 Table 70 Format Unit command F7h 126 Table 71 Identify Device command ECh 127 Table 72 Identify device information Part 1 of 7 128 Table 73 Identify device informat...

Page 13: ...F4h 179 Table 109 Erase Unit information 179 Table 110 Security Freeze Lock command F5h 181 Table 111 Security Set Password command F1h 182 Table 112 Security Set Password Information 182 Table 113 Security Unlock command F2h 184 Table 114 Seek command 7xh 185 Table 115 Service command A2h 186 Table 116 Set Features command EFh 187 Table 117 Set Max ADDRESS command F9h 190 Table 118 Set Max Set Pa...

Page 14: ...e 210 Table 136 S M A R T Error Codes 211 Table 137 Standby E2h 96h 212 Table 138 Standby Immediate E0h 94h 213 Table 139 Write Buffer E8h 214 Table 140 Write DMA Queued Command CAh CBh 215 Table 141 Write Sectors command 30h 31h 231 Table 142 Write Sector s Command 34h 233 ...

Page 15: ...3 Abbreviations Abbreviation Meaning A Ampere AC alternating current AT Advanced Technology ATA Advanced Technology Attachment BIOS Basic Input Output System C Celsius CSA Canadian Standards Association C UL Canadian Underwriters Laboratory Cyl cylinder DC Direct Current DFT Drive Fitness Test DMA Direct Memory Access ECC error correction code EEC European Economic Community EMC electromagnetic co...

Page 16: ...000 bits per inch kgf cm kilogram force centimeter KHz kilohertz LBA logical block addressing Lw unit of A weighted sound power m meter max maximum MB 1 000 000 bytes Mbps 1 000 000 bits per second MHz megahertz MLC Machine Level Control mm millimeter ms millisecond us ms microsecond O Output OD Open Drain Programmed Input Output PIO POH power on hours Pop population P N part number p p peak to pe...

Page 17: ...rband Deutscher Electrotechniker W watt 3 state transistor transistor tristate logic 1 4 Caution Do not apply force to the top cover Do not cover the breathing hole on the top cover Do not touch the interface connector pins or the surface of the printed circuit board This drive can be damaged by electrostatic discharge ESD Any damages incurred to the drive after its removal from the shipping packa...

Page 18: ...Deskstar T7K250 Hard Disk Drive Specification 4 ...

Page 19: ...used for firmware Ring buffer implementation Write Cache Queued feature support Advanced ECC On The Fly EOF Automatic Error Recovery procedures for read and write commands Self Diagnostics on Power on and resident diagnostics Parallel ATA PIO Register Data Transfer Mode 4 16 6 MB sec Parallel ATA DMA Data Transfer Multiword mode Mode 2 16 6 MB s Ultra DMA Mode 6 133 MB s Serial ATA Data Transfer 3...

Page 20: ...Deskstar T7K250 Hard Disk Drive Specification 6 ...

Page 21: ...Deskstar T7K250 Hard Disk Drive specification 7 Part 1 Functional specification ...

Page 22: ...Deskstar T7K250 Hard Disk Drive Specification 8 ...

Page 23: ...itions of the servo and takes corresponding action if an error occurs Monitors various timers such as head settle and servo failure Performs self checkout diagnostics 3 2 Head disk assembly The head disk assembly HDA is assembled in a clean room environment and contains the disks and actuator assembly Air is constantly circulated and filtered when the drive is operational Venting of the HDA is acc...

Page 24: ...Deskstar T7K250 Hard Disk Drive Specification 10 ...

Page 25: ... 512 512 Sectors per track 594 1242 630 1296 594 1242 Number of heads 3 4 4 Number of disks 2 2 2 Data sectors per cylinder 1782 3726 2520 5184 2376 4968 Data cylinders per zone 601 7060 1810 8341 500 6500 Logical layout1 Number of heads 16 16 16 Number of Sectors per track 63 63 63 Number of Cylinders2 16 383 16 383 16 383 Number of sectors 321 672 960 488 397 168 390 721 968 Total logical data b...

Page 26: ...signment Description 200 GB 250 GB 160 GB Organization Hitachi GST Manufacturing Site Sriracha Plant Thailand Hitachi Global Storage Products Shenzen Co Ltd China Product Deskstar T7K250 OUI 000CCAh SHBU Block Assignment Thailand China 20Bh 307h 205h 306h Port Node ID 11b ...

Page 27: ...ipment from manufacturing the drive satisfies the sector continuity in the physical format by means of the defect flagging strategy described in Section 5 0 Defect flagging strategy on page 21 in order to provide the maximum performance to users 4 4 2 Cylinder allocation Table 2 Cylinder allocation ...

Page 28: ...ding on the capacity some of the inner zone cylinders are not allocated Data cylinder This cylinder contains the user data which can be sent and retrieved via read write commands and a spare area for reassigned data Spare cylinder The spare cylinder is used by Hitachi Global Storage Technologies manufacturing and includes data sent from a defect location ...

Page 29: ... time the command is written into the command regis ter by a host to the assertion of DRQ for the first data byte of a READ command when the requested data is not in the buffer excluding Physical seek time and Latency The table below gives average command overhead 4 5 2 Mechanical positioning 4 5 2 1 Average seek time including settling Table 3 Command overhead Command type Drive is in quiescent s...

Page 30: ...l possible seek combinations max Σ m10 n Tnin Tnout n 1 Weighted Average max 1 max where max Maximum seek length n Seek length 1 to max Tnin Inward measured seek time for an n track seek Tnout Outward measured seek time for an n track seek 4 5 2 2 Full stroke seek time without command overhead including settling Full stroke seek is measured as the average of 1 000 full stroke seeks with a random h...

Page 31: ...ections inward and outward 4 5 2 6 Average latency 4 5 3 Drive ready time Ready The condition in which the drive is able to perform a media access command for exam ple read write immediately Power on This includes the time required for the internal self diagnostics Note Max Power On to ready time is the maximum time period that Device 0 waits for Device 1 to assert PDIAG Table 7 Single track seek ...

Page 32: ...y the following formula Sustained Transfer Rate A B C D where A 512 number of data sectors per cylinder B number of Surfaces per cylinder 1 head switch time C cylinder change time D number of surfaces time for one revolution Instantaneous buffer host transfer rate Mbyte s defines the maximum data transfer rate on the AT Bus It also depends on the speed of the host The method of measurement is give...

Page 33: ...e It is assumed that a host system responds instantaneously and host data transfer is faster than sustained data rate 4 5 5 2 Random access The following table illustrates simple sequential access for three disk enclosure The above table gives the time required to execute a total of 1000h read commands which access a single random LBA Typical and Max values are given by 105 and 110 of T respective...

Page 34: ...own Seek Seek operation mode Write Write operation mode Read Read operation mode Unload Idle Spindle rotation at 7200 RPM with heads unloaded Idle Spindle motor and servo system are working normally Commands can be received and pro cessed immediately Standby Actuator is unloaded and spindle motor is stopped Commands can be received immediately Sleep TActuator is unloaded and spindle motor is stopp...

Page 35: ... physical locations is calculated by an internally maintained table Shipped format Data areas are optimally used No extra sector is wasted as a spare throughout user data areas All pushes generated by defects are absorbed by the spare tracks of the inner zone Table 15 Plist physical format Defects are skipped without any constraint such as track or cylinder boundary N N 1 N 2 N 3 defect defect ski...

Page 36: ...Deskstar T7K250 Hard Disk Drive Specification 22 ...

Page 37: ...Deskstar T7K250 Hard Disk Drive Specification 23 6 0 Electrical interface specification 6 1 Connector location Refer to the following illustration to see the location of the connectors ...

Page 38: ...using AMP pins part number 350078 4 strip part number 61173 4 loose piece or their equivalents Pin assignments are shown in the figure below 6 1 2 AT signal connector The AT signal connector is a 40 pin connector The SATA signal connector is a 8 pin connector The SATA power connector is a 15 pin connector 4 3 2 1 Pin Voltage 1 12 V 2 GND 3 GND 4 5V ...

Page 39: ...e DMA burst Table 16 Signal definitions PIN SIGNAL I O Type PIN SIGNAL I O Type 01 RESET I TTL 02 GND 03 DD7 I O 3 state 04 DD08 I O 3 state 05 DD6 I O 3 state 06 DD09 I O 3 state 07 DD5 I O 3 state 08 DD10 I O 3 state 09 DD4 I O 3 state 10 DD11 I O 3 state 11 DD3 I O 3 state 12 DD12 I O 3 state 13 DD2 I O 3 state 14 DD13 I O 3 state 15 DD1 I O 3 state 16 DD14 I O 3 state 17 DD0 I O 3 state 18 DD1...

Page 40: ...lected See Table 34 I O address map on page 43 RESET This line is used to reset the drive It shall be kept at a Low logic state during power up and kept High thereafter DIOW The rising edge of this signal holds data from the data bus to a register or data register of the drive DIOR When this signal is low it enables data from a register or data register of the drive onto the data bus The data on t...

Page 41: ...ndicate that it is no longer busy and is able to provide status Following the receipt of a valid Execute Drive Diagnostics command device 1 shall negate PDIAG within 1 ms to indicate to device 0 that it is busy and has not yet passed its drive diagnostics If device 1 is present then device 0 shall wait up to 6 seconds from the receipt of a valid Execute Drive Diagnostics command for drive 1 to ass...

Page 42: ...rising and falling edge of HSTROBE latch the data from DD 15 0 into the device The host may stop toggling HSTROBE to pause an Ultra DMA data out transfer STOP Ultra DMA This signal is used only for Ultra DMA data transfers between host and drive The STOP signal shall be asserted by the host prior to initiation of an Ultra DMA burst A STOP shall be negated by the host before data is transferred in ...

Page 43: ...nition Signal I O S1 GND 2nd mate Gnd S2 A Differential signal A from Phy RX Input S3 A RX Input Signal S4 Gnd 2nd mate Gnd S5 B Differential signal B from Phy TX Output S6 B TX Output S7 Gnd 2nd mate Gnd Key and spacing separate signal and power segments P1 V33 3 3V power 3 3V P2 V33 3 3V power 3 3V P3 V33 3 3V power pre charge 2nd Mate 3 3V P4 Gnd 1st mate Gnd P5 Gnd 2nd mate Gnd P6 Gnd 2nd mate...

Page 44: ... are the inbound high speed differential signals that are connected to the serial ATA cable The fol lowing standard shall be referenced about signal specifications Serial ATA High Speed Serialized AT Attachment Revision 1 0a 7 January 2003 6 6 Out of band signaling SATA model PARAMETER DESCRIPTION Nominal ns t1 ALINE primitives 106 7 t2 Spacing 320 t3 ALIGN primitives 106 7 t4 Psacing 106 7 ...

Page 45: ...T7K250 Hard Disk Drive Specification 31 6 7 Reset timings Table 18 System reset timing chart Table 19 System reset timing PARAMETER DESCRIPTION Min µs Max µs t10 RESET low width 25 t14 RESET high to not BUSY 31 ...

Page 46: ...the next DRQ bit PARAMETER DESCRIPTION MIN ns MAX ns t0 Cycle time 120 t1 Address valid to DIOR DIOW setup 25 t2 DIOR DIOW pulse width 70 t2i DIOR DIOW recovery time 25 t3 DIOW data setup 20 t4 DIOW data hold 10 t5 DIOR data setup 20 t6 DIOR data hold 5 t9 DIOR DIOW to address valid hold 10 tA IORDY setup width 35 tB IORDY pulse width 1250 IOCS16 t9 t0 t2 t2i t3 t4 t5 t8 t7 t1 tB Read data DD 15 0...

Page 47: ... end of negation of the DRQ bit until setting of the next DRQ bit is as follows In the event that a host reads the status register only before the sector or block transfer DRQ interval the DRQ interval 4 2 µs In the event that a host reads the status register after or both before and after the sector or block transfer the DRQ interval is 11 5 µs ...

Page 48: ...pulse width 70 tE DIOR data access 50 tF DIOR data hold 5 tG DIOR DIOW data setup 20 tH DIOW data hold 10 tI DMACK to DIOR DIOW setup 0 tJ DIOR DIOW to DMACK hold 5 tKR tKW DIOR DIOW negated pulse width 25 tLR tLW DIOR DIOW to DMARQ delay 35 tM CS 1 0 valid to DIOR DIOW 25 tN CS 1 0 10 tZ DMACK to read data released 25 WRITE DATA READ DATA DMACK DMARQ DIOR DIOW t0 tLR tLW tJ tI tD tKR tKW tF tG tH...

Page 49: ... driv ing IORDY 0 0 0 0 0 0 tFS First DSTROBE time 0 230 0 200 0 170 0 130 0 120 90 tCYC Cycle time 112 73 54 39 25 17 t2CYC Two cycle time 230 154 115 86 57 38 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAD Drivers to assert 0 0 0 0 0 0 tDS Data setup time at host 15 10 7 7 5 4 8 tDH Data hold time at host 5 5 5 5 5 4 8 tDZFS Time from data ouput released to driving...

Page 50: ...ausing Read Table 21 Ultra DMA cycle timings Host pausing Read PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR DSTROBE to HDMARDY time 50 30 20 tRFS HDMARDY to final DSTROBE time 75 70 60 60 60 50 DSTROBE HDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 51: ... tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Minimum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 tIORDYZ Maximum...

Page 52: ...ted interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tAZ Maximum time allowed for output drivers to release 10 10 10 10 10 10 tZAH Maximum delay time required for output 20 20 20 20 20 20 tMLI Interlock time with minimum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 tIORDYZ Maximum time bef...

Page 53: ...K Setup time for DMACK 20 20 20 20 20 20 tENV Envelope time 20 70 20 70 20 70 20 55 20 55 20 55 tZIORDY Minimum time before driving IORDY 0 0 0 0 0 0 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tCYC Cycle time 112 73 54 39 25 16 8 t2CYC Two cycle time 230 154 115 86 57 38 tDS Data setup time at device 15 10 7 7 5 4 tDH Data Hold time at device 5 5 5 5 5 4 6 HSTROBE DDMARDY DMACK ...

Page 54: ...ng Write Note When a device does not satisfy the tSR timing it shall be ready to receive two more strobes after DDMARDY is negated PARAMETER DESCRIPTION all values in ns MODE 0 MODE 1 MODE 2 MODE 3 MODE 4 MODE 5 MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX MIN MAX tSR HSTROBE to DDMARDY time 50 30 20 tRFS DDMARDY to final HSTROBE time 75 70 60 60 60 50 HSTROBE DDMARDY DMACK DMARQ tSR STOP tRFS ...

Page 55: ...HSTROBE time 75 70 60 60 60 50 tRP Ready to pause time 160 125 100 100 100 85 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlocking time with minimum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 tACK Hold time for DMACK negation 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20...

Page 56: ...tSS Time from HSTROBE edge to assertion of STOP 50 50 50 50 50 50 tLI Limited interlock time 0 150 0 150 0 150 0 100 0 100 0 75 tMLI Interlock time with minimum 20 20 20 20 20 20 tCS CRC word setup time at device 15 10 7 7 5 5 tCH CRC word hold time at device 5 5 5 5 5 5 tACK Hold time for DMACK 20 20 20 20 20 20 tIORDYZ Maximum time before releasing IORDY 20 20 20 20 20 20 HSTROBE DDMARDY DMACK D...

Page 57: ...ents before interrupt the value is invalid 6 11 1 Cabling The maximum cable length from the host system to the drive plus circuit pattern length in the host system shall not exceed 18 inches For higher data transfer application 8 3 MB s a modification in the system design is recommended to reduce cable noise and cross talk such as a shorter cable bus termination or a shielded cable For systems ope...

Page 58: ...Deskstar T7K250 Hard Disk Drive Specification 44 ...

Page 59: ...Deskstar T7K250 Hard Disk Drive Specification 45 Part 2 Interface specification ...

Page 60: ...Deskstar T7K250 Hard Disk Drive Specification 46 ...

Page 61: ...Deskstar T7K250 Hard Disk Drive Specification 47 7 0 Specification 7 1 Jumper settings 7 1 1 Jumper pin location 7 1 2 Jumper pin identification Jum perpins Pin A Pin B Pin I DERA001 prz ...

Page 62: ...Within each of these four jumper settings the pin assignment selects Device 0 Device 1 Cable Selection or Device 1 Slave Present as shown in the following figures The Device 0 setting automatically recognizes device 1 if it is present The Device 1 Slave Present setting is for a slave device that does not comply with the ATA specification Note In conventional terminology Device 0 designates a Maste...

Page 63: ...k must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounded or at a low level the drive address is 0 Device 0 When CSEL is open or at a high level the drive address is 1 Device 1 GND DS I G E C A H D B F RSV GND GND RSV CS SP GND RSV G I E C A H F D B DEVICE 0 Master G I E C A H F D B DEVICE 1 Slave G I E C A H F D B C...

Page 64: ...default 16 logical head models Notes 1 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounded or at a low level the drive address is 0 Device 0 When CSEL is open or at a high level the drive address is 1 Device 1 2 In CSEL mode installing or removing the ...

Page 65: ...lips the LBA to 66055248 The CHS is unchanged from the factory default of 16383 16 63 7 1 4 4 Power up in Standby The figure below shows the jumper positions used to select Device 0 Device 1 Cable Selection or Device1 Slave Present to enable Power Up In Standby G I E C A H F D B DEVICE 0 Master G I E C A H F D B DEVICE 1 Slave G I E C A H F D B CABLE SEL G I E C A H F D B DEVICE 1 Slave Present G ...

Page 66: ... SET FEATURES subcommand 07h Refer to 12 28 Set Features 3 To enable the CSEL mode Cable Selection mode the jumper block must be installed at E F In the CSEL mode the drive address is determined by AT interface signal 28 CSEL as follows When CSEL is grounded or at a low level the drive address is 0 Device 0 When CSEL is open or at a high level the drive address is 1 Device 1 ...

Page 67: ...aintained at any time Maximum storage period within shipping package is one year Table 35 Temperature and humidity Operating conditions Temperature 5C to 55ºC See note below Relative humidity 8 to 90 non condensing Maximum wet bulb temperature 29 4ºC non condensing Maximum temperature gradient 15ºC hour Altitude 300 to 3 048 m Non operating conditions Temperature 40C to 65ºC Relative humidity 5 to...

Page 68: ... If SATA power supply cable is connected or disconnected to the SATA power connector hot plug unplug is allowed 7 3 1 Input voltage 1 To avoid damage to the drive electronics power supply voltage spikes must not exceed specifications Table 36 Input voltage Input voltage supply During run and spin up Absolute max spike voltage1 Supply rise time 5 V 5 V 5 0 3 to 7 V 0 to 5 sec 12 V 12 V 10 8 0 3 to ...

Page 69: ... 72 Unload idle average Unload idle ripple 160 220 6 20 270 400 6 20 4 04 Random R W average Random R W peak 500 1200 6 30 600 1700 10 40 9 70 Silent R W average2 Silent R W peak 500 1200 6 30 400 1000 8 40 7 3 Start up max 900 50 1880 50 Standby average 150 9 15 2 0 93 Sleep average 100 10 15 2 0 68 Power supply current of 160 GB and 250 GB model SATA models 5 Volts mA 12 Volts mA Total W Pop mea...

Page 70: ...xternal electrical noise from interfering with the performance of the drive the drive must be held by four screws in a user system frame which has no electrical level difference at the four screws position and has less than 300 millivolts peak to peak level difference to the ground of the drive power connector Silent R W average2 Silent R W peak 680 1450 9 30 400 1000 12 40 8 2 Start up max 1200 5...

Page 71: ...art stop cycles in a 40 C environment and a minimum of 10 000 start stop cycles in extreme temperature or humidity within the operating range See Table 35 Temperature and humidity on page 53 and Figure 5 Limits of temperature and humidity on page 28 7 4 4 Preventive maintenance None 7 4 5 Data reliability Probability of not recovering data is 1 in 1014 bits read ECC On The Fly correction 1 Symbol ...

Page 72: ...5 Mechanical specifications 7 5 1 Physical dimensions and weight All dimensions in the above figure are in millimeters The breather hole must be kept uncovered in order to keep the air pressure inside of the disk enclosure equal to external air pressure ...

Page 73: ...le locations The mounting hole locations and size of the drive are shown below All dimensions are in mm Table 39 Physical dimensions and weight Height mm 25 4 0 4 Width mm 101 6 0 4 Length mm 146 0 0 6 Weight grams maximum 640 Thread 1 2 3 4 5 6 7 6 32 UNC 41 28 0 5 44 45 0 2 95 25 0 2 6 35 0 2 28 5 0 5 60 0 0 2 41 6 0 2 ...

Page 74: ... error rate will stay within specification limits if the drive is operated in the other orientations from which it was formatted For reliable operation the drive must be mounted in the system securely enough to prevent excessive motion or vibration of the drive during seek operation or spindle rotation using appropriate screws or equivalent mounting hardware ...

Page 75: ...ive level vibration test and shock test are to be conducted with the drive mounted to the table using the bottom four screws 7 5 5 Heads unload and actuator lock The head load unload mechanism is provided to protect the disk data during shipping movement or storage Upon power down the heads are automatically unload from the disk area and the locking mechanism of the head actuator will secure the h...

Page 76: ...fied conditions No errors occur with 0 5 G 0 to peak 5 to 300 to 5 Hz sine wave 0 5 oct min sweep rate with 3 minute dwells at two major resonances No data loss occurs with 1 G 0 to peak 5 to 300 to 5 Hz sine wave 0 5 oct min sweep rate with 3 minute dwells at two major resonances 7 6 2 Nonoperating vibration The drive does not sustain permanent damage or loss of previously recorded data after bei...

Page 77: ...es No error occurs with a 10 G half sine shock pulse of 11 ms duration in all models No data loss occurs with a 30 G half sine shock pulse of 4 ms duration in all models No data loss occurs with a 55 G half sine shock pulse of 2 ms duration in all models 7 6 4 Nonoperating shock The drive will operate with no degradation of performance after being subjected to shock pulses with the following chara...

Page 78: ...pulse The figure below shows the maximum acceleration level and duration 7 6 5 Nonoperating rotational shock All shock inputs shall be applied around the actuator pivot axis Table 43 Rotational shock Table 42 Sinusoidal shock wave Acceleration level G Duration ms 350 2 150 11 Duration Rad sec2 1 ms 30 000 2 ms 20 000 ...

Page 79: ...ollowing formula Dwell time 0 5 x 60 RPM Seek rate 0 4 average seek time dwell time 7 8 Identification labels The following labels are affixed to every drive A label containing the Hitachi logo the Hitachi Global Storage Technologies part number and the statement Made by Hitachi Global Storage Technologies Inc or Hitachi Global Storage Technol ogies approved equivalent A label containing the drive...

Page 80: ...Safe handling The product is conditioned for safe handling in regards to sharp edges and corners 7 9 5 Environment The product does not contain any known or suspected carcinogens Environmental controls meet or exceed all applicable government regulations in the country of origin Safe chemi cal usage and manufacturing control are used to protect the environment An environmental impact assessment ha...

Page 81: ... 2 0001 401 and NB 2 0001 403 7 10 1 CE mark The product is declared to be in conformity with requirements of the following EC directives under the sole responsibility of Hitachi Global Storage Technologies Japan Ltd Council Directive 89 336 EEC on the approximation of laws of the Member States relating to electromagnetic compatibility 7 10 2 C TICK mark The product complies with the following Aus...

Page 82: ...Deskstar T7K250 Hard Disk Drive Specification 68 ...

Page 83: ...ions described in Section 8 3 below 8 2 Terminology 8 3 Deviations from standard The device conforms to the referenced specifications with the following deviations Check Power Mode Check Power Mode command returns FFh to Sector Count Register when the device is in Idle mode This command does not support 80h as the return value Hard Reset Hard reset response is not the same as that of power on rese...

Page 84: ...Deskstar T7K250 Hard Disk Drive Specification 70 ...

Page 85: ...ternate status Addresses Functions CS0 CS1 DA2 DA1 DA0 READ DIOR WRITE DIOW N N x x x Data bus high impedance Not used Control block registers N A 0 x x Data bus high impedance Not used N A 1 0 x Data bus high impedance Not used N A 1 1 0 Alternate Status Device Control N A 1 1 1 Device Address Not used Command block registers A N 0 0 0 Data Data A N 0 0 1 Error Register Features A N 0 1 0 Sector ...

Page 86: ...he end of the com mand this register is updated to reflect the current cylinder number In LBA Mode this register contains Bits 16 23 At the end of the command this register is updated to reflect the current LBA Bits 16 23 The cylinder number may be from zero to the number of cylinders minus one When 48 bit addressing commands are used the most recently written content contains LBA Bits 16 23 and t...

Page 87: ... DRQ 1 is in the Status Register 9 7 Device Control Register Table 48 Device Control Register 7 6 5 4 3 2 1 0 HOB 1 SRST IEN 0 Bit Definitions HOB HOB high order byte is defined by the 48 bit Address feature set A write to any Command Register shall clear the HOB bit to zero SRST Software Reset The device is held at reset when RST 1 Setting RST 0 again enables the device To ensure that the device ...

Page 88: ...ast significant DS1 Drive Select 1 The Drive Select bit for device 1 is active low DS1 0 when device 1 slave is selected and active DS0 Drive Select 0 The Drive Select bit for device 0 is active low DS0 0 when device 0 master is selected and active 7 6 5 4 3 2 1 0 1 L 1 DRV HS3 HS2 HS1 HS0 L Binary encoded address mode select When L 0 addressing is by CHS mode When L 1 addressing is by LBA mode DR...

Page 89: ... specified If the register is zero at command completion the command was successful If it is not successfully completed the register contains the number of sectors which need to be transferred in order to complete the request The contents of the register are defined otherwise on some commands These definitions are given in the command descriptions 7 6 5 4 3 2 1 0 CRC UNC 0 IDNF 0 ABRT TK0NF AMNF B...

Page 90: ... bit commands are used the most recently written content contains LBA Bits 0 7 and the previous con tent contains Bits 24 31 9 14 Status Register Table 52 Status Register This register contains the device status The contents of this register are updated whenever an error occurs and at the completion of each command If the host reads this register when an interrupt is pending it is considered to be...

Page 91: ...e device just before a Seek begins When an error occurs this bit is not changed until the Status Register is read by the host at which time the bit again indicates the current Seek complete status When the device enters into or is in Standby mode or Sleep mode this bit is set by the device in spite of the drive not spinning up DRQ Data Request Bit DRQ 1 indicates that the device is ready to transf...

Page 92: ...Deskstar T7K250 Hard Disk Drive Specification 78 ...

Page 93: ...sponse table POR hard reset soft reset Aborting Host interface O O Aborting Device operation 1 1 Initialization of hardware O X X Internal diagnostic O X X Spinning spindle O X X Initialization of registers 2 O O O DASP handshake O O X PDIAG handshake O O O Reverting programmed parameters to default Number of CHS set by Initialize Device Parameters Multiple mode Write Cache Read look ahead ECC byt...

Page 94: ...rd reset or the Execute Device Diagnostic command is shown in the figure below Table 54 Default Register Values Register Default Value Error Diagnostic Code Sector Count 01h Sector Number 01h Cylinder Low 00h Cylinder High 00h Device Head A0h Status 50h Alternate Status 50h Table 55 Diagnostic codes Code Description 01h No error detected 02h Formatter device error 03h Sector buffer error 04h ECC c...

Page 95: ...ce 0 may assert DASP to indicate device activity Hard Reset Soft Reset If Device 1 is present Device 0 shall read PDIAG to determine when it is valid to clear the BSY bit and whether Device 1 has reset without any errors otherwise Device 0 shall simply reset and clear the BSY bit DASP is asserted by Device 0 and Device 1 if it is present in order to indicate device active Execute Device Diagnostic...

Page 96: ...the host requests the number of sectors per logical track and the number of heads per logical cylinder The device then computes the number of logical cylinders available in requested mode The default CHS translation mode is described in the Identify Device Information The current CHS translation mode also is described in the Identify Device Information 10 4 2 LBA addressing mode Logical sectors on...

Page 97: ...o one setting a pending interrupt and asserting INTRQ if selected and if nIEN is cleared to zero SERV shall remain set until all commands ready for service have been serviced The pending interrupt shall be cleared and INTRQ negated by a Status register read or a write to the Command register When the device is ready to continue processing a bus released command and BSY or DRQ is set to one i e the...

Page 98: ...ed Sleep Mode The lowest power consumption when the device is powered on occurs in Sleep Mode When in Sleep Mode the device requires a reset to be activated Standby Mode The device interface is capable of accepting commands but since the media may not be immediately accessible there is a delay while waiting for the spindle to reach operating speed Idle Mode In Idle Mode the device is capable of re...

Page 99: ...physical interface as defined in the following table Ready RDY is not a power condition A device may post ready at the interface even though the media may not be accessible Table 57 Power conditions Mode BSY RDY Interface active Media Active x x Yes Active Idle o 1 Yes Active Standby o 1 Yes Inactive Sleep x x No Inactive ...

Page 100: ...xisting Accordingly lower attribute values indicate that the analysis algorithms being used by the device are predicting a higher probability of a degrading or faulty condition 10 7 3 Attribute thresholds Each attribute value has a corresponding attribute threshold limit which is used for direct comparison to the attribute value to indicate the existence of a degrading or faulty condition The nume...

Page 101: ...are modification all error log data is discarded and the device error count for the life of the device is reset to zero 10 7 8 Self test The device provides the self test features which are initiated by SMART Execute Off line Immediate command The self test checks the fault of the device reports the test status in Device Attributes Data and stores the test result in the SMART self test log sector ...

Page 102: ...n Media access commands are enabled by either a Security Unlock command or a Security Erase Unit command Device Unlocked Mode The device enables all commands If a password is not set this mode is entered after power on otherwise it is entered by a Security Unlock or a Security Erase Unit command Device Frozen Mode The device enables all commands except those which can update the device lock functi...

Page 103: ...d is set the device will automatically enter lock mode the next time the device is powered on Master Password When the Master Password is set the device does NOT enable the Device Lock Function and the device CANNOT be locked with the Master Password but the Master Password can be used for unlocking the locked device Identify Device Information word 92 contains the value of the Master Password Rev...

Page 104: ...he commands in Figure 10 8 5 Command table on page 92 POR Device Locked mode Unlock CMD Command 1 Command 1 Password Erase Unit Password Match Reject Complete Complete Erase Unit Lock function Disable Normal operation All commands are available Freeze Lock command Enter Device Frozen mode Normal Operation expect Set Password Disable Password Erase Unit Unlock commands Enter Device Unlock mode N Y ...

Page 105: ...K command has an attempt limit the purpose of which is to prevent attempts to unlock the drive with various passwords numerous times The device counts the password mismatch If the password does not match the device counts it without distinguishing the Master password and the User password If the count reaches 5 EXPIRE bit bit 4 of Word 128 in Identify Device information is set and then the SECURIT...

Page 106: ...o o S M A R T Enable Operations o o o Initialize Device Parameters o o o S M A R T Exectue Off line Immdeiate o o o NOP S M A R T Read Attribute Values o o o Read Buffer o o o S M A R T Read Attribute Thresholds o o o Read DMA x o o S M A R T Return Status o o o Read DMA Ext x o o S M A R T Save Attributre Values o o o Read DMA Queued x o o S M A R T Read Log Sector o o o Read DMA Queued Ext x o o...

Page 107: ...e is as follows i Issue a Read Native Max ADDRESS command to get the real device maximum LBA Returned value shows that native device maximum LBA is 12 692 735 C1ACFFh regardless of the current setting ii Make the entire device accessible including the protected area by setting the device maximum LBA to 12 692 735 C1ACFFh via Set Max ADDRESS command The option may be either nonvolatile or volatile ...

Page 108: ...et Max Lock Set Max Freeze Lock Set Max Unlock The Set Max Set Password command allows the host to define the password to be used during the current power on cycle The password does not persist over a power cycle but does persist over a hardware or software reset This password is not related to the password used for the Security Mode Feature set When the password is set the device is in the Set_Ma...

Page 109: ...seek command from the host however the actual seek operation for the next seek command starts immediately after the actual seek operation for the first seek command is completed In other words the execution of two seek commands overlaps excluding the time required for the actual seek operation With this overlap the total elapsed time for a number of seek commands results in the total accumulated t...

Page 110: ...he data onto the disk While writing data after completed acknowledgment of a write command soft reset or hard reset does not affect its operation However power off terminates the writing operation immediately and unwritten data is lost The Soft reset Standby Immediate command and Flush Cache commands during the writing of the cached data are executed after the completion of writing to media So the...

Page 111: ...ecovered write errors When a write operation cannot be completed after the Error Recovery Procedure ERP is fully carried out the sector s are reallocated to the spare location An error is reported to the host system only when the write cache is disabled and the auto reallocation has failed If the Write Cache function is ENABLED when the number of available spare sectors reaches 0 sector both Auto ...

Page 112: ...after power cycle A device needs a SET FEATURES subcommand to spin up to active state when the device has powered up into Standby The device remains in Standby until the SET FEATURES subcommand is received If power up into Standby is enabled when an IDENTIFY DEVICE is received while the device is in Standby as a result of powering up into Standby the device shall set word 0 bit 2 to one to indicat...

Page 113: ...EATURES command in detail This feature set uses the following functions A SET FEATURES subcommand to enable Advanced Power Management A SET FEATURES subcommand to disable Advanced Power Management Advanced Power Management is independent of the Standby timer setting If both Advanced Power Management and the Standby timer are set the device will go to the Standby state when the timer times out or t...

Page 114: ...ic Management and the Standby timer setting are independent functions The device shall enter Standby mode if any of the following are true 1 The Standby timer has been set and times out 2 Automatic Power Management is enabled and the associated algorithm indicates that the Standby mode should be entered to save power 3 Automatic Acoustic Management is enabled and the associated algorithm indicates...

Page 115: ...Mode Subcommand code 09h Enable Address Offset Mode offsets address Cylinder 0 Head 0 Sector 1 LBA 0 to the start of the nonvolatile protected area established using the Set Max Address command The offset condition is cleared by Subcommand 89h Disable Address Offset Mode Hardware reset or Power on Reset If Reverting to Power on Defaults has been enabled by Set Features command it is cleared by Sof...

Page 116: ... device is in Address Offset mode 10 16 3 Exceptions in Address Offset Mode Any commands which access sectors across the original native maximum LBA are rejected with error even if the access protection is removed by a Set Max Address command If the sectors for Read Look Ahead operation include the original native maximum LBA Read Look Ahead operation is not carried out even if it is enabled by th...

Page 117: ...ister to one and then reading the desired register If HOB in the Device Control register is cleared to zero the host reads the most recently written content when the register is read A write to any Command Block register shall cause the device to clear the HOB bit to zero in the Device Control register The most recently written content always gets written by a register write regardless of the stat...

Page 118: ... device vendor specific The streaming commands may access any user LBA on a device These commands may be interspersed with non streaming commands but there may be an impact on performance due to the unknown time required to complete the non streaming commands The streaming commands should be issued using a specified minimum number of sectors transferred per command as specified in word 95 of the I...

Page 119: ...omplete the request without posting an error If an error cannot be resolved within the Command Completion Time Limit the erroneous section on the media may be unchanged or may contain undefined data A future read of this area may not report an error even though the data is erroneous 10 18 1 6 Streaming Logs The Streaming Data Transfer feature set requires two error logs and one performance log The...

Page 120: ...Deskstar T7K250 Hard Disk Drive Specification 106 ...

Page 121: ... responding Interrupts are cleared when the host reads the Status Register issues a reset or writes to the Command Register See Section 13 0 Time out values on page 241 for the device time out values 11 1 PIO Data In commands The following are Data In commands Device Configuration Identity Identify Device Read Buffer Read Log Ext Read Long Read Multiple Read Multiple Ext Read Sector s Read Sector ...

Page 122: ...ort the command by setting BSY 0 ERR 1 ABT 1 and interrupting the host If an error occurs the device will set BSY 0 ERR 1 and DRQ 1 The device will then store the error status in the Error Register and interrupt the host The registers will contain the location of the sector in error The error location will be reported using CHS mode or LBA mode The mode is decided by the mode select bit bit 6 of t...

Page 123: ...device sets BSY 0 and DRQ 1 when it is ready to receive a sector b The host writes one sector of data including ECC bytes via the Data Register c The device sets BSY 1 after it has received the sector d After processing the sector of data the device sets BSY 0 and interrupts the host e In response to the interrupt the host reads the Status Register f The device clears the interrupt in response to ...

Page 124: ... M A R T Disable Operations S M A R T Enable Disable Attribute Autosave S M A R T Enable Disable Automatic Off Line S M A R T Enable Operations S M A R T Execute Off line Data Collection S M A R T Return Status S M A R T Save Attribute Values Standby Standby Immediate Execution of these commands involves no data transfer a The host writes any required parameters to the Features Sector Count Sector...

Page 125: ...pts are issued on multisector commands The host resets the DMA channel prior to reading status from the device The DMA protocol allows high performance multitasking operating systems to eliminate processor overhead asso ciated with PIO transfers 1 The host initializes the Slave DMA channel 2 The host writes any required parameters to the Features Sector Count Sector Number Cylinder and Device Head...

Page 126: ...device clears BDY 2 Data Transfer and Command Completion If the device is ready for data transfer REL is cleared a the host transfers the data for the command identified by the Tag number using tghe DMA transfer pro tocol currently in effect b the device generates an interrupt to the host when all of the data has been transferred c the host may issue another command or wait for service request fro...

Page 127: ...E3 1 1 1 0 0 0 1 1 3 Idle 97 1 0 0 1 0 1 1 1 3 Idle Immediate E1 1 1 1 0 0 0 0 1 3 Idle Immediate 95 1 0 0 1 0 1 0 1 3 Initialize Device Parameters 91 1 0 0 1 0 0 0 1 3 NOP 00 0 0 0 0 0 0 0 0 1 Read Buffer E4 1 1 1 0 0 1 0 0 4 Read DMA C8 1 1 0 0 1 0 0 0 4 Read DMA C9 1 1 0 0 1 0 0 1 4 Read DMA Ext 25 0 0 1 0 0 1 0 1 5 Read DMA Queued C7 1 1 0 0 0 1 1 1 5 Read DMA Queued Ext 26 0 0 1 0 0 1 1 0 1 R...

Page 128: ...1 0 1 1 0 0 0 0 3 S M A R T Execute Off line Data Col lection B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Values B0 1 0 1 1 0 0 0 0 1 S M A R T Read Attribute Thresholds B0 1 0 1 1 0 0 0 0 3 S M A R T Return Status B0 1 0 1 1 0 0 0 0 3 S M A R T Save Attribute Values B0 1 0 1 1 0 0 0 0 2 S M A R T Write Log Sector B0 1 0 1 1 0 0 0 0 3 Standby E2 1 1 1 0 0 0 1 0 3 Standby 96 1 0 0 1 0 1 1 0 3 Sta...

Page 129: ...omatic Off line B0 DB Set Features Enable Write Cache EF 02 Set Transfer mode EF 03 Enable Advanced Power Management EF 05 Enable Power up in Standby Feature Set EF 06 Power up in Standby Feature Set Device Spin up EF 07 Enable Address Offset mode EF 09 Enable Automatic Acoustic Management EF 42 52 bytes of ECC apply on Read Write Long EF 44 Disable read look ahead feature EF 55 Enable release int...

Page 130: ... meaning is already obsolete there is no difference between 0 and 1 Using 0 is recommended for future compatibility B Option Bit This indicates that the Option Bit of the Sector Count Register be specified This bit is used by Set Max ADDRESS command V Valid This indicates that the bit is part of an output parameter and should be specified x This indicates that the hex character is not used This in...

Page 131: ...r is at speed and the device is not in Standby or Sleep mode Other wise the Sector Count Register is set to 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count V V V V V V V V Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Dev...

Page 132: ...gs After successful execution of a DEVICE CONFIGURATION FREEZE LOCK com mand all DEVICE CONFIGURATION SET DEVICE CONFIGURATION FREEZE LOCK DEVICE CONFIGURATION IDENTIFY and DEVICE CONFIGURATION RESTORE commands are aborted by the device The DEVICE CONFIGURATION FREEZE LOCK condition shall be cleared by a power down The DEVICE CONFIGURATION FREEZE LOCK condition shall not be cleared by hardware or ...

Page 133: ...n the overlay transmitted by the device that is not set in the overlay received from a DEVICE CONFIGURATION IDENTIFY command no action is taken for that bit The format of the overlay transmitted by the device is described in the table in Table 65 Device Configuration Overlay Data structure on page 120 The restrictions on changing these bits is described in the text following that table If any of t...

Page 134: ... are supported 0 1 Multiword DMA mode 0 is supported 2 Ultra DMA modes supported 15 6 Reserved 5 1 Ultra DMA mode 5 and below are supported 4 1 Ultra DMA mode 4 and below are supported 3 1 Ultra DMA mode 3 and below are supported 2 1 Ultra DMA mode 2 and below are supported 1 1 Ultra DMA mode 1 and below are supported 0 1 Ultra DMA mode 0 is supported 3 6 Maximum LBA address 7 Command set feature ...

Page 135: ...lid bit location bits 15 8 Sector count error reason code description 01h DCO feature is frozen 02h Device is now Security Locked mode 03h Device s feature is already modified with DCO 04h User attempt to disable any feature enabled 05h Device is now SET MAX Locked or Frozen mode 06h Protected area is now established 07h DCO is not supported 08h Subcommand code is invalid FFh other reason ...

Page 136: ...e register contains a diagnostic code See Table 54 Default Register Values on page 80 for the definition Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 Device Head Command 1 0 0 ...

Page 137: ...mand Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ...

Page 138: ...2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 Previous HOB 1 Cylinder Low Current Cylinder Low HOB 0 Previous HOB 1 Cylinder High Current Cylinder High HOB 0 Previous HOB 1 Device Head D Device Head Command 1 1 1 0 1 0 1 0 Status See below...

Page 139: ...A address bits 8 15 Low and bits 16 23 High are to be formatted L 1 H This indicates the head number of the track to be formatted L 0 In LBA mode this reg ister specifies that LBA address bits 24 27 are to be formatted L 1 Input parameters from the device Sector Number In LBA mode this register specifies the current LBA address bits as 0 7 L 1 Cylinder High Low In LBA mode this register specifies ...

Page 140: ...ase Prepare F3h command should be completed immediately prior to the Format Unit command If the device receives a Format Unit command without a prior Security Erase Prepare command the device aborts the Format Unit command All values in Feature register are reserved and any values other than 11h should not be put into Feature register This command does not request a data transfer Command execution...

Page 141: ...3 beginning on page 128 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 1 0 0 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5...

Page 142: ...spin up after power up Identify Device is incomplete 03 00XXH Number of heads in default translate mode 04 0 Reserved 05 0 Reserved 06 003FH Number of sectors per track in default translate mode 07 0000H Number of bytes in sector gap 08 0000H Number of bytes in sync field 09 0000H Reserved 10 19 XXXX Serial number in ASCII 0 not specified 20 0003H Controller type 0003 dual ported multiple sector b...

Page 143: ...nsfer cycle timing mode 52 0200H DMA data transfer cycle timing mode Refer to Word 62 and 63 53 0007H Validity flag of the word 15 3 0 Reserved 2 1 1 Word 88 is Valid 1 1 1 Word 64 70 are Valid 0 1 1 Word 54 58 are Valid 54 XXXXH Number of current cylinders 55 XXXXH Number of current heads 56 XXXXH Number of current sectors per track 57 58 XXXXH Current capacity in sectors Word 57 specifies the lo...

Page 144: ...16 6 MB s 69 74 0000H Reserved 75 00XXH Queue depth 15 5 Reserved 4 0 Maximum queue depth 76 0106H SATA capabilities 15 11 0 Reserved 10 0 Phy event counters 9 1 Receipt of host initiated interface power management requests 8 1 Native Command Queuing supported 7 3 0 Reserved 2 1 SATA Gen 2 speed 3 0Gbps supported 1 1 SATA Gen 1 speed 1 5Gbps supported 0 0 Reserved 77 0000H Reserved 78 0016H SATA s...

Page 145: ...ion 3a 82 74EBH Command set supported 15 0 Reserved 14 1 NOP command 13 1 READ BUFFER command 12 1 WRITE BUFFER command 11 0 Reserved 10 1 Host Protected Feature set 9 0 DEVICE RESET command 8 0 SERVICE interrupt 7 1 RELEASE interrupt 6 1 LOOK AHEAD 5 1 WRITE CACHE 4 0 PACKET Command Feature set 3 1 Power Management Feature Set 2 0 Removable feature set 1 1 Security feature set 0 1 SMART feature s...

Page 146: ...Removable Media Status Notification feature 3 1 Advanced Power Management Feature Set 2 0 CFA feature set 1 1 READ WRITE DMA QUEUED 0 0 DOWNLOAD MICROCODE command 84 4023H Command set feature supported extension 15 14 Word 84 is valid 13 6 Reserved 5 1 General purpose logging feature set supported 4 2 Reserved 1 1 SMART self test supported 0 1 SMART error logging supported 85 XXXXH Command set fea...

Page 147: ...ROCODE command 87 4023H Command set feature enabled 15 14 01 Word 87 is valid 13 6 0 Reserved 5 1 General Purpose Logging feature set supported 4 2 0 Reserved 1 1 SMART self test supported 0 1 SMART error logging supported 88 0X3FH Ultra DMA transfer modes 15 8 xx Current active Ultra DMA transfer mode 15 14 Reserved 0 13 Mode 5 1 Active 0 Not Active 12 Mode 4 1 Active 0 Not Active 11 Mode 3 1 Act...

Page 148: ... not respond 5 DASP detection 1 detect 0 not detect 4 PDIAG detection 1 pass 0 fail 3 Device 0 diagnostic 1 pass 0 fail 2 1 How to determine the device number 00 Reserved 01 Jumper 10 CSEL signal 11 Other method 0 Shall be set to one if Device 0 94 XXXXH Current Advanced Acoustic Management value 15 8 Vendor s Recommended Acoustic Management level 7 0 Current Acoustic Management level 95 99 0000H ...

Page 149: ...that are vendor specific Word Content Description 129 XXXXH Current Set Feature Option Bit assignments 15 4 Reserve 3 Auto reassign 1 enabled 2 Reverting 1 enabled 1 Read Look ahead 1 enabled 0 Write Cache 1 enabled 130 159 XXXXH Reserved 160 254 0000H Reserved 255 XXA5H 15 8 Checksum This value is the two s complement of the sum of all bytes in byte 0 through 510 7 0 Signature ...

Page 150: ...ow When the automatic power down sequence is enabled the drive will enter Standby mode automatically if the time out interval expires with no drive access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Fe...

Page 151: ...st commands immediately The Idle Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1...

Page 152: ...ans that there are no sectors rather than 256 sectors per track H This indicates the number of heads minus 1 per cylinder The minimum is 0 and the maxi mum is 15 The following condition needs to be met to avoid invalid number of cylinders beyond FFFFh Total number of user addressable sectors sector count x H 1 FFFFh The total number of user addressable sectors is described in Identify Device comma...

Page 153: ...y host is not changed Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature V V V V V V V V Error see below Sector Count Sector Count Initial value Sector Number Sector Number Initial value Cylinder Low Cylinder Low Initial value Cylinder High Cylinder High Initial value Device Head 1 1 D Device Head Initial value Command 0...

Page 154: ...he sector may be different if any reads or writes have occurred since the Write Buffer command was issued Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count V V V V V V V V Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device ...

Page 155: ...ates the cylinder number of the first sector to be transferred L 0 In LBA mode this register specifies the transfer of LBA address bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the first sector to be transferred L 0 In LBA mode this register specifies that LBA bits 24 27 is to be transferred L 1 R This indicates the retry bit This bit is ignored Input parameters from the dev...

Page 156: ... 1 Cylinder High Low This indicates the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 157: ...nt register is specified then 65 536 sectors will be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see bel...

Page 158: ...ror Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 159: ...r LBA address bits 23 8 H Starting head number or LBA address bits 27 24 Input parameters from the device on bus release Sector Count Bits 7 3 Tag contain the Tag of the command being bus released Bit 2 REL is set to one Bit 1 I O is cleared to zero Bit 0 C D is cleared to zero Sector Number Cylinder High low H n a SRV Cleared to zero when the device performs a bus release This bit is set to one w...

Page 160: ...plete Sector Count Bits 7 3 Tag contain the Tag of the completed command Bit 2 REL is cleared to zero Bit 1 I O is set to one Bit 0 C D is set to one Sector Number Cylinder High Low H Sector address of unrecoverable error applicable only when an unrecoverable error has occurred SRV Cleared to zero ...

Page 161: ...delivered Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V V Error see below Pre...

Page 162: ... Number HOB 0 LBA 7 0 of the address of the first unrecoverable error applicable only when an unrecoverable error has occurred Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error applicable only when an unrecoverable error has occurred Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error applicable only when an unrecoverable error has occurred Cylin...

Page 163: ...linder Low Current The first sector of the log to be read low order bits 7 0 Cylinder Low Previous The first sector of the log to be read high order bits 15 8 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count H...

Page 164: ...y The value of the General Purpose Logging Version word shall be 0001h A value of 0000h indicates that there is no General Purpose Log Directory The logs at log addresses 80 9Fh shall each be defined as 16 sectors long Log Address Content Feature set Type 00h Log directory N A Read Only 03h Extended Comprehensive SMART error log SMART error logging Ready Only 06h SMART self test log SMART self tes...

Page 165: ...rrors reported by the device These error log data structure entries are viewed as a circular buffer The fifth error shall create an error log structure that replaces the first error log data structure The next error after that shall create an error log data structure that replaces the second error log structure etc Unused error log data structures shall be filled with zeros 12 18 2 3 1 Data format...

Page 166: ...mber register 7 0 1 05h Sector number register 15 8 1 06h Cylinder Low register 7 0 1 07h Cylinder Low register 15 8 1 08h Cylinder High register 7 0 1 09h Cylinder High register 15 8 1 0Ah Device Head register 1 0Bh Command register 1 0Ch Reserved 1 0Dh Timestamp milliseconds from Power on 4 0Eh 18 Description Bytes Offset Reserved 1 00h Error register 7 0 1 01h Sector count register 7 0 See Note...

Page 167: ...log sector The figure below defines the format of each of the sectors that comprise the Extended SMART self test log The Extended SMART self test log sector shall support 48 bit and 28 bit addressing All 28 bit entries contained in the SMART self test log defined in 11 42 6 Self test log data structure on page0203 shall also be included in the Extended SMART self test log with all 48 bit entries T...

Page 168: ... Valid values for the Self test descriptor index are 0 to 18 12 18 3 3 Extended Self test log descriptor entry The content of the self test descriptor entry is shown below Description Bytes Offset Self test number 1 00h Self test execution status 1 01h Power on life timestamp in hours 2 02h Self test failure check point 1 04h Failing LBA 7 0 1 05h Failing LBA 15 8 1 06h Failing LBA 23 16 1 07h Fai...

Page 169: ... transferred L 0 In LBA mode this register contains LBA bits 0 7 L 1 Cylinder High Low This indicates the cylinder number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains LBA bits 24 27 L 1 R This indicates the retry bit This bit is ignored ...

Page 170: ...rent LBA bits 8 15 Low 16 23 High L 1 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 The device internally uses 52 bytes of ECC data on all data written or read from the disk The 4 byte mode of oper ation is provided via an emulation Use of the 52 byte ECC mode is recommended for testing the effectiveness and integrity o...

Page 171: ...f the sector to be transferred L 0 In LBA mode this register contains LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This number is zero unless an unrecoverable error occurs Sector Number This indicates the sector number of the transferred sector L 0 In LBA mode this register contains current LBA bits 0 7 L 1 Cylinder...

Page 172: ...Deskstar T7K250 Hard Disk Drive Specification 158 H This indicates the head number of the transferred sector L 0 In LBA mode this register contains current LBA bits 24 27 L 1 ...

Page 173: ...BA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector...

Page 174: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 175: ...he native max LBA bits 8 15 Low and bits 16 23 High L 1 In CHS mode this register contains the native max cylinder number L 0 H In LBA mode this register contains the native max LBA bits 24 27 L 1 In CHS mode this register contains the native maximum head number L 0 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Erro...

Page 176: ...ax address Cylinder High HOB 1 LBA 47 40 of the address of the Native max address Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current Sector Count HOB 0 Previous HOB 1 Sector Number Current Sector Number HOB 0 V V V V V V V V Previous HOB 1 ...

Page 177: ...s the head number of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit but this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not transferred This will be zero unless an unre coverable error occurs Sector Number This is the sector number of the last transferred sector L 0 I...

Page 178: ... is the cylinder number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 179: ...inder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1...

Page 180: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 181: ...of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the Command Completion Time Limit event if some data transferred is in error O...

Page 182: ...BA space HSE bit 4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream to be read The device shall operate according to the Stream ID set by the Read Stream command Feature Previous CC...

Page 183: ... the command and the RC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the RC bit is set to one when the command is issued and ICRC UNC IDNF ABRT or CCTO error occurs the SE bit shall be set to one the ERR bit sh...

Page 184: ...he device shall stop execution of the command and pro vide ending status with BSY bit cleared to zero the SE bit set to one the ERR bit cleared to zero and report the fact that the Command Completion Time Limit expired by setting the CCTO bit in the error log to one In all cases the device shall attempt to transfer the amount of data requested within the Command Completion Time Limit event if some...

Page 185: ...BA space HSE bit 4 HSE Handle Stream Error specifies that this command starts at the LBA of the last reported error for this stream so the device may attempt to continue its corresponding error recovery sequence where it left off earlier Stream ID bit 0 2 Stream ID specifies the stream to be read The device shall operate according to the Stream ID set by the Read Stream command Feature Previous CC...

Page 186: ... the command and the RC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the RC bit is set to one when the command is issued and ICRC UNC IDNF ABRT or CCTO error occurs the SE bit shall be set to one the ERR bit sh...

Page 187: ...of the first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This is the retry bit this bit is ignored Input parameters from the device Sector Count This is the number of requested sectors not verified This number will be zero unless an unrecoverable error occurs Sector Number This is the sector number of the last transferred sector L 0 In LBA mode this reg...

Page 188: ...Specification 174 In LBA mode this register contains the current LBA bits 8 15 Low and bits 16 23 High L 1 H This is the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 189: ...Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error see below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 P...

Page 190: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 191: ... Register Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 0 0 0 1 Status see below Error Register Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 I...

Page 192: ...ty Disable Password command The device will compare the password sent from this host with that specified in the control word Identifier Zero indicates that the device should check the supplied password against the user pass word stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block ...

Page 193: ...d is to prevent accidental erasure of the device This command does not request the transfer of data Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 1 0...

Page 194: ...ll user data and disables the security mode feature device lock func tion After the completion of this command all the user data will be initialized to zero with a write operation At this time the data write is not verified with a read operation to determine if the data sector is initialized correctly At this time the defective sector information and the reassigned sector information for the devic...

Page 195: ...ever the master password is still stored internally within the device and may be reactivated later when a new user password is set If you execute this command when disabling the security mode feature device lock function the password sent by the host is NOT compared with either the Master Password or the User Password The device then erases all user data The execution time of this command is set i...

Page 196: ...ode Security Set Password Security Unlock Security Disable Password Security Erase Unit Refer to Table 58 Command table for device lock operation on page 92 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cyli...

Page 197: ...command Table 113 Security Set Password Information Identifier Zero indicates that the device should check the supplied password against the user password stored internally One indicates that the device should check the given password against the master password stored internally Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Dat...

Page 198: ...el bits The setting of the Identifier and Security level bits interact as follows Identifier User Security level High The password supplied with the command will be saved as the new user password The security mode feature lock function will be enabled from the next power on The drive may then be unlocked by either the user password or the previously set master password Identifier Master Security l...

Page 199: ...or each password mismatch When this counter reaches zero all password protected commands are rejected until there is a hard reset or a power off Identifier A zero indicates that the device regards Password as the User Password A one indicates that the device regards Password as the Master Password The user can detect if the attempt to unlock the device has failed due to a mismatched password since...

Page 200: ...ameters from the device Sector Number In LBA mode this register contains the current LBA bits 0 7 L 1 Cylinder High Low In LBA mode this register contains the current LBA bits 8 15 Low and bits16 23 High L 1 H In LBA mode this register contains the current LBA bits 24 27 L 1 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Fea...

Page 201: ... released Output parameters to the device D Selected device Input parameters from the device Input from the device as a result of a Service command are described in the command description for the command for which Service is being requested Command Block Output Registers Register 7 6 5 4 3 2 1 0 Data Feature Sector Count Sector Number Cylinder Low Cylinder High Device Head 1 1 D Command 1 1 1 1 0...

Page 202: ...egister Status Register 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 CRC UNC 0 IDN 0 ABT T0N AMN BSY RDY DF DSC DRQ COR IDX ERR 0 0 0 0 0 V 0 0 0 V 0 0 V 02H Enable write cache 03H Set transfer mode based on value in sector count register 05H Enable Advanced Power Management 06H Enable Power up in Standby feature set 07H Power up in Standby feature set device spin up 09H Enable Address Offset mode 42H Enable A...

Page 203: ...wer Management the Sector Count Register specifies the Advanced Power Management level The idle time to Low power idle mode and Low RPM standby mode vary according to the value in Sector Count register as follows When Low power idle mode is the deepest Power Saving mode When Low RPM standby mode is the deepest Power Saving mode and the value in Sector Count register is between 40h and 7Fh Write ca...

Page 204: ...ting to Power on defaults is disabled and the devise receives a soft reset Additional electronics are powered off and the heads are unloaded on the ramp The spindle is still rotated at the full speed The heads are unloaded on the ramp and the spindle is rotated at the 60 65 of the full speed When Feature register is 85h Disable Advanced Power Management the deepest Power Saving becomes nor mal Idl...

Page 205: ...il the next power on or hardware reset The device returns command aborted during Set Max Locked mode or Set Max Frozen mode After a successful command completion Identify Device response words 61 60 shall reflect the maximum address set with this command If the 48 bit Address feature set is supported the value placed in Identify Device response words 103 100 shall be the same as the value placed i...

Page 206: ...de this register is ignored L 0 Cylinder High Low In LBA mode this register contains LBA bits 8 15 Low 16 23 High which is to be set L 1 In CHS mode this register contains cylinder number which is to be set L 0 H In LBA mode this register contains LBA bits 24 27 which is to be set L 1 In CHS mode this register is ignored L 0 Input parameters from the device Sector Number In LBA mode this register ...

Page 207: ...e accepts this command the device is in Set_Max_Unlocked state Table 120 Set Max Set Password data contents Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 0 1 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Devic...

Page 208: ...cted The device remains in this state until a power cycle or the acceptance of a Set Max Unlock or Set Max Freeze Lock command Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Devi...

Page 209: ...itially set to 5 and is decremented for each password mismatch When this counter reaches zero all Set Max Unlock commands are rejected until a hard reset or a power off occurs If the password compare matches the device sets the Set_Max_Unlocked state and all Set Max commands are accepted Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 ...

Page 210: ...ected The following commands are disabled by Set Max Freeze Lock Set Max Address Set Max Set PASSWORD Set Max Lock Set Max Unlock Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature 0 0 0 0 0 0 1 0 Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High D...

Page 211: ...and or the device is in the Set Max Locked or Set Max Frozen state the device shall return command aborted If the device in Address Offset mode receives this command with the nonvolatile option the device returns aborted error to the host The device returns the command aborted for a second non volatile Set Max Address Ext command until next power on or hardware reset Command Block Output Registers...

Page 212: ...1 is not valid when the device is in Address Offset mode Sector Number Current Set Max LBA 7 0 Sector Number Previous Set Max LBA 31 24 Cylinder Low Current Set Max LBA 15 8 Cylinder Low Previous Set Max LBA 39 32 Cylinder High Current Set Max LBA 23 16 Cylinder High Previous Set Max LBA 47 40 Input parameters from the device Sector Number HOB 0 Set Max LBA 7 0 Sector Number HOB 1 Set Max LBA 31 2...

Page 213: ...set is the only way to recover from Sleep Mode Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 0 1 1 0 Status see below Error Register Status Registe...

Page 214: ...R T Read Attribute Values subcommand from the host the device saves any updated Attribute Values to the Attribute Data sectors and then transfer the 512 bytes of Attribute Value information to the host Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature V V V V V V V V Error see below Sector Count V V V V V V V V Sector C...

Page 215: ...ror code specified in Table 137 S M A R T Error Codes on page 212 The S M A R T Disable Operations subcommand disables the Autosave feature along with the S M A R T opera tions of the device Upon the receipt of the subcommand from the host the device asserts BSY enables or disables the Autosave fea ture clears BSY and asserts INTRQ 12 43 1 4 S M A R T Save Attribute Values subcommand D3h This subc...

Page 216: ... a Read Only log sector is specified the device returns ABRT error 12 43 1 8 S M A R T Enable Operations subcommand D8h This subcommand enables access to all S M A R T capabilities within the device Prior to receipt of a S M A R T Enable Operations subcommand Attribute Values are neither monitored nor saved by the device The state of S M A R T either enabled or disabled will be preserved by the de...

Page 217: ... loads 4Fh into the Cylinder Low register and C2h into the Cylinder High register If the device detects a Threshold Exceeded Condition the device loads F4h into the Cylinder Low register and 2Ch into the Cylinder High register 12 43 1 11 S M A R T Enable Disable Automatic Off line subcommand DBh This subcommand enables and disables the optional feature that causes the device to perform the set of ...

Page 218: ...he 12 bytes that make up the information for each Attribute entry in the Device Attribute Data Structure Table 128 Individual Attribute Data Structure Description Byte Offset Format Value Data Structure Revision Number 2 00h binary 0010h 1st Device Attribute 12 02h 1 30th Device Attribute 12 15Eh 1 Off line data collection status 1 16Ah 1 Self test execution status 1 16Bh 1 Total time in seconds t...

Page 219: ...ormalized values The device performs conversion of the raw Attribute Values to transform them into normal ized values which the host can then compare with the Threshold values A Threshold is the excursion limit for a normalized Attribute Value 12 43 2 3 Off Line Data Collection Status The value of this byte defines the current status of the off line activities of the device Bit 7 indicates an Auto...

Page 220: ...ff line subcommand is not implemented 1 S M A R T Enable disable Automatic Off line subcommand is implemented 2 Abort restart off line by host bit 0 The device will suspend off line data collection activity after an interrupting command and resume it after a vendor specific event 1 The device will abort off line data collection activity upon receipt of a new command Bit Definition 0 3 Percent Self...

Page 221: ...rts the S M A R T ENABLE DISABLE ATTRIBUTE AUTOSAVE command 2 15 Reserved 0 12 43 2 8 Error logging capability Bit Definition 7 1 Reserved 0 0 The Error Logging support bit If bit 1 the device supports the Error Logging 12 43 2 9 Self test failure check point This byte indicates the section of self test where the device detected a failure 12 43 2 10 Self test completion time These bytes are the mi...

Page 222: ...e entries in the Individual Attribute Data Structure 12 43 3 3 Attribute ID Numbers Attribute ID Numbers supported by the device are the same as Attribute Values Data Structures 12 43 3 4 Attribute Threshold These values are preset at the factory and are not meant to be changeable 12 43 3 5 Data Structure Checksum The Data Structure Checksum is the two s complement of the result of a simple 8 bit ...

Page 223: ...log sector 12 43 5 1 S M A R T error log version This value is set to 01h 12 43 5 2 Error log pointer This points to the most recent error log data structure Only values 1 through 5 are valid 12 43 5 3 Device error count This field contains the total number of errors The value will not roll over Description Byte Offset S M A R T Logging Version 2 00h Number of sectors in the log at log address 1 1...

Page 224: ... command data structure 12 18h 4th command data structure 12 24h 5th command data structure 12 30h Error data structure 30 3Ch 90 Description Byte Offset Device Control register 1 00h Features register 1 01h Sector count register 1 02h Sector number register 1 03h Cylinder Low register 1 04h Cylinder High register 1 05h Device Head register 1 06h Command register 1 07h Time stamp ms from Power On ...

Page 225: ...re is capable to contain up to 21 descriptors After 21 descriptors has been recorded the oldest descriptor will be overwritten with the new descriptor The self test log index points to the most recent descriptor When there is no descriptor the value is 0 When there are one or more descriptors the value is 1 through 21 Value State x0h Unknown x1h Sleep x2h Standby x3h Active Idle x4h S M A R T Off ...

Page 226: ...d into the Cylinder High and Cylinder Low registers 51h 04h A S M A R T FUNCTION SET command was received by the device with a subcommand value in the Features Regis ter that is either invalid or not supported by this device 51h 04h A S M A R T FUNCTION SET command subcommand other than S M A R T ENABLE OPERATIONS was received by the device while the device was in a S M A R T Disabled state 51h 04...

Page 227: ...tic power down sequence is enabled The time out interval is shown below When the automatic power down sequence is enabled the device will enter the Standby mode automatically if the time out interval expires with no device access from the host The time out interval will be reinitialized if there is a drive access before the time out interval expires Command Block Output Registers Command Block Inp...

Page 228: ... delay while waiting for the spindle to reach operating speed The Standby Immediate command will not affect the auto power down time out parameter Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High ...

Page 229: ...tial Write Buffer and Read Buffer commands access the same 512 byte within the buffer Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Data Feature Error see below Sector Count Sector Count Sector Number Sector Number Cylinder Low Cylinder Low Cylinder High Cylinder High Device Head 1 1 D Device Head Command 1 1 1 0 1 0 0 0 Status ...

Page 230: ... number or LBA address bits 23 8 H Starting head number or LBA address bits 27 24 Input parameters from the device on bus release Sector Count Bits 7 3 Tag contain the Tag of the command being bus released Bit 2 REL is set to one Bit 1 I O is cleared to zero Bit 0 C D is cleared to zero Sector Number Cylinder High Low H n a SRV Cleared to zero when the device performs a bus release This bit is set...

Page 231: ...omplete Sector Count Bits 7 3 Tag contain the Tag of the completed command Bit 2 REL is cleared to zero Bit 1 I O is set to one Bit 0 C D is set to one Sector Number Cylinder High Low H Sector address of unrecoverable error applicable only when an unrecoverable error has occurred SRV Cleared to 0 ...

Page 232: ... 0 Sector Count Previous The number of continuous sectors to be transferred high order bits 15 8 If zero is speci fied in the Sector Count register then 65 536 sectors will be transferred Sector Number CurrentLBA 7 0 Sector Number PreviousLBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low PreviousLBA 39 32 Cylinder High CurrentLBA 23 16 Command Block Output Registers Command Block Input Register...

Page 233: ...or Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 234: ...or Count register then 65 536 sectors will be transferred Sector Number CurrentLBA 7 0 Sector Number PreviousLBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low PreviousLBA 39 32 Cylinder High CurrentLBA 23 16 Cylinder High PreviousLBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature ...

Page 235: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 236: ... Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Device Head Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V V Error see below Previous V V V V V V V V Secto...

Page 237: ...ccessfully when Write Cache is enabled Input parameters from the device Sector Number HOB 0 LBA 7 0 of the address of the first unrecoverable error Sector Number HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 L...

Page 238: ...be written low order bits 7 0 Cylinder Low PreviousThe first of the log to be written high order bits 15 8 If the feature set associated with the log specified in the Sector Number register is not supported or enabled or if the values in the Sector Count Sector Number or Cylinder Low registers are invalid the device shall return com mand aborted If the host attempts to write to a read only log add...

Page 239: ...s the LBA bits 8 15 Low and bits 16 23 High L 1 H This indicates the head number of the sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R The retry bit This bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transferred Sector Number This indicates the sector number of the sector to be transferred L...

Page 240: ...7 L 1 The drive internally uses 52 bytes of ECC on all data read or writes The 4 byte mode of operation is provided by means of an emulation technique As a consequence of this emulation it is recommended that 52 byte ECC mode be used for all tests to confirm the operation of the ECC hardware of the drive Unexpected results may occur if such testing is performed using 4 byte mode ...

Page 241: ...he first sector to be transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 Input parameters from the device Sector Count This indicates the number of requested sectors not transferred The Sector Count will be zero unless an unrecoverable error occurs Sector Number This indicates the sector number of the last transferred sector L 0 In LBA mode this register contains current the...

Page 242: ...Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Input parameters from the device Sector Number HOB 0 LBA 7 0 of the address of the first unrecoverable error Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current V V V V V V V V Error See below Previo...

Page 243: ...able error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 244: ...r Count register then 65 536 sectors shall be transferred Sector Number Current LBA 7 0 Sector Number Previous LBA 31 24 Cylinder Low Current LBA 15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Fea...

Page 245: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 246: ...e transferred L 0 In LBA mode this register contains the LBA bits 24 27 L 1 R This indicates the retry bit this bit is ignored Input parameters from the device Sector Count This indicates the number of requested sectors not transferred This will be zero unless an unrecoverable error occurs Sector Number This indicates the sector number of the last transferred sector L 0 In LBA mode this register c...

Page 247: ...pecification 233 In LBA mode this register contains the current LBA bits 8 15 Low and 16 23 High L 1 H This indicates the head number of the last transferred sector L 0 In LBA mode this register contains the current LBA bits 24 27 L 1 ...

Page 248: ...15 8 Cylinder Low Previous LBA 39 32 Cylinder High Current LBA 23 16 Cylinder High Previous LBA 47 40 Command Block Output Registers Command Block Input Registers Register 7 6 5 4 3 2 1 0 Register 7 6 5 4 3 2 1 0 Data Low Data Low Data High Data High Feature Current Error See below Previous Sector Count Current V V V V V V V V Sector Count HOB 0 Previous V V V V V V V V HOB 1 Sector Number Current...

Page 249: ... HOB 1 LBA 31 24 of the address of the first unrecoverable error Cylinder Low HOB 0 LBA 15 8 of the address of the first unrecoverable error Cylinder Low HOB 1 LBA 39 32 of the address of the first unrecoverable error Cylinder High HOB 0 LBA 23 16 of the address of the first unrecoverable error Cylinder High HOB 1 LBA 47 40 of the address of the first unrecoverable error ...

Page 250: ...mpletion Time Limit event if some data transferred is in error Output parameters to the device Feature Current The number of continuous sectors to be transferred low order bits 7 0 URG bit 7 URG specifies an urgent transfer request The Urgent bit specifies that the command should be completed in the minimum possible time by the device and shall be completed within the specified Command Completion ...

Page 251: ...is stream so the device may attempt to continue its corresponding error recovery sequence where it left earlier Feature Previous CCTL 7 0 The time allowed for the current command s completion is calculated as follows Command Completion Time Limit content of the Feature register Previous Iden tify Device words 99 98 useconds If the value is zero the device shall use the Default CCTL supplied with a...

Page 252: ...d and the WC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the WC bit is set to one when the command is issued and an ICRC UNC IDNF ABRT or CCTO error occurs the SE bit shall be set to one the ERR bit shall be c...

Page 253: ... transferred is in error Output parameters to the device Feature Current URG bit 7 URG specifies an urgent transfer request The Urgent bit specifies that the command should be completed in the minimum possible time by the device and shall be completed within the specified Command Completion Time Limit WC bit 6 WC specifies Write Continuous mode enabled If the Write Continuous bit is set to one the...

Page 254: ...tempt to continue its corresponding error recovery sequence where it left earlier Stream ID bit 0 2 Stream ID specifies the stream being written The device shall operate according to the Stream ID set by the Write Stream command Feature Previous The time allowed for the current command s completion is calculated as follows Command Completion Time Limit content of the Feature register Previous Iden...

Page 255: ...rred during the execution of the command and the WC bit is set to one In this case the LBA returned in the Sector Number registers shall be the address of the first sector in error and the Sector Count registers shall contain the number of consecutive sectors that may contain errors If the WC bit is set to one when the command is issued and an ICRC UNC IDNF ABRT or CCTO error occurs the SE bit sha...

Page 256: ...Deskstar T7K250 Hard Disk Drive Specification 242 ...

Page 257: ...RDY 1 31 sec Hard Reset Device Busy After Hard Reset Bus RESET Signal Asserted Status Register BSY 1 400 ns Device Ready After Hard Reset Bus RESET Signal Asserted Status Register BSY 0 and RDY 1 31 sec Data In Com mand Device Busy After Com mand Code Out OUT To Command Register Status Register BSY 1 400 ns Interrupt DRQ For Data Transfer In Status Register BSY 1 Status Register BSY 0 and DRQ 1 In...

Page 258: ...Deskstar T7K250 Hard Disk Drive Specification 242 ...

Page 259: ...y formatted 11 Caution 3 CE mark 67 Command descriptions 113 Command overhead 15 Command protocol 107 Command table 92 Connector locations 60 Control electronics 9 Corrosion test 54 CSA approval 66 C TICK mark 67 Cylinder allocation 12 13 D Data In commands 107 Data Out Commands 108 Data Reliability 57 Data sheet 11 DC power connector 24 DC power requirements 54 Defect flagging strategy 21 Deviati...

Page 260: ...53 F Fixed disk subsystem 9 Flammability 66 Flush Cache 123 Formatted capacity 11 Functional specification 7 G General 1 General features 5 H Head disk assembly 9 Head disk assembly data 9 Heads unload 61 Humidity 53 I Identification labels 65 Input voltage 54 Interface logic signal levels 29 Interface specification 45 J Jumper pin location 47 Jumper positions 49 Jumper settings 47 ...

Page 261: ...ta commands 110 O Operating modes 20 description 18 Operating shock 63 P Packaging 67 Passwords 89 Performance characteristics 15 Physical dimensions 58 PIO timings 32 Power consumption effiency 56 Power management features 84 Power supply current 55 Preventive maintenance 57 Protected Area 93 R Reassign function 97 References 1 Register set 71 Registers 71 Reset timings 29 ...

Page 262: ... protection 66 Sector Addressing 82 Security Mode Feature Set 88 Shock 62 Signal definitions 25 Specification 47 T Temperature 53 Time out values 241 Timings multi word DMA 34 reset 29 Ultra DMA 35 U UL approval 66 V Vibration 62 W Weight 58 Write Buffer 214 ...

Page 263: ...stered trade marks of their respective companies References in this publication to Hitachi Global Storage Technologies products programs or services do not imply that Hitachi Global Storage Technologies intends to make these available in all countries in which Hitachi Global Storage Technologies operates Product information is provided for information pur poses only and does not constitute a warra...

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