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154

5 . 5 . 7

Color detection registers H and L (CDERH, CDERL)

15

CDG

*

R/W

14

CDG

*

R/W

13

CDG

*

R/W

12

CDG

*

R/W

11

CDG

*

R/W

8

—

—

—

10

CDG

*

R/W

9

—

—

—

Bit:

CDERL:

Initial value:

Read/Write:

7

CDB

*

R/W

6

CDB

*

R/W

5

CDB

*

R/W

4

CDB

*

R/W

3

CDB

*

R/W

0

—

—

—

2

CDB

*

R/W

1

—

—

—

15

—

—

—

14

—

—

—

13

—

—

—

12

—

—

—

11

—

—

—

8

—

—

—

10

—

—

—

9

—

—

—

Bit:

CDERH:

Initial value:

Read/Write:

7

CDR

*

R/W

6

CDR

*

R/W

5

CDR

*

R/W

4

CDR

*

R/W

3

CDR

*

R/W

0

—

—

—

2

CDR

*

R/W

1

—

—

—

Note: * Value is retained.

Color detection registers H and L (CDERH, CDERL) are 16-bit readable/writable registers. When
the display data output from pins DD17 to DD0 matches the values set in these registers, 1 is
output from the CDE pin. Color detection is performed by means of the CDE pin during the
blanking period. Pins DD0 to DD17 all go low during this period. Therefore, if both CDERH and
CDERL are cleared to 0, CDE pin output will go high during the blanking period. Similarly, if
either CDERH or CDERL is not 0, the CDE pin will go low during the blanking period.

Bits 15 to 8, 1, and 0 of CDERH, and bits 9, 8, 1, and 0 of CDERL are reserved. Only 0 should
be written to these bits.

CDERH/L bits CDR, CDG, and CDB retain their values in a reset.

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Summary of Contents for HD64411 Q2

Page 1: ...HD64411 Q2 Quick 2D Graphics Renderer User s Manual SuperH RISC engine Peripheral LSI ADE 602 120 Rev 1 0 7 9 99 Hitachi Ltd ...

Page 2: ...the characteristics and performance of Hitachi s semiconductor products Hitachi assumes no responsibility for any intellectual property claims or other problems that may result from applications based on the examples described herein 5 No license is granted by implication or otherwise under any patents or other rights of any third party or Hitachi Ltd 6 MEDICAL APPLICATIONS Hitachi s products are ...

Page 3: ...or these applications The approach to graphics processing up to now has been to have both geometrical processing and rendering processing carried out by the CPU using large amounts of high speed memory or to use a graphics LSI containing as many embedded algorithms as possible at that time A more desirable approach however is to have geometrical processing handled by the CPU while rendering and di...

Page 4: ...Interface Pins 20 2 3 1 CPU Writes 20 2 3 2 CPU Reads 21 2 3 3 DMA Writes 21 2 3 4 Interrupts 21 2 4 Power Supply Pins 22 2 4 1 Normal Power Supply and PLL Power Supply 22 2 4 2 CPU Power Supply 22 2 5 Display Interface Pins 22 2 5 1 DAC Interface 22 2 5 2 Video Encoder Interface 23 2 5 3 CRT Interface 23 2 6 UGM Interface Pins 23 2 6 1 UGM Access 23 Section 3 Unified Graphics Memory UGM Display F...

Page 5: ... 4 Drawing Commands 75 4 4 1 POLYGON4A 75 4 4 2 POLYGON4B 78 4 4 3 POLYGON4C 81 4 4 4 FTRAP 83 4 4 5 RFTRAP 85 4 4 6 LINEW 87 4 4 7 RLINEW 89 4 4 8 LINE 91 4 4 9 RLINE 93 4 4 10 PLINE 95 4 4 11 RPLINE 98 4 4 12 MOVE 100 4 4 13 RMOVE 102 4 4 14 LCOFS 104 4 4 15 RLCOFS 106 4 4 16 UCLIP 108 4 4 17 SCLIP 110 4 4 18 CLRW 112 4 4 19 JUMP 114 4 4 20 GOSUB 116 4 4 21 RET 118 4 4 22 TRAP 119 4 4 23 NOP3 12...

Page 6: ...HSWR 151 5 5 3 Horizontal Scan Cycle Register HCR 151 5 5 4 Vertical Start Position Register VSPR 152 5 5 5 Vertical Scan Cycle Register VCR 152 5 5 6 Display Off Output Registers H and L DOORH DOORL 153 5 5 7 Color detection registers H and L CDERH CDERL 154 5 6 Rendering Control Registers 155 5 6 1 Command Status Registers H and L CSTRH CSTRL 155 5 7 Input Control Registers 156 5 7 1 Image Data ...

Page 7: ...tics 178 7 5 Timing Charts 188 7 5 1 Input Clocks 188 7 5 2 Reset Timing 190 7 5 3 CPU Read Cycle Timing 191 7 5 4 CPU Write Cycle Timing 192 7 5 5 DMA Write Cycle Timing DMAC Q2 193 7 5 6 Interrupt Output Timing 195 7 5 7 UGM Read Cycle Timing 196 7 5 8 UGM Write Cycle Timing 198 7 5 9 UGM Refresh Cycle Timing 200 7 5 10 Master Mode Display Timing 201 7 5 11 TV Sync Mode Display Timing 202 Append...

Page 8: ...uperH bus utilization is performed by the Q2 This provides the flexibility required for updating algorithms while also improving bus utilization In addition the hardware configuration has been simplified with the inclusion of a built in CPU interface circuit display circuit and memory interface circuit functions previously supported by external circuitry Moreover first time use of UGM unified grap...

Page 9: ...video Figure 1 1 Overview of Q2 System 1 2 Block Diagram Figure 1 2 shows a block diagram of the Q2 The functions of the various blocks in figure 1 2 are as follows Rendering unit Performs fetching and interpretation of the display list on the UGM references the source data on the UGM and output drawing data to the drawing side frame buffer on the UGM Rendering buffer unit Buffers data and address...

Page 10: ... data 60 000 colors and stores it in the UGM RGB YCrCb conversion Converts RGB data 60 000 colors to YCrCb data 60 000 colors and outputs the data Memory interface unit Chip manager CLK0 CLK1 DCLK HSYNC EXHSYNC VSYNC EXVSYNC DD0 DD17 18 MD0 MD15 16 CONTROL 6 MA0 MA11 12 RESET CONTROL A1 A22 22 D0 D15 16 9 CPU interface unit DMA control YUV RGB conversion YUV RGB conversion Rendering buffer unit Di...

Page 11: ...on One 16 bit data bus type 4 Mbit EDO page mode DRAM Monochrome binary source Color multi valued source area Monochrome pattern binary work area Minimum configuration 4M 16 bit EDO DRAM POLYGON Display list 16 bit instructions Figure 1 3 Reduced System Size Through Use of UGM Architecture Unified system bus interface A CPU interface circuit is incorporated to provide a unified interface This enab...

Page 12: ...d drawing is forcibly terminated midway Auto rendering mode Mode in which display switching is not performed until drawing ends If drawing does not end within one frame drawing is continued without interruption and frame switching is performed at the frame boundary immediately after drawing is completed Manual display change mode Mode in which display frame switching and the start of drawing are c...

Page 13: ...rawing a drawing method using only write operations is used to improve drawing performance 1 3 3 Upgradability Algorithm Upgrading In the Q2 s drawing system algorithms for coordinate conversion etc are executed by the SuperH using a systematized data base containing coordinates and other data and the results are represented in graphical form Thus the graphics for a variety of shapes can be implem...

Page 14: ...riate Q2 and SuperH models for his application The user s drawing system can also be upgraded as necessary by changing the Q2 or SuperH combination Consistency of Application Interface The Q2 s carefully selected drawing commands are of four kinds four vertex surface drawing line drawing work surface drawing and work line drawing This makes it possible to reduce the parts dependent upon drawing co...

Page 15: ... dots standard size in interlace video operation CRT scanning system Non interlace interlace interlace sync video External synchronization Master TV synchronization Display colors 256 colors selectable from 260 000 or 65 536 colors Drawing functions Drawing commands Drawing related 4 vertex surface drawing line drawing work surface drawing work line drawing Register setting related Current pointer...

Page 16: ...upt output Sync detection frame detection DMA transfer end command error vertical blanking command end command abort Supported SuperH Directly connectable to 3 3 V or 5 V operation SuperH Unified graphics memory 16 bit bus width EDO DRAM Minimum 4 Mbits choice of 4 Mbits 1 4 Mbits 2 16 Mbits 1 16 Mbits 2 Display RGB YCrCb conversion 16 bit input R 5 G 6 B 5 16 bit output 4 2 2 8 bits each for Y Cr...

Page 17: ...10 ...

Page 18: ...H interface Power supply HD64411 FP 144 Display interface UGM interface MODE0 2 CLK0 CLK1 RESET CAP0 TEST A1 A22 D0 D15 CS0 CS1 RD WE0 WE1 DACK DREQ WAIT IRL VCC GND PLL VCC PLL GND CPU VCC CPU GND DD0 DD17 DCLK CSYNC FCLK HSYNC EXHSYNC VSYNC EXVSYNC DISP CDE ODDF MA0 MA11 MD0 MD15 MWE MRAS0 MRAS1 MLCAS MUCAS MOE Figure 2 1 Overview of Q2 Pins ...

Page 19: ...AP0 PLLVCC CS0 CS1 RD WE0 WE1 DACK MODE0 MODE1 MODE2 TEST RESET 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 FCLK VCC5 CLK1 GND8 MA11 MA10 MA9 MA8 MA7 GND7 MA6 MA5 MA4 MA3 VCC4 MA2 MA1 MA0 MOE GND6 MUCAS MLCAS MRAS1 MRAS0 MWE MD15 VCC3 MD14 MD13 GND5 MD12 MD11 MD10 MD9 MD8 MD7 144 143 142 141 140 139 138 137 136 135 134 133 13...

Page 20: ...n CPU A1 39 Input CPU address 1 3V 5V CPU I F interface A2 40 Input CPU address 2 3V 5V CPU I F A3 42 Input CPU address 3 3V 5V CPU I F A4 43 Input CPU address 4 3V 5V CPU I F A5 44 Input CPU address 5 3V 5V CPU I F A6 45 Input CPU address 6 3V 5V CPU I F A7 46 Input CPU address 7 3V 5V CPU I F A8 47 Input CPU address 8 3V 5V CPU I F A9 48 Input CPU address 9 3V 5V CPU I F A10 49 Input CPU address...

Page 21: ...D8 13 Input output CPU data 8 3V 5V CPU I F D9 14 Input output CPU data 9 3V 5V CPU I F D10 15 Input output CPU data 10 3V 5V CPU I F D11 17 Input output CPU data 11 3V 5V CPU I F D12 18 Input output CPU data 12 3V 5V CPU I F D13 20 Input output CPU data 13 3V 5V CPU I F D14 21 Input output CPU data 14 3V 5V CPU I F D15 22 Input output CPU data 15 3V 5V CPU I F CS0 26 Input Chip select 0 UGM 3V 5V...

Page 22: ...ta output 12 5 V output specification DD13 136 Output Display data output 13 5 V output specification DD14 138 Output Display data output 14 5 V output specification DD15 139 Output Display data output 15 5 V output specification DD16 140 Output Display data output 16 5 V output specification DD17 141 Output Display data output 17 5 V output specification DCLK 111 Output Display clock output 5 V o...

Page 23: ...cation MA10 103 Output Memory address 10 5 V output specification MA11 104 Output Memory address 11 5 V output specification MD0 64 Input output Memory data 0 5 V input output specification MD1 65 Input output Memory data 1 5 V input output specification MD2 66 Input output Memory data 2 5 V input output specification MD3 67 Input output Memory data 3 5 V input output specification MD4 68 Input ou...

Page 24: ...t signal 1 5 V output specification MLCAS 87 Output Lower column select signal 5 V output specification MUCAS 88 Output Upper column select signal 5 V output specification MOE 90 Output Memory read pulse 5 V output specification Power supply VCC1 41 Power supply Buffer internal VDD 5 V input specification VCC2 71 Power supply Buffer internal VDD 5 V input specification VCC3 82 Power supply Buffer ...

Page 25: ...nal VSS GND4 69 Ground Internal VSS GND7 99 Ground Internal VSS GND10 116 Ground Internal VSS GND12 129 Ground Internal VSS PLL VCC 25 Power supply Multiplication circuit VDD 5 V input specification PLL GND 23 Ground Multiplication circuit VSS CPU VCC1 4 Power supply CPU IO unit buffer VDD 3 V 5 V input specification CPU VCC2 16 Power supply CPU IO unit buffer VDD 3 V 5 V input specification CPU G...

Page 26: ...he external clock is duty free The internal operating clock has twice the frequency of the external input clock 3 MODE2 L MODE1 H MODE0 L Normal operation state Multiplication on The external clock is duty free The internal operating clock has four times the frequency of the external input clock 4 MODE2 L MODE1 H MODE0 H Normal operation state Multiplication off The external clock must have a 50 d...

Page 27: ...y to the Q2 s CLK0 pin so that the CPU and Q2 operate on clocks with the same frequency and the same phase clock synchronous interface or when the Q2 multiplication factor is N input a clock to the CLK0 pin such that the N CLK0 frequency is higher than that of the clock output from the CK pin so that the Q2 s WE0 WE1 and RD signal high level width specifications are satisfied clock asynchronous in...

Page 28: ... the data bus The data on the data bus is then latched internally by the Q2 on the rise of the RD signal and transferred to the UGM When DMA writes are performed using a display list or binary source as the data the DMA mode is set to 01 When DMA writes are performed using YUV data as the data the DMA mode is set to 11 The Q2 accepts data in word units In DMA mode the Q2 does not output hardware w...

Page 29: ...riate Connect 5 V for an SH703X SH 1 SH7064 SH 2 or SH704X SH 2 CPU and 3 3 V for an SH7708 SH3 CPU When a 3 3 V CPU power supply is used the order of powering on is normal power supply and PLL power supply 5 V first followed by the CPU power supply 3 3 V The order of powering off is CPU power supply 3 3 V first followed by the PLL power supply 5 V The device may be damaged if this order is not fo...

Page 30: ...rface Outputs the horizontal sync signal and vertical sync signal the DISP signal indicating display synchronization and the ODDF signal that indicates whether the current field is even or odd for interlace control When synchronization is coordinated with an external device TV or video recorder the horizontal sync vertical sync and ODDF signals are input In a reset the HSYNC VSYNC and ODDF pins go...

Page 31: ...24 ...

Page 32: ... and is used to control display data output and generate horizontal and vertical sync signals The Q2 has a display dot clock divider that enables a x1 or x2 multiple of the dot rate to be input at the CLK1 pin The relationship between the clocks and operating frequencies is summarized in table 3 1 Table 3 1 Input Clocks and Operating Frequencies Clock Input Pin Clock Type Operating Mode CLK0 One o...

Page 33: ...cted to the Q2 graphics memory is used for the following purposes 1 Frame buffers Q2 drawing area and display area 2 Display list command list Area that stores the Q2 drawing command list The Q2 fetches commands from this area while carrying out drawing operations 3 Source areas work areas etc Used as the source area that stores painting patterns and font data the FTRAP command drawing area and so...

Page 34: ... can access the UGM in two ways via CPU software or via the DMAC When the CPU accesses the UGM the UGM address is input directly to the Q2 s A1 A22 pins and the CS0 pin is driven low Therefore a UGM address in the range specified by the memory mode register should be input to the Q2 s A1 A22 pins For example when using one 4 Mbit memory as the UGM the Q2 s A19 A22 pins must go low when the UGM is ...

Page 35: ...phics memory addresses are controlled by the Q2 s built in address counter However only cycle steal mode can be used as the bus mode UGM Access by Q2 EDO page mode DRAM can be connected to the Q2 as UGM Use of this memory enables the Q2 to perform memory access in one cycle operating clock units The memory configuration consists of one or two 256 kword 16 bit 4 Mbit DRAMs and one or two 1 Mword 16...

Page 36: ...s 8 bits H 00 Lower byte H 00 Upper byte H 01 Lower byte H 0F Upper byte H F0 Lower byte H F0 Upper byte H F1 Lower byte H FF Upper byte 16 lines Figure 3 3 Configuration of One Memory Unit 512 Bytes 2 16 bits pixel multi valued source multi valued destination 16 words 16 bits H 00 H 01 H 0F H F0 H F1 H FF 16 lines Figure 3 3 Configuration of One Memory Unit 512 Bytes 3 Figures 3 4 to 3 8 show sam...

Page 37: ...Frame buffers 0H 0H 20000H 40000H 44000H Display data Work area exclusive use of 32 lines Multi valued source binary source display list selection Display data multi valued source binary source display list selection Multi valued source area Work area Display list binary source area 1 4 Mbits 2 4 Mbits Physical address Figure 3 4 Memory Map Example 1 Screen Size at 8 Bits Pixel 320 240 Equivalent ...

Page 38: ...0000H 88000H Display data Work area exclusive use of 32 lines Multi valued source binary source display list selection Display data multi valued source binary source display list selection 2 4 Mbits Multi valued source area Work area Display list binary source area 511 767 639 F0 F1 1 16 Mbits Physical address Figure 3 5 Memory Map Example 2 Screen Size at 8 Bits Pixel 640 240 Equivalent ...

Page 39: ...me buffers 0H 0H 80000H 100000H 110000H Display data Work area exclusive use of 64 lines Multi valued source binary source display list selection Display data multi valued source binary source display list selection 1 16 Mbits Multi valued source area Work area Display list binary source area Physical address Figure 3 6 Memory Map Example 3 Screen Size at 8 Bits Pixel 640 480 Equivalent ...

Page 40: ...start address F0 start address F1 start address Work area start address Display list start address F0 F1 Frame buffers 0H 0H 40000H 80000H 84000H Multi valued source area Work area Display list binary source area Display data Work area exclusive use of 16 lines Multi valued source binary source display list selection Display data multi valued source binary source display list selection 2 4 Mbits 0...

Page 41: ...100000H 200000H 210000H Display data Work area exclusive use of 32 lines Multi valued source binary source display list selection Display data multi valued source binary source display list selection 2 16 Mbits Multi valued source area Work area Display list binary source area Physical address Figure 3 8 Memory Map Example 5 Screen Size at 16 Bits Pixel 640 480 Equivalent ...

Page 42: ...g is completed In manual display change mode the Q2 performs a frame change once only at the frame change timing following issuance by the SuperH of a frame change directive to the Q2 These modes are specified by the double buffering mode bits DBM in the system control register Normally when double buffering control is performed frame changes can be performed according to the relevant mode by dete...

Page 43: ... VBK flag Vertical blanking flag bit 11 of status register SR Interrupt handling F1 display list transfer Display screen F0 Display screen F1 1st frame 2nd frame Drawing destination F1 Drawing to F1 aborted Drawing destination F0 VSYNC non interlace operation Q2 operation CPU operation Drawing start Interrupt by VBK flag Drawing start Interrupt by VBK flag Figure 3 9 Operation in Auto Display Chan...

Page 44: ...ay screen F0 1st frame 2nd frame 3rd frame Drawing destination F1 Display screen F1 Drawing destination F0 VSYNC non interlace operation Q2 operation CPU operation Interrupt by VBK flag Drawing start Interrupt is generated by VBK flag but is ignored as command has not finished Interrupt by TRA flag Display switching is performed at frame boundary immediately after end of drawing Interrupt by VBK f...

Page 45: ...ftware or by setting the start address of FB0 or FB1 in the display start address register indicated by DBF in SR The start of drawing is controlled by the RS bit in SYSR Interrupts by means of the VBK flag and TRA flag in SR are used for the control timing An outline of operation when using the DC bit in this mode is shown in figure 3 11 When switching from this mode to another double buffering c...

Page 46: ...screen F0 1st frame 2nd frame 3rd frame Drawing destination F1 Display screen F1 Drawing destination F0 VSYNC non interlace operation Q2 operation CPU operation Drawing start Interrupt is generated by VBK flag but is ignored as command has not finished Drawing start Interrupt by VBK flag Interrupt by TRA flag Display area change DC bit is set and screen is switched at next frame boundary Interrupt...

Page 47: ...word 2 1 bit pixel data 0 0 15 D15 to D0 Pixel no 14 15 14 1 word Note The pixel number runs from 0 upward from the left to right side of the screen 3 8 bit pixel data 0 15 1 D15 to D0 Pixel no 8 7 0 1 word 4 16 bit pixel data 0 15 D15 to D0 1 word 1 pixel 5 RGB data 16 bit pixel data B 5 bits G 6 bits R 5 bits 0 15 D15 to D0 11 10 5 4 1 word ...

Page 48: ...rd 8 7 V0 0 15 Y2 D15 to D0 Image data 3rd word 8 7 U2 0 15 Y3 D15 to D0 Image data 4th word 8 7 V2 0 15 Yn 1 D15 to D0 Image data nth word 8 7 Vn 2 1 word Data flow n Even number 7 YUV data YUV data uses a raster as the basic unit The data configuration for one raster consists of the initial value in the first two words and compressed image data in the remaining words ...

Page 49: ... 7 4 3 12 11 4 3 12 11 4 3 12 11 1 word 0 15 D15 to D0 Image data 4th word 8 7 1 word 0 15 D15 to D0 Image data nth word 8 7 1 word Data flow Color Palette Register Color Data Configuration The color palette register color data configuration is shown below MSB R 6 bits 0 LSB 15 D15 to D0 Register address Even word 8 7 MSB 2 1 B 6 bits G 6 bits 0 LSB 15 Odd word 10 9 8 7 MSB LSB 2 1 1 word ...

Page 50: ...d Note The pixel number runs from 0 upward from the left to right side of the screen 3 8 bit pixel data 0 15 1 D15 to D0 Pixel no 8 7 0 1 word 4 16 bit pixel data 0 15 D15 to D0 1 word 1 pixel 5 RGB data 16 bit pixel data B 5 bits G 6 bits R 5 bits 0 15 D15 to D0 11 10 5 4 1 word Output Color Data Configurations Q2 Display Monitor Output data configurations are shown below ...

Page 51: ...DD0 17 R 6 bits B 6 bits G 6 bits MSB LSB MSB LSB MSB LSB 18 bits 2 18 bit data in case of independent format Frame buffer bits 15 to 11 are output to DD17 to DD13 and bits 10 to 0 are output to DD11 to DD1 0 12 DD17 to DD0 16 bits pixel 18 bits 17 0 0 3 YC data When the frame buffer is 16 bits pixel and a color palette is not used YC data uses a 4 2 2 format Cr and Cb data is horizontally reduced...

Page 52: ...bits 0 1716 8 7 Yn 1 8 bits 0 Crn 2 8 bits Assuming an even number for n and an 18 bit word Color Data Format Conversion YUV YUV to RGB conversion The specifications of the function for converting YUV or YUV data in main memory to RGB data are shown in figure 3 12 The Q2 converts YUV or YUV data transferred from the CPU to RGB data and stores it in the UGM source area The converted RGB data is use...

Page 53: ...e Figure 3 13 RGB to YC conversion The Q2 can convert RGB data in the frame buffers to YC data before outputting it The display mode register DSMR contains a conversion enable bit the YCM bit If this bit is modified during display several pixels of abnormal data will be output This bit should therefore only be modified outside the display period 3 3 4 Display Functions The Q2 has functions for out...

Page 54: ...re making the display parameter register settings Figure 3 14 shows the display timing The display screen is defined by the variables shown in table 3 3 The number of rasters in one VSYNC cycle should be set in vc vsw ys and yw regardless of the display mode register scan mode HSYNC EXHSYNC Display area VSYNC EXVSYNC hsw hc xw xs vc yw vsw ys Figure 3 14 Display Timing ...

Page 55: ...splay start position register DSWR VDS VDS ys ys 4 016 Vertical display end position register DSWR VDE VDE ys yw ys yw 017 Horizontal sync pulse width register HSWR HSW hsw 1 hsw 1 018 Horizontal scan cycle register HCR HC hc 1 hc 019 Vertical sync position register VSPR VSP vc vsw vc vsw 01A Vertical scan cycle register VCR VC vc vc 2 Notes 1 In all scanning modes the settings of bits VDS VDE VSP...

Page 56: ... modes the setting is VDS8 0 1 5 Use a value of 4 or more for DSX 6 When the EXHSYNC cycle is an even multiple of CLK1 7 When the EXHSYNC cycle is an odd multiple of CLK1 Table 3 3 Variables Defined by Display Screen Variable Description Unit hc Horizontal scan cycle Dot clock hsw Horizontal sync pulse width Dot clock xs Interval between HSYNC rise and display screen horizontal display start posit...

Page 57: ...e sync mode or interlace sync video mode as the scanning system The mode setting is made in the SCM scan mode bits in the display mode register DSMR In non interlace mode one frame is composed of one field In interlace sync mode one frame is composed of two fields even and odd in which the same data is displayed In interlace sync video mode also one frame is composed of two fields even and odd but...

Page 58: ... 03 04 05 06 07 08 09 Interlace mode 00 01 02 03 04 05 06 07 08 09 00 02 04 06 08 0A 0C 0E 10 12 Interlace sync video mode 01 03 05 07 09 0B 0D 0F 11 13 Raster scanned in odd field Raster scanned in even field Figure 3 15 Examples of Raster Scan Control Display ...

Page 59: ...is output in synchronization with vertical and horizontal sync signals EXHSYNC and EXVSYNC input from an external source The Q2 outputs display data on the basis of the fall of the EXHSYNC signal and the rise of the EXVSYNC signal In this mode the horizontal sync signal vertical sync signal and clock from the sync signal generator should be input at the EXHSYNC EXVSYNC and CLK1 pins respectively S...

Page 60: ...quence in this case is as follows detection of malfunction set this mode switch CLK1 to a clock supplied by a different system then set master mode Refresh Control The number of refresh cycles for the UGM connected to the Q2 is set in bits REF3 0 refresh cycle count in the display mode register DSMR Bit 3 REF3 Bit 2 REF2 Bit 1 REF1 Bit 0 REF0 Operation 0 0 0 0 Refresh timing is not output Refresh ...

Page 61: ... Size 4 Mbit 1 4 Mbit 2 16 Mbit 1 16 Mbit 2 320 240 5 5 640 240 5 5 5 640 480 3 3 The Q2 supports CAS before RAS refresh mode The refresh cycles set in bits REF3 0 are executed from the fall of the DISP signal Display Timing The relationship between the display control register settings and the display signals is shown in figure 3 17 ...

Page 62: ...55 CLK1 ODDF VSYNC interlace operation Odd field Even field DISP VSYNC non interlace operation HSYNC CSYNC DCLK DD 0 to DD17 HC HSW HDE 1 2HC HDS VC VSP Figure 3 17 Display Timing ...

Page 63: ... States Initial states are undefined Registers undefined I O pins undefined Output pins low high output 3 4 2 Reset State when RESET is Driven Low Registers After a reset the Q2 s internal registers are initialized as shown in table 3 5 ...

Page 64: ... 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ISAR IDSR 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Address 000 001 002 003 004 005 006 007 R W R W Register Name Abbrevia tion R W R W R W R W R W R W 1 CS1 0 System control Status Status register clear Interrupt enable Memory mode Display mode Rendering mode Input data conversion mode SYSR SR SRCR IER MEMR DSMR R...

Page 65: ...ates After Reset I O pins Input state D0 D15 VSYNC EXVSYNC HSYNC EXHSYNC ODDF Output state low level output MD0 MD15 Output pins Low level output DISP CDE DD0 DD17 High level output DREQ IRL WAIT Low high level output CSYNC DCLK FCLK MA0 MA11 MWE MRAS0 MRAS1 MLCAS MUCAS MOE ...

Page 66: ...se four vertex surface drawing and line drawing commands which draw at rendering coordinates and work surface drawing and work line drawing commands which draw at work coordinates There are also register setting sequence control and drawing end commands In addition line drawing and trapezoid files have absolute coordinate and relative coordinate specification commands Table 4 1 lists the drawing c...

Page 67: ... with line type specification Draws polygonal line with line type pattern from start coordinates through nodal coordinates PLINE Pattern reference polygonal line drawing absolute coordinate specification RPLINE Pattern reference polygonal line drawing relative coordinate specification Work surface drawing FTRAP Trapezoid paint Performs binary EOR painting of trapezoid with left side parallel to Y ...

Page 68: ...that can be specified depend on the command Rendering coordinate system The position of all coordinate system origins excluding binary source coordinates can be assigned to the pixel position at which x 0 and y is a multiple of 128 counting from the start of the unified graphics memory UGM in pixel units Rendering coordinates 2 dimensional coordinate system These are the coordinates at which the Q...

Page 69: ...erenced With a POLYGON4 type command work data may be referenced Rendering attributes Seven kinds of attribute specifications can be made work WORK clipping CLIP transparent TRNS source style STYL net drawing NET source half HALF and even odd select EOS The attributes that can be specified depend on the command 4 2 Command Fetching The Q2 carries out drawing operations while performing fetches fro...

Page 70: ...tes Rendering Coordinates The size of the coordinate system is fixed as shown in figure 4 2 The correspondence to the frame buffers is also fixed but depends on the installed memory capacity and screen size Make the appropriate selection with the rendering mode register In an area other than one containing a frame buffer although drawing operations are performed nothing is written Rendering coordi...

Page 71: ...t address The maximum coordinate system size is represented by 1024 1024 positive coordinates as shown in figure 4 3 but the size depends on the installed memory capacity screen size and multi valued source area start address Depending on the multi valued source start address this coordinate system may entirely or partially overlap another coordinate system MAX 1023 MAX 1023 0 Figure 4 3 Multi Val...

Page 72: ...ddress The size of the figure is specified by POLYGON4B command parameters TDX and TDY The horizontal width TDX setting can only be made in multiples of 8 pixels TDX TDY Binary source space and display list space Source address word Figure 4 4 Binary Source Coordinates Binary Work Coordinate System The work coordinate system corresponds on a one to one basis to the rendering coordinate system Ther...

Page 73: ...xel 512 or 1024 pixels specified by the MWX bit in the rendering mode register REMR Examples are shown in figures 4 6 and 4 7 The memory capacity required for the binary work area is the number of pixels specified by the MWX bit the number of pixels along the Y axis 8 bytes 0 511 Work area Display list and binary source area Work area start address 40000H Display list start address 44000H 512 544 ...

Page 74: ...r source are POLYGON4A POLYGON4B PLINE and RPLINE Drawing commands that do not reference the transfer source are POLYGON4C LINE RLINE FTRAP RFTRAP CLRW LINEW and RLINEW With drawing operations that reference the transfer source there are two reference data formats multi valued source data and binary source data Of the commands that do not reference the transfer source POLYGON4C LINE RLINE LINEW an...

Page 75: ...OLYGON4B POLYGON4B POLYGON4C Rendering result Transparent mode Figure 4 8 Example of POLYGON4 Transfer Data Combinations Multi Valued Source Data Multi valued source data is defined as multi valued source coordinates 2 dimensional coordinates However the horizontal width TDX is specified in multiples of 8 pixels The configuration of multi valued source data is shown in figure 4 9 ...

Page 76: ... multiples of 8 pixels 1 byte units an example of binary source data is shown in figure 4 10 A binary source is used for the definition of character data and line type data When drawing 0s are converted to COLOR0 data and 1s to COLOR1 data in transparent mode only 1s are converted to COLOR1 data for drawing TDY TDX LSB LSB MSB Example of kanji font as binary source TDX 24 TDY 24 Data H 1C00 H 0E07...

Page 77: ...g parameters COLOR COLOR0 COLOR1 LINE COLOR0 and LINE COLOR1 When the Q2 is used for 8 bit pixel operation the same color palette number is defined in the upper 8 bits and lower 8 bits by the drawing parameter color specification When the Q2 is used for 16 bit pixel operation the R G and B values are defined directly by the drawing parameter color specification However with LINEW and RLINEW 0 or 1...

Page 78: ... be used are POLYGON4A POLYGON4B and POLYGON4C with other commands the work specification bit should be cleared to 0 Clipping Specification CLIP The Q2 can perform clipping area management There are two kinds of clipping area a system clipping area designated by the SCLIP command and a user clipping area designated by the UCLIP command The system clipping area is a rectangular area for prescribing...

Page 79: ...are not drawn The transparency specification can be used with the POLYGON4A POLYGON4B PLINE and RPLINE commands it is invalid for other commands Source Style Specification STYL When drawing a rectangle the STYL bit can be used to select on an individual drawing command basis whether the source data is to be enlarged or reduced or referenced repeatedly If no style specification is made the source d...

Page 80: ...LINE RLINE PLINE and RPLINE commands it is invalid for other commands Source Half Drawing Specification HALF The HALF bit can be used to select whether all or only half of the source data is to be referenced When the source half drawing specification is selected only EOS 0 even number 1 odd number data is referenced from the source starting point Thus only half of the source data in the horizontal...

Page 81: ...eferencing with half drawing specification HALF 1 EOS 0 Source data Starting point Drawing data Odd number referencing with half drawing specification HALF 1 EOS 1 Figure 4 15 Examples of Even Odd Select Specifications ...

Page 82: ...cing a multi valued 8 or 16 bit pixel source Command Format 15 DRAW MODE CODE 0 DY4 DX4 DY3 DX3 DY2 DX2 DY1 DX1 Fixed at 0 Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension TDY TDX TYS TXS 1 Code B 00000 2 Rendering Attributes ...

Page 83: ...rizontally but diagonal scanning may be used in the drawing depending on the shape In diagonally scanned drawing double writing occurs to fill in gaps When repeated source referencing is selected as a rendering attribute STYL 1 the source is not enlarged or reduced but is referenced repeatedly When work referencing is selected as a rendering attribute WORK 1 transfer is performed while referencing...

Page 84: ... DX1 DY1 DX4 DY4 DX2 DY2 DX3 DY3 No work specification Work specification provided DX1 DY1 DX4 DY4 Rendering coordinates DX2 DY2 DX3 DY3 TDX TDY TXS TYS Multi valued source coordinates DX1 DY1 DX4 DY4 Work coordinates DX2 DY2 DX3 DY3 ...

Page 85: ... source Command Format DRAW MODE CODE 15 0 COLOR 1 COLOR 0 DY4 DX4 DY3 DX3 DY2 DX2 DY1 DX1 TDY TDX SOURCE ADDRESS L SOURCE ADDRESS H Fixed at 0 Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension 1 Code B 00001 2 Rendering Attributes ...

Page 86: ... or 16 bit pixel color specifications Description Transfers binary 1 bit pixel source data to any quadrilateral rendering area expanding the data to the colors specified by parameters COLOR0 and COLOR1 The source is always scanned horizontally but diagonal scanning may be used in the drawing depending on the shape In diagonally scanned drawing double writing occurs to fill in gaps When repeated so...

Page 87: ...urce coordinates Binary source 0 data is transparent Transparent mode TRNS 1 Non transparent mode TRNS 0 COLOR 0 COLOR 1 COLOR 1 DX1 DY1 DX4 DY4 Rendering coordinates DX2 DY2 DX3 DY3 DX1 DY1 DX4 DY4 Rendering coordinates DX2 DY2 DX3 DY3 ...

Page 88: ...tension Sign extension Sign extension Sign extension Sign extension 1 Code B 00010 2 Rendering Attributes Reference Data Drawing Destination Multi Valued Source Binary Source Binary Work Specified Color Rendering Work O O Draw Mode Reserved CLIP Reserved NET EOS Reserved WORK Fixed at 0 Fixed at 0 Fixed at 0 O Fixed at 0 O O Fixed at 0 Fixed at 0 Fixed at 0 O O Can be used Referenced depending on ...

Page 89: ...meter When work referencing is selected as a rendering attribute WORK 1 transfer is performed while referencing work area data for the same coordinates as the rendering coordinates Example COLOR DX1 DY1 DX4 DY4 Rendering coordinates DX2 DY2 DX3 DY3 No work specification Specified color DX1 DY1 DX4 DY4 Rendering coordinates DX2 DY2 DX3 DY3 DX1 DY1 DX4 DY4 Work coordinates DX2 DY2 DX3 DY3 Work speci...

Page 90: ...ta Drawing Destination Multi Valued Source Binary Source Binary Work Specified Color Rendering Work O Draw Mode Reserved CLIP Reserved Fixed at 0 Fixed at 0 Fixed at 0 O Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 O Can be used Cannot be used 3 Command Parameters n n 2 to 65 535 Number of vertices DXL Lefthand side coordinate DXn n 2 to 65 535 Absolute coordinate D...

Page 91: ...side with X DXL as the left hand side and with top and bottom bases parallel to the X axis Bottom base drawing is not performed and so the border should be drawn using the LINEW command Set the minimum value of DX1 to DXn as DXL Example DXL Painting order DXL DXL DXL DXL DX1 DY1 0 0 n 5 DXL Work coordinates DX2 DY2 DX3 DY3 DX4 DY4 Order of Listing FTRAP Parameters n DXL DX1 DY1 DX2 DY2 DX3 DY3 DX4...

Page 92: ... Valued Source Binary Source Binary Work Specified Color Rendering Work O Draw Mode Reserved CLIP Reserved Fixed at 0 Fixed at 0 Fixed at 0 O Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 O Can be used Cannot be used 3 Command Parameters n n 1 to 65 535 Number of vertices DXL Lefthand side coordinate DXn DYn n 1 to 65 535 Relative coordinates ...

Page 93: ...ft DX DY from the current pointer XC YC as the right hand sides and with top and bottom bases parallel to the X axis at work coordinates using binary EOR Bottom base drawing is not performed The final coordinate point is stored as the current pointer XC YC Example DXL Painting order DXL DXL DXL XC YC 0 0 When n 3 DXL Work coordinates DX3 DX2 DX1 DY1 DY2 DY3 XC DX1 DX2 DX3 YC DY1 DY2 DY3 XC DX1 DX2...

Page 94: ... Destination Multi Valued Source Binary Source Binary Work Specified Color Rendering Work O Draw Mode Reserved CLIP Reserved EOS Reserved Fixed at 0 Fixed at 0 Fixed at 0 O Fixed at 0 Fixed at 0 O Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 O Can be used Can be used EOS reference Cannot be used 3 Command Parameters n n 2 to 65 535 Number of vertices DXn n 2 to 65 535 Absolute coordinate DYn n 2 to...

Page 95: ... 1 to vertex n DXn DYn 0 drawing or 1 drawing is selected with the drawing mode EOS bit Drawing is performed at work coordinates with 0 when EOS 0 and at work coordinates with 1 when EOS 1 Used for polygon painting drawn figure border drawing at work coordinates Note 8 point drawing is used Example DX2 DY2 DX3 DY3 DX1 DY1 0 0 n 3 Work coordinates ...

Page 96: ...urce Binary Source Binary Work Specified Color Rendering Work O Draw Mode Reserved CLIP Reserved EOS Reserved Fixed at 0 Fixed at 0 Fixed at 0 O Fixed at 0 Fixed at 0 O Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 O Can be used Can be used EOS reference Cannot be used 3 Command Parameters n n 1 to 65 535 Number of vertices DXn DYn n 1 to 65 535 Relative coordinates ...

Page 97: ...DY from the current pointer XC YC 0 drawing or 1 drawing is selected with the drawing mode EOS bit Drawing is performed at work coordinates with 0 when EOS 0 and at work coordinates with 1 when EOS 1 The final coordinate point is stored as the current pointer XC YC Used for polygon painting drawn figure border drawing at work coordinates Note 8 point drawing is used Example XC DX1 YC DY1 XC DX1 DX...

Page 98: ... extension Sign extension 1 Code B 01100 2 Rendering Attributes Reference Data Drawing Destination Multi Valued Source Binary Source Binary Work Specified Color Rendering Work O O Draw Mode Reserved CLIP Reserved NET EOS Reserved Fixed at 0 Fixed at 0 Fixed at 0 O Fixed at 0 O O Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 O Can be used Cannot be used ...

Page 99: ... vertices DXn n 2 to 65 535 Absolute coordinate DYn n 2 to 65 535 Absolute coordinate Description Draws a polygonal line from vertex 1 DX1 DY1 through vertex 2 DX2 DY2 vertex n 1 DXn 1 DYn 1 to vertex n DXn DYn Note 8 point drawing is used Example DX2 DY2 DX3 DY3 DX1 DY1 0 0 n 3 Rendering coordinates ...

Page 100: ...Binary Source Binary Work Specified Color Rendering Work O O Draw Mode Reserved CLIP Reserved NET EOS Reserved Fixed at 0 Fixed at 0 Fixed at 0 O Fixed at 0 O O Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 O Can be used Cannot be used 3 Command Parameters LINE COLOR 8 or 16 bit pixel color specification n n 1 to 65 535 Number of vertices DXn DYn n 1 to 65 535 Relative coordinates ...

Page 101: ...C DXn 1 YC DYn 1 XC DXn 1 DXn YC DYn 1 DYn to the coordinates specified by the relative shift DX DY from the current pointer XC YC The final coordinate point is stored as the current pointer XC YC Note 8 point drawing is used Example XC DX1 YC DY1 XC DX1 DX2 YC DY1 DY2 0 0 N 2 Rendering coordinates XC YC DY2 DY1 DX1 DX2 ...

Page 102: ...encing a binary source Command Format DYn DXn DY2 DX2 DY1 DX1 n TDX SOURCE ADDRESS L SOURCE ADDRESS H 15 0 LINE COLOR 1 LINE COLOR 0 DRAW MODE CODE Fixed at 0 Sign extension Sign extension Sign extension Sign extension Sign extension Sign extension 1 Code B 01110 2 Rendering Attributes ...

Page 103: ...OLOR0 8 or 16 bit pixel color specification LINE COLOR1 8 or 16 bit pixel color specification SOURCE ADDRESS H 1 bit pixel source start upper address SOURCE ADDRESS L 1 bit pixel source start lower address TDX Source size n n 2 to 65 535 Number of vertices DXn n 2 to 65 535 Absolute coordinate DYn n 2 to 65 535 Absolute coordinate Description Draws a polygonal line from vertex 1 DX1 DY1 through ve...

Page 104: ...97 Example SOURCE ADDRESS TRNS 1 and STYL 1 specified DX2 DY2 DX3 DY3 DX1 DY1 0 0 n 3 Rendering coordinates TDX 1100 1100 1100 1100 L S B M S B ...

Page 105: ... DRAW MODE CODE n TDX DX1 DY1 DX2 DY2 DXn DYn Fixed at 0 1 Code B 01111 2 Rendering Attributes Reference Data Drawing Destination Multi Valued Source Binary Source Binary Work Specified Color Rendering Work O O Draw Mode Reserved TRNS Reserved CLIP Reserved NET EOS Reserved Fixed at 0 O Fixed at 1 O Fixed at 0 O O Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 1 O Can be used Cannot be used ...

Page 106: ...raws a polygonal line comprising line segments XC YC XC DX1 YC DY1 XC DX1 YC DY1 XC DX1 DX2 YC DY1 DY2 XC DXn 1 YC DYn 1 XC DXn 1 DXn YC DYn 1 DYn to the coordinates specified by the relative shift DX DY from the current pointer XC YC The final coordinate point is stored as the current pointer XC YC Note TDX can be set in multiples of 8 pixels 4 point drawing is used Example SOURCE ADDRESS TRNS 1 ...

Page 107: ...be used 3 Command Parameters XC Absolute coordinate YC Absolute coordinate Description Sets the current pointer of the rendering coordinate system and the current pointer of the work coordinate system with absolute coordinates The current pointer is used only by relative drawing commands After issuing a MOVE command use relative drawing commands in succession If an absolute drawing command is used...

Page 108: ...101 Example 0 0 Work coordinates Rendering coordinates XC YC ...

Page 109: ...ndering Work Draw Mode Reserved Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Cannot be used 3 Command Parameters XC YC Absolute coordinates Description Sets the current pointer of the rendering coordinate system and the current pointer of the work coordinate system with relative coordinates from the old current pointer ...

Page 110: ...103 Example Old XC YC Old XC XC old YC YC 0 0 Work coordinates Rendering coordinates XC YC ...

Page 111: ...0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Cannot be used 3 Command Parameters XO YO Absolute specification Description Sets the local offset of the rendering coordinate system and the local offset of the work coordinate system with absolute coordinates After this setting is made this offset value is added in all subsequent coordinate specifications The start of the display list must be set the...

Page 112: ...105 Example 0 0 Work coordinates Rendering coordinates XO1 YO1 XO1 DX2 YO1 DY2 XO1 DX1 YO1 DY1 LINE ...

Page 113: ...nnot be used 3 Command Parameters XO YO Relative specification Description Sets the local offset of the rendering coordinate system and the local offset of the work coordinate system with relative coordinates from the old local offset After this setting is made this offset value is added in all subsequent coordinate specifications The old local offset refers to the local offset value set by the lc...

Page 114: ...107 Example 0 0 Work coordinates Rendering coordinates Old XO Old YO Old XO XO DX2 Old YO YO DY2 Old XO XO DX1 Old YO YO DY1 LINE XO YO Old XO XO Old YO YO ...

Page 115: ...Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Cannot be used 3 Command Parameters XMIN XMAX Left and right X coordinates YMIN YMAX Upper and lower Y coordinates Description Designates the area specified by top left coordinates XMIN YMIN and bottom right coordinates XMAX YMAX in the rendering coordinate and work coordinate systems as a user clipping area When making t...

Page 116: ...109 Example 0 0 Work coordinates Rendering coordinates XMIN YMIN XMAX YMAX ...

Page 117: ...d at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Cannot be used 3 Command Parameters XMAX Left right X coordinate YMAX Upper lower Y coordinate Description Designates the area specified by top left coordinates 0 0 and bottom right coordinates XMAX YMAX in the rendering coordinate and work coordinate systems as the system clipping area Make this setting according to the screen size The...

Page 118: ...111 Example 0 0 Work coordinates Rendering coordinates XMAX YMAX ...

Page 119: ...k Specified Color Rendering Work O Draw Mode Reserved Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 O Can be used Cannot be used 3 Command Parameters XMIN XMAX Left and right X coordinates YMIN YMAX Upper and lower Y coordinates Description Zero clears the area specified by top left coordinates XMIN YMIN and bottom right co...

Page 120: ...113 Example 0 0 Work coordinates XMIN YMIN XMAX YMAX ...

Page 121: ...urce Binary Work Specified Color Rendering Work Draw Mode Reserved Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Cannot be used 3 Command Parameters JUMP ADDRESS H Jump destination upper address JUMP ADDRESS L Jump destination lower address Description Changes the display list fetch destination to the specified address ...

Page 122: ...115 Example Display list area Drawing starts Drawing command Drawing command Register setting command Drawing command JUMP command ...

Page 123: ...at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Cannot be used 3 Command Parameters SUBROUTINE ADDRESS H Subroutine upper address SUBROUTINE ADDRESS L Subroutine lower address Description Changes the display list fetch destination to the specified subroutine address The fetch address is restored by an RET instruction As only one level of nesting is perm...

Page 124: ...117 Example Display list area Subroutine Drawing starts Drawing command Drawing command RET command Register setting command Drawing command Drawing command GOSUB command ...

Page 125: ...d Source Binary Source Binary Work Specified Color Rendering Work Draw Mode Reserved Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Cannot be used Description Restores the display list fetch destination to the address following the source of the subroutine call ...

Page 126: ... Binary Source Binary Work Specified Color Rendering Work Draw Mode Reserved Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Cannot be used Description Halts the drawing operation and sends an interrupt to the CPU This command must be placed at the end of the display list ...

Page 127: ...play list area Drawing starts Register setting command Drawing command TRA interrupt generated If TRE 1 at this time an interrupt is generated externally Drawing command Interrupt command Drawing command Drawing stops ...

Page 128: ...raw Mode Reserved Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Fixed at 0 Cannot be used Description The NOP3 command does not perform any operation This command which consists of three words including the command word simply fetches the next instruction without executing any processing The NOP3 command can be used instead of a JUMP ...

Page 129: ...122 ...

Page 130: ... the 0 state Addresses H 026 to H 0FF are reserved and should not be read or written to Reading or writing to these addresses may result in the loss of address mapped register values and unpredictable operation by the Q2 To enable the Q2 to manage UGM access rights initial values must be set in the address mapped registers by the SuperH before it accesses the UGM If the UGM is accessed without set...

Page 131: ...diately before the rise of VSYNC a register can be rewritten without causing display flicker As the VBK flag and FRM flag in the status register SR are set to 1 at the start of vertical blanking external updating can be carried out using these flags Figures 5 1 a and b show the external update interval HSYNC Display area External update interval VSYNC VBK and FRM flags both set to 1 Figure 5 1 a E...

Page 132: ... latches data in an internal register This data transfer is called internal updating Internal updating is carried out while the DRES is set to 1 in the system control register SYSR and at the beginning of each frame The update is performed on setting of the fall ofVSYNC when TVM1 0 and TVM0 0 in the display mode register DSMR master mode and on detection of the fall of EXVSYNC when TVM1 1 and TVM0...

Page 133: ... Control Registers Address A 10 1 Name Abbreviation Bit with Internal Update Function 013 Display window register horizontal display start position DSWR HDS All bits 014 Display window register horizontal display end position DSWR HDE All bits 015 Display window register vertical display start position DSWR VDS All bits 016 Display window register vertical display end position DSWR VDE All bits 01...

Page 134: ...W 0 R W 2 R W 1 R W The system control register SYSR is a 16 bit readable writable register that specifies Q2 system operation SYSR is initialized as follows in a reset Bits SRES and DRES are set to 1 Bits DEN RS DMA1 and DMA0 are cleared to 0 Bits DBM1 and DBM0 retain their values Bit 15 Software Reset SRES Controls execution and suspension of command processing Bit 15 SRES Description 0 Command ...

Page 135: ... then set the DEN bit to 1 Display data from pins DD17 to DD0 has the value stored in the UGM from the next frame 1 0 Display synchronous operation is started Initial value The Q2 only performs UGM refresh operations regardless of the settings of TVM1 and TVM0 in the display mode register With these settings the Q2 operates as follows With these settings the Q2 operates as shown below In a transit...

Page 136: ...g Bit 8 Rendering Start RS Specifies the start of rendering Bit 8 R S Description 0 Rendering is not started Initial value 1 Rendering is started This bit is cleared to 0 after rendering starts When starting rendering have a UGM dummy read performed by the CPU clear the internal FIFO and then set this bit to 1 The internal FIFO is cleared automatically 64 CLK0 cycles later after which drawing can ...

Page 137: ...ount is an internal value in the LSI and is decremented by 1 each time a word is processed UGM access by the CPU is disabled in this mode 1 0 Setting prohibited 1 The mode for DMA transfer to the register image data entry register IDER corresponding to CS1 is set In this mode register address incrementing is not performed and all writes are to IDER When the remaining DMA transfer count reaches 0 t...

Page 138: ...ster VCR setting after the TVR flag has been cleared by the DRES bit in SYSR or the TVCL bit in SRCR Initial value 1 In TV sync mode bits TVM1 and TVM0 10 in DSMR a rise ofEXVSYNC has not been detected within the vertical cycle determined by the VCR set value The TVR flag retains its state until cleared by a reset or by software Bit 14 Frame Flag FRM Flag that indicates the vertical blanking inter...

Page 139: ...2 CER Description 0 Normal state An illegal command has not been fetched since CER flag clearing by the SRES bit in SYSR or the CECL bit in SRCR Initial value 1 Drawing operation halt state Drawing operation remains halted because an illegal command was fetched after CER flag clearing by the SRES bit in SYSR or the CECL bit in SRCR The CER flag retains its state until cleared by a reset or by soft...

Page 140: ...ion Initial value 1 A rendering end interrupt has not been generated in the interval from CSF flag clearing by the SRES bit in SYSR or the CSCL bit in SRCR until the next frame change The CSF flag retains its state until cleared by a reset or by software Bit 8 Display Buffer Frame DBF Flag that indicates the display start address register used as the display start address by the Q2 Bit 8 DBF Descr...

Page 141: ...me Abbreviation Description 15 TV sync signal error flag clear TVCL Writing 1 to the TVCL bit clears the TVR flag to 0 in SR 14 Frame buffer clear FRCL Writing 1 to the FRCL bit clears the FRM flag to 0 in SR 13 DMA flag clear DMCL Writing 1 to the DMCL bit clears the DMF flag to 0 in SR 12 Command error flag clear CECL Writing 1 to the CECL bit clears the CER flag to 0 in SR 11 Vertical blanking ...

Page 142: ...pt generation condition IRL a b c d e f g a TVR TVE b FRM FRE c DMF DME d CER CEE e VBK VBE f TRA TRE g CSF CSE Bit 15 TV Sync Signal Error Flag Enable TVE Enables or disables interrupts initiated by the TVR flag in SR Bit 15 TVE Description 0 Interrupts initiated by the TVR flag in SR are disabled Initial value 1 Interrupts initiated by the TVR flag in SR are enabled When TVR TVE 1 anIRL interrup...

Page 143: ...nitiated by the CER flag in SR are enabled When CER CEE 1 anIRL interrupt request is sent to the CPU Bit 11 Vertical Blanking Flag Enable VBE Enables or disables interrupts initiated by the VBK flag in SR Bit 11 VBE Description 0 Interrupts initiated by the VBK flag in SR are disabled Initial value 1 Interrupts initiated by the VBK flag in SR are enabled When VBK VBE 1 anIRL interrupt request is s...

Page 144: ... R W 0 2 MEA0 R W 1 Note Value is retained The memory mode register MEMR is a 16 bit readable writable register that specifies the size of UGM used and the number of row addresses If the value of this register is modified during a memory access operation will be temporarily unstable MEMR bits MES2 to MES0 MEA1 and MEA0 retain their values in a reset Bits 15 to 7 Reserved Only 0 should be written t...

Page 145: ...1 REF1 0 R W Note Value is retained The display mode register DSMR is a 16 bit readable writable register that specifies the Q2 display operation If the value of this register is modified during a display operation operation will be temporarily unstable DSMR is initialized as follows in a reset Bit YCM is initialized to 0 bits TVM1 and TVM0 to 10 and bits REF3 to REF0 to 1000 The DOT SCM1 and SCM0...

Page 146: ... The frequency of the clock output from the FCLK pin is 1 2 that of CLK1 1 A clock with 1 2 the frequency of the clock input from the CLK1 pin is used as the display dot clock The frequency of the clock output from the DCLK pin is 1 2 that of CLK1 The frequency of the clock output from the FCLK pin is 1 4 that of CLK1 Figure 5 2 shows the display clock timing CLK1 Display dot clock internal signal...

Page 147: ...rcibly halted and the DISP pin output goes low The clock supply to the CLK1 pin can also be stopped input invalidated fixed high within the chip The HSYNC VSYNC and ODDF pins are inputs 1 0 TV sync mode is set HSYNC VSYNC and ODDF signals are input to the Q2 Initial value 1 Setting prohibited Bits 5 and 4 Scan Mode SCM1 SCM0 These bits specify the display output scan mode and the unit of display s...

Page 148: ...of refresh cycles 1 1 0 Number of refresh cycles 2 1 Number of refresh cycles 3 1 0 0 Number of refresh cycles 4 1 Number of refresh cycles 5 1 0 Number of refresh cycles 6 1 Number of refresh cycles 7 1 0 0 0 Number of refresh cycles 8 Initial value 1 Number of refresh cycles 9 1 0 Number of refresh cycles 10 1 Number of refresh cycles 11 1 0 0 Number of refresh cycles 12 1 Number of refresh cycl...

Page 149: ...cription 0 X direction logical coordinate space is 512 pixels 1 X direction logical coordinate space is 1024 pixels Bits 5 to 1 Reserved Only 0 should be written to these bits Bit 0 Graphic Bit Mode GBM Specifies the bit configuration of the rendering data handled by the Q2 Bit 0 GBM Description 0 Rendering data bit configuration is 8 bits pixel 1 Rendering data bit configuration is 16 bits pixel ...

Page 150: ... A2 A1 A0 0 Y upper coordinate X upper coordinate Y lower coordinate X lower coordinate A22 A21 A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 Upper line Memory physical addresses bytes A22 to A1 A0 A0 is an LSI internal signal indicating the LSB of the byte address When GBM 0 the X lower coordinate value must be an even number GBM 0 8 bits pixel MWX 0 512 pixels GBM 0...

Page 151: ...t Data conversion is not performed 1 YUV RGB conversion is performed When the total number of data conversion pixels reaches 0 this bit is automatically cleared and normal mode is entered The total number of data conversion pixels is the product of the image data size register X and Y IDSRX IDSRY set values The total number of data conversion pixels is decremented by 1 in the LSI each time a pixel...

Page 152: ...SX R W 2 DSX R W 1 DSX R W Note Value is retained Display size registers X and Y DSRX DSRY are 16 bit readable writable registers that specify the size of the display screen The number of dots in the horizontal direction is set in DSRX and the number of dots in the vertical direction in DSRY The set value of bits DSX H 0000 to H 03FF corresponds to the number of horizontal dots from 1 to 1024 The ...

Page 153: ...frame buffer 1 F1 are set in the DSA1 field in DSAR1 The display start address register whose contents are actually valid as the display start address is the register indicated by DBF in SR The display start address register whose contents are not valid as the display start address indicates the rendering coordinate origin When these registers are modified the new set value becomes valid when an i...

Page 154: ... are set in these fields Bits 15 to 7 of DLSARH and bits 4 to 0 of DLSARL are reserved Only 0 should be written to these bits a read will return an undefined value The DLSAH field in DLSARH and the DLSAL field in DLSARL retain their values in a reset 5 4 4 Multi Valued Source Area Start Address Register SSAR 15 14 13 12 11 8 10 9 Bit Initial value Read Write 7 6 R W 5 R W 4 R W 3 R W 0 SSAH addres...

Page 155: ...ry capacity for 640 240 screen size 1024 pixels 256 lines 262 144 bits 262 144 bits 8 bits 1024 32 kB 3 Work coordinate system memory capacity for 640 480 screen size 1024 pixels 512 lines 524 288 bits 524 288 bits 8 bits 1024 64 kB Bits 15 to 7 of WSAR are reserved Only 0 should be written to these bits a read will return an undefined value The WSAH field in WSAR retains its value in a reset 5 4 ...

Page 156: ... R W 12 DMAW 0 R W 11 DMAW 0 R W 8 DMAW 0 R W 10 DMAW 0 R W 9 DMAW 0 R W Bit Initial value Read Write 7 DMAW 0 R W 6 DMAW 0 R W 5 DMAW 0 R W 4 DMAW 0 R W 3 DMAW 0 R W 0 DMAW 0 R W 2 DMAW 0 R W 1 DMAW 0 R W The DMA transfer word count register DWAWR is a 16 bit readable writable register that specifies the number of words 1 word 16 bits to be transferred in DMA transfer If the value of this registe...

Page 157: ...E R W 0 HDE R W 2 HDE R W 1 HDE R W 15 14 13 12 11 8 HDS R W 10 9 Bit DSWR HDS Initial value Read Write 7 HDS R W 6 HDS R W 5 HDS R W 4 HDS R W 3 HDS R W 0 HDS R W 2 HDS R W 1 HDS R W Note Value is retained The display window registers DSWR HDS HDE VDS VDE are 16 bit readable writable registers that specify the horizontal and vertical output timing for the display screen 1 Horizontal Display Start...

Page 158: ...HSWR are reserved Only 0 should be written to these bits a read will return an undefined value HSWR bits HSW retain their values in a reset 5 5 3 Horizontal Scan Cycle Register HCR 15 14 13 12 11 8 HC R W 10 HC R W 9 HC R W Bit Initial value Read Write 7 HC R W 6 HC R W 5 HC R W 4 HC R W 3 HC R W 0 HC R W 2 HC R W 1 HC R W Note Value is retained The horizontal scan cycle register HCR is a 16 bit r...

Page 159: ...ten to these bits a read will return an undefined value VSPR bits VSP retain their values in a reset 5 5 5 Vertical Scan Cycle Register VCR 15 14 13 12 11 8 VC R W 10 9 VC R W Bit Initial value Read Write 7 VC R W 6 VC R W 5 VC R W 4 VC R W 3 VC R W 0 VC R W 2 VC R W 1 VC R W Note Value is retained The vertical scan cycle register VCR is a 16 bit readable writable register that specifies the verti...

Page 160: ...DOR R W 5 DOR R W 4 DOR R W 3 DOR R W 0 2 DOR R W 1 Note Value is retained Display off output registers H and L DOORH DOORL are 16 bit readable writable registers that specify the display data to be output from pins DD0 to DD17 when DRES 0 and DEN 1 A6 bit setting is made for each of the RGB components in bits DOR DOG and DOB Bits 15 to 8 1 and 0 of DOORH and bits 9 8 1 and 0 of DOORL are reserved...

Page 161: ...itable registers When the display data output from pins DD17 to DD0 matches the values set in these registers 1 is output from the CDE pin Color detection is performed by means of the CDE pin during the blanking period Pins DD0 to DD17 all go low during this period Therefore if both CDERH and CDERL are cleared to 0 CDE pin output will go high during the blanking period Similarly if either CDERH or...

Page 162: ...5 R 4 R 3 CSTH address A22 A16 setting R 0 R 2 R 1 R Note Value is retained Command status registers H and L CSTRH CSTRL are 16 bit read only registers that store the address of the command word op code word being executed when frame switching is performed The upper bits A22 to A16 of the command word address are indicated by the CSTH field and the lower bits A15 to A1 by the CSTL field The addres...

Page 163: ...ting 0 R W 0 0 R W 2 0 R W 1 0 R W Note Value is retained Image data transfer start address registers H and L ISARH ISARL are 16 bit readable writable registers that specify the image data transfer destination as a physical address when the setting of bits YUV1 and YUV0 is 01 or 10 The upper bits A22 to A16 of the start address are set in the ISAH field and the lower bits A15 to A1 in the ISAL fie...

Page 164: ...should be set for the X size IDSX0 bit 0 If the value of these registers is modified during a series of data conversion operations from the time bits YUV1 and YUV0 are set to 01 or 10 by the CPU until YUV mode is cleared automatically by the Q2 operation will be unstable Bits 15 to 11 of IDSRX and bits 15 to 10 of IDSRY are reserved Only 0 should be written to these bits The values of IDSRX Y bits...

Page 165: ...R W 3 R W 0 2 R W 1 15 14 13 12 11 8 10 9 Bit CP255RH Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 2 R W 1 15 R W 14 R W 13 R W 12 R W 11 R W 8 10 R W 9 Bit CP001RL Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 2 R W 1 15 14 13 12 11 8 10 9 Bit CP001RH Initial value Read Write 7 R W 6 R W 5 R W 4 R W 3 R W 0 2 R W 1 15 R W 14 R W 13 R W 12 R W 11 R W 8 10 R W 9 Bit CP000RL I...

Page 166: ... reading color palette registers first read the R register then the G and B registers When accessing color palette registers it is not possible to access another register between the R register and the G and B registers In color palette accesses access to another Q2 register is prohibited between access to the R register and access to the G and B registers In modes in which GBM 1 16 bits pixel the...

Page 167: ...160 ...

Page 168: ...ssumed that a clock with the same frequency and same phase as the SuperH clock is used as the Q2 operating clock Therefore Q2 multiplication should be turned off and the clock output from the CK pin should be input directly to CLK0 see figure 6 1 This operation is possible only with an SH 1 or SH 2 CPU The RD and WE high level setup time and hold time specifications must still be observed when syn...

Page 169: ... in which the number of dots in the X direction exceeds 512 For this reason a value that satisfies condition 1 or 2 below should be set in the horizontal display start position register HDS The horizontal display start position register HDS value is determined by the graphic bit mode the internal operating frequency CLK0 and the display dot clock DCLK If the DSX value is less than 512 it is not ne...

Page 170: ...alculation When X direction screen size 640 dots CLK0 28 2636 MHz DCLK 14 1318 MHz HDS 36 32 14 1318 28 2636 500 640 512 640 512 HDS 225 2 8 bits pixel GBM 0 HDS 68 64 DCLK CLK0 500 X direction screen size 512 2 X direction screen size 512 Sample calculation When X direction screen size 640 dots CLK0 28 2636 MHz DCLK 14 1318 MHz HDS 68 64 14 1318 28 2636 500 640 512 2 640 512 HDS 225 Round off ...

Page 171: ... more 2nd setting 3rd setting 4th setting 5th setting Dummy read Dummy read Dummy read Figure 6 3 Data Transfer Procedure for One Line 3 When YUV mode 01 or 10 do not perform reads of the registers shown in the table below A 10 1 Register Abbreviation Register Name 007 IEMR Input data conversion mode 010 DMASHR DMA transfer start address 011 DMASLR DMA transfer start address 012 DMAWR DMA transfer...

Page 172: ...st include at least one of the following commands POLYGON4A POLYGON4B POLYGON4C LINE RLINE PLINE RPLINE An example of a dummy display list is shown below Example of dummy display list SCLIP XMAX YMAX LCOFS 0 0 LINE LINE COLOR 2 0 0 0 0 TRAP 6 5 Note on Use of Auto Display Change Mode When using auto display change mode if Q2 drawing is aborted due to a frame change invalid drawing of 1 to 4 dots m...

Page 173: ...et to 11 YUV conversion is not performed As YUV 01 is set for the YUV mode the registers shown in the table below must not be accessed A 10 1 Register Abbreviation Register Name 007 IEMR Input data conversion mode 010 DMASHR DMA transfer start address 011 DMASLR DMA transfer start address 012 DMAWR DMA transfer word count 021 ISAHR Image data transfer start address 022 ISALR Image data transfer st...

Page 174: ...rise of CLK0 and CLK1 should be 100 ms or less and the time from the rise of VCCn until the rise of RESET 100 ms or more If CLK0 and CLK1 are stopped for a long period 100 ms or more after powering on the chip may be damaged 4 5 V 1 5 V Max 100 ms Min 100 ms Min 0 ms 3 6 V 0 8 V VCCn CPU VCCn CLK0 CLK1 RESET Figure 6 4 CLK0 CLK1 RESET Signal Timing ...

Page 175: ...work coordinates Figure 6 5 Updating of Q2 s Internal Buffers These buffers are used by the Q2 to temporarily store data held in the UGM The Q2 uses the data stored in these buffers when executing drawing The functions of these buffers are shown in a to c below a Command buffer Used by the Q2 to store a display list held in the UGM b Source buffer Used by the Q2 to store a binary source or multi v...

Page 176: ... word boundary is used without updating command parameters TXS and TYS or the source area start address the source buffer is not updated since the address indicated by the Q2 does not exceed a 16 word boundary In a drawing operation drawing is performed using the multi valued source stored in the source buffer c When using the FTRAP RFTRAP CLRW LINEW and RLINEW commands If a binary source within a...

Page 177: ...mode register DSMR and a transition is made to synchronization system switching mode set the display reset bit DRES to 1 and clear the display enable bit DEN to 0 in the system control register before making the transition to synchronization system switching mode This procedure provides for the HD64411 to perform UGM refreshing in synchronization system switching mode The procedure is shown below ...

Page 178: ...ce reference error occurs and the same data is drawn at the rendering coordinate X 64 t 1 pixel and the following pixel where t 1 Conditions Rendering attribute WORK 1 or STYL 1 Source start point TXS 32 p 1 where p 0 Remedy When using the POLYGON4A command under these conditions set a value other than 32 p 1 for source start point TXS ...

Page 179: ...172 ...

Page 180: ...t voltage Vin 1 0 3 to VCC 0 3 V Permissible output low current IOL 2 2 0 mA Total permissible output low current IOL 3 90 mA Permissible output high current IOH 2 2 0 mA Total permissible output high current IOH 3 90 mA Operating temperature Topr 0 to 70 C Storage temperature Tstg 55 to 125 C Notes 1 Value based on GND 0 V Includes CPUVCC and PLLVCC 2 The permissible output current is the maximum...

Page 181: ...PLLVCC 2 4 75 5 0 5 25 V CPUVCC 3 5 V operation 4 75 5 0 5 25 V 3 3 V operation 3 0 3 3 3 6 V Input low voltage VILT 1 0 0 8 V Input low voltage CVLK0 CLK1 VILC 1 0 0 8 V Input high voltage VIHT 1 2 2 VCC V Input high voltage CLK0 CLK1 VIHC 1 0 8 VCC VCC V Operating temperature Topr 0 25 70 C Notes 1 Value based on GND 0 V 2 Value based on PLLGND 0 V 3 Value based on CPUGND 0 V ...

Page 182: ... 7 3 1 Timing Testing The output low voltage for timing testing is 1 5 V The output high voltage for timing testing is also 1 5 V VOH V 0 t Reference point VOL for timing testing 1 5 V DC level steady VOL 0 4 V Figure 7 1 Basis of VOL Timing Testing ...

Page 183: ...ut and Input Output Pins Test Point C R RL 5 0V Input output timing test levels excluding CLK0 and CLK1 Low level 1 5 V High level 1 5 V RL 1 8 kΩ C 70 PF R 10 kΩ All diodes are 1S2074 H or equivalent products Figure 7 2 Test Load Circuit ...

Page 184: ...el VILT 0 3 0 8 Input leakage current I1 I2 Iin 2 5 2 5 µA Vin 0 to VCC Three state leakage current off state IO1 IO2 ITSI 10 10 Vin 0 4 to VCC Output high voltage 5 V IO1 O1 VOH VCC 1 0 V IOH 400 µA Output high voltage IO2 O2 VOH CPUVCC 1 0 IOH 400 µA CPUVCC 5 0 V 5 CPUVCC 0 5 IOH 200 µA CPUVCC 3 0 V to 3 6 V Output low voltage IO1 IO2 O1 O2 VOL 0 4 IOL 2 0 mA Input capacitance IO1 IO2 Cin 20 pF ...

Page 185: ...7 4 Input Clocks 1 Pins MODE2 to MODE0 011 Multiplication Off Item Symbol Min Max Unit Test Conditions Notes Clock 0 Cycle Time tcyc0 30 3 50 ns Figure 7 3 Clock 0 High Level Pulse Width tC0PWH 10 1 ns Clock 0 Low Level Pulse Width tC0PWL 10 1 ns Clock 0 Duty tC0DT 0 5tcyc0 1 7 0 5tcyc0 1 7 ns Clock 1 Cycle Time tcyc1 60 6 150 ns XW 512 170 XW 512 Clock 1 High Level Pulse Width tC1PWH 25 3 ns Cloc...

Page 186: ...10 1 ns Clock Delay Time 1 tCLKD1 10 ns Clock Delay Time 2 tCLKD2 tcyc 4 11 7 ns Clock Delay Time 3 tCLKD3 tcyc 2 11 7 ns Clock Delay Time 4 tCLKD4 3tcyc 4 11 7 ns Clock i Cycle Time tcyc0 30 3 50 ns Clock i High Level Pulse Width tCiPWH 10 1 ns Clock i Low Level Pulse Width tCiPWL 10 1 ns Clock 1 Cycle Time tcyc1 60 6 150 ns XW 512 170 XW 512 Clock 1 High Level Pulse Width tC1PWH 25 3 ns Clock 1 ...

Page 187: ...s RESET Uncertain Time of Acceptance 2 tRES2 5 ns DCLK Rise Delay Time From CLK1 tDCRD 30 ns DCLK Fall Delay Time From CLK1 tDCFD1 30 ns DOT 1 DCLK Fall Delay Time From CLK1 tDCFD0 30 ns DOT 0 FCLK Rise Delay Time From CLK1 tFCRD 30 ns FCLK Fall Delay Time From CLK1 tFCFD 30 ns DCLK Cycle Time tcyc D 2tcyc1 2tcyc1 ns DOT 1 DCLK Cycle Time tcyc D 1tcyc1 1tcyc1 ns DOT 0 ...

Page 188: ... Read Data Setup Time For WAIT tRDDWS 10 ns WAIT Delay Time tWAD 25 ns RD High Level Hold Time tRDH 12 1 2 tcyc0 ns Multiplica tion off Read Data Turn On Time tRDDON 0 ns Read Data Hold Time tRDDH 4 ns Read Data Turn Off Time tRDDOF 4 ns WE High Level Width tWEHW tcyc0 ns Notes 1 If the fall of CSn is later than the fall of RD the specifications of tADS tWAS1 tRDDON and tWEHW are from the fall of ...

Page 189: ...me 2 tWAS2 4tcyc0 ns WEn High Level Width tWEHW tcyc0 ns 3 Write Data Setup Time For WEn tWRDES 2tcyc0 ns 3 Write Data Hold Time tWRDH 0 ns Write Data Turn Off Time tWRDOF 30 ns WEn High Level Hold Time tWEH 12 1 2 tcyc0 ns 3 Multiplica tion off Notes 1 If the fall of CSn is later than the fall of WEn the specifications of tADS tRDHW and tWAS2 are from the fall of CSn CSn CS0 CS1 WEn WE0 WE1 2 If ...

Page 190: ...RDOF 30 ns Write Data Setup Time For RD tWRDRS 2tcyc0 ns DREQ Delay Time tDAD 25 ns DREQ Negate Time tDAN 3tcyc0 ns DACK Setup Time tDAS 0 ns 1 DACK Hold Time tDAH 0 ns 2 Notes 1 If the fall of DACK is later than the fall of RD the specification of tRDLW is from the fall of DACK 2 If the rise of DACK is earlier than the rise of RD the specifications of tRDLW tWRDH tWRDOF and tWRDRS are from the ri...

Page 191: ...ROWS 0 ns Row Address Hold Time tROWH 15 ns Column Address Setup Time tCOMS 6 ns Column Address Hold Time tCOMH 10 ns OE Delay Time tOED 25 ns MD Turn On Time tMDON 0 ns MD Turn Off Time tMDOF 35 ns MD Input Setup Time tMDIS 5 ns MD Input Hold Time tMDIH 3 ns MD Input Time 1 tMDI1 tcyc0 5 µs MD Input Hold Time 1 tMDH1 3 µs OE Rise Time from RAS Rise tOER0 0 Column Address Delay Time tCADD 20 ns ...

Page 192: ... tROWS 0 ns Row Address Hold Time tROWH 15 ns Column Address Setup Time tCOMS 6 ns Column Address Hold Time tCOMH 10 ns MD Turn On Time tMDON 0 ns WE Delay Time tWED 25 ns MD Output Setup Time tMDOS 0 ns MD Output Hold Time tMDOH 18 ns 9 UGM Refresh Cycle Table 7 12UGM Refresh Cycle Item Symbol Min Max Unit Test Conditions Notes RAS Delay Time tRASD 25 ns Figure 7 15 CAS Delay Time tCASD 25 ns ...

Page 193: ...Delay Time from CLK1 tFCRD 30 ns FCLK Fall Delay Time from CLK1 tFCFD 30 ns DD Setup Time For DCLK tDDS 9 ns DD Hold Time For DCLK tDDH 5 ns HSYNC Delay Time From DCLK tHSDD 25 ns VSYNC Delay Time From DCLK tVSDD 25 ns ODDF Delay Time From DCLK tODDD 25 ns CSYNC Delay Time From DCLK tSYDD 25 ns DISP Delay Time From DCLK tDIDD 25 ns CDE Delay Time From DCLK tCDEDD 25 ns ...

Page 194: ...30 ns DCLK cycle tcyc0 2tcyc1 2tcyc1 µs DOT 1 tcyc1 tcyc1 DOT 0 DD Setup Time For DCLK tDDS 9 ns DD Hold Time For DCLK tDDH 5 ns DISP Delay Time From DCLK tDIDD 25 ns CDE Delay Time From DCLK tCDEDD 25 ns EXHSYNC High Level Width tEXHHW 2tcyc1 ns EXHSYNC Low Level Width tEXLLW 4tcyc1 µs EXHSYNC Uncertain Time of Acceptance 1 tEXH1 5 ns EXHSYNC Uncertain Time of Acceptance 2 tEXH2 5 ns DISP Start T...

Page 195: ...14 ODDF Uncertain Time of Acceptance 2 tOD2 1tcyc1 ns Note 1 hds hsw xs 7 5 Timing Charts 7 5 1 Input Clocks VIL tcyc0 tcyc1 tC0PWH tC0DT tC0DT tC0PWL tcr tcf tcr tcf VIH 0 5VCC VIH 0 5VCC VIL VIH 0 5VCC VIL VIH 0 5VCC VIL tC1PWH tC1PWL VIH 0 5VCC VIL tC1DT tC1DT VIH 0 5VCC VIL CLK0 input CLK1 input Figure 7 3 Input Clocks Pins MODE2 to MODE0 011 ...

Page 196: ... pins MODE2 to MODE0 010 tcyc CLK0 input pins MODE2 to MODE0 001 CLK0 input pins MODE2 to MODE0 000 CLKi pins MODE2 to MODE0 000 CLKi pins MODE2 to MODE0 010 CLKi pins MODE2 to MODE0 001 VIH 0 5VCC VIH 0 5VCC VIL 0 5VCC VIL VIH 0 5VCC VIH 0 5VCC VIL 0 5VCC VIL VIH 0 5VCC VIH 0 5VCC VIL 0 5VCC VIL VIH 0 5VCC VIH VIH VIH 0 5VCC VIL VIL 0 5VCC VIL VIH 0 5VCC VIH VIH 0 5VCC VIL VIL 0 5VCC VIL tcr tcf ...

Page 197: ...ise of RESET Initialization sequence 3t cyc1 CLK1 input RESET input DCLK output DOT 1 FCLK output DOT 1 DCLK output DOT 0 FCLK output DOT 0 t RESW t RES1 t DCRD t cyc D t cyc D t DCRD t DCRD t DCRD t DCFD1 t DCFD0 t FCRD t FCRD t FCRD t FCFD t FCFD t FCRD t RES2 Figure 7 5 Reset Timing ...

Page 198: ...o A1 input CS1 CS0 input RD input WE1 WE0 input WAIT output D15 to D0 input output DACK input t ADH t ADS t CSS t CSH t RDS t RDH t WAD t WAS1 t RDHW t WAD t RDDON t WEHW t WEHW t RDDH t RDDOF t RDDWS t RDHW High low simultaneous with CS0 and CS1 prohibited Figure 7 6 CPU Read Cycle Timing CPU Q2 with Hardware Wait ...

Page 199: ...t WEH t WEHW t WRDOF t WRDH T1 T1 T1 TW TW T2 T2 T3 CLK0 input CLKi multiplication off multiplication on A22 to A1 input CS1 CS0 input RD input WE1 WE0 input WAIT output D15 to D0 input output DACK input High low simultaneous with CS0 and CS1 prohibited Figure 7 7 CPU Write Cycle Timing CPU Q2 with Hardware Wait ...

Page 200: ...DH T1 CLK0 input CLKi multiplication off multiplication on CS1 CS0 input RD input WAIT output D15 to D0 input output t RDHW t RDH t RDHW t RDLW t DAH t DAS DACK input High t RDS High low simultaneous with DACK prohibited Figure 7 8 DMA Write Cycle Timing DMAC Q2 ...

Page 201: ...194 T1 T2 T3 CLK0 input CLKi multiplication off multiplication on DACK input t RDHW t RDS t DAN t DAH t DAS RD input t DAD t DAD DREQ output t DAD t RDH Figure 7 9 DMA Write Cycle Timing DMAC Q2 ...

Page 202: ...195 7 5 6 Interrupt Output Timing CLK0 input CLKi multiplication off multiplication on IRL output t IRD t IRD t IRLW Figure 7 10 Interrupt Output Timing ...

Page 203: ... MRAS1 MRAS0 output MWE output MOE output MD15 to MD0 input output MLCAS MUCAS output t ROWH t RASD t CADD t RASD T1 T2 T3 T4 T5 T1 T2 T3 T4 t RASD t OED t OED t OERD t CASD t CASD t CASD t MDH1 t MDI1 t MDON Q2 input Q2 output Q2 output t MDOF t MDON RAS RAS t COMH t COMS t ROWS CAS Figure 7 11 UGM EDO DRAM Single Read Cycle Timing ...

Page 204: ... input Q2 output Q2 output D1 D2 D3 D4 D5 t ROWH t RASD t CADD t CADD t RASD T1 T2 T3 T4 T4 T4 T4 T4 T5 T1 t OED t OED t OERD t MDS t MDS t MDS t MDS t MDH1 t MDH1 t MDH1 t MDH1 t MDH1 t MDON t MDI1 t MDS t MDOF t MDON CAS2 CAS3 RAS CAS4 t COMH t COMH t COMH t COMS t COMS t COMS t ROWS CAS5 t CASD t CASD t CASD t CASD t CASD t CASD CAS1 Figure 7 12 UGM EDO DRAM Burst Read Cycle Timing ...

Page 205: ...i multiplication off multiplication on MRAS1 MRAS0 output MWE output MOE output MD15 to MD0 input output MLCAS MUCAS output Q2 output t ROWH t RASD t RASD T1 T2 T3 T4 T5 t WED t WED t CASD t CASD t MDS t MDH t MDON RAS CAS t COMH t COMS t ROWS RAS Figure 7 13 UGM EDO DRAM Single Write Cycle Timing ...

Page 206: ... MOE output MD15 to MD0 input output MLCAS MUCAS output Q2 output D1 D2 D3 D4 D5 t ROWH T1 T2 T3 T4 T4 T4 T4 T4 T5 T1 t WED t CASD t CASD t CASD t CASD t MDH t MDS t MDH t MDS t WED t MDS t MDH t MDON CAS2 CAS3 RAS CAS4 t COMH t COMS t COMS CAS5 t RASD t RASD t COMH t ROWS CAS1 Figure 7 14 UGM EDO DRAM Burst Write Cycle Timing ...

Page 207: ... CASD t RASD t RASD T1 T2 T3 T4 T5 CLK0 input CLKi multiplication off multiplication on MRAS1 MRAS0 output MLCAS MUCAS output MWE output MOE output MD15 to MD0 output MA11 to MA0 output t CASD Figure 7 15 UGM EDO DRAM Refresh Cycle Timing ...

Page 208: ... DCLK output FCLK output DD17 to DD0 output tDCRD T1 T1 tDCRD tFCFD tFCRD tFCRD HSYNC output tDDH tDDS VSYNC output tHSDD tHSDD ODDF output tVSDD tVSDD CSYNC output tSYDD tSYDD DISP output tDIDD tDIDD CDE output tCDEDD tCDEDD tODDD tODDD Figure 7 16 Master Mode Display Timing ...

Page 209: ...ing T1 CLK1 input DOT 0 CLK1 input DOT 1 DCLK output FCLK output DD17 to DD0 output tDCRD T1 T1 tDCRD tFCRD tFCRD DISP output tDIDD tDIDD tDDH tDDS CDE output tCDEDD tCDEDD CSYNC output High tFCFD Figure 7 17 TV Sync Mode Display Timing ...

Page 210: ...lization sequence 3 tcyc1 TH1 t DCFD1 t cycD t cycD t DCFD0 t FCRD t FCFD t FCRD t FCRD t FCFD t FCRD CLK1 input EXHSYNC input DCLK output DOT 1 FCLK output DOT 1 DCLK output DOT 0 FCLK output DOT 0 t EXHHW t EXH2 t EXH1 t DCRD t DCRD t DCRD t DCRD Figure 7 18 TV Sync Mode Display Timing ...

Page 211: ... output ODDF input EXVSYNC input EXHSYNC input CLK1 input t EXHHW t EXH2 t EXH1 t EXH1 t EXV1 t EXVLW t OD2 t OD1 t DIEXH t DCRD t DDH t DDS t EXV2 t DIDD Figure 7 19 TV Sync Mode Display Timing When DOT 1 and EXHSYNC cycle is odd multiple of CLK1 cycle ...

Page 212: ...5 t EXH1 t OD1 t EXH2 t EXV2 t DDH t DDS t DIEXH t DCRD t EXH1 TH1 1t cyc1 t EXV1 t OD2 t EXVLW t EXHHW t DIDD DISP output DD17 to DD0 output DCLK output ODDF input EXVSYNC input EXHSYNC input CLK1 input ...

Page 213: ...206 Figure 7 20 TV Sync Mode Display Timing When DOT 0 or DOT 1 and EXHSYNC cycle is even multiple of CLK1 cycle ...

Page 214: ... width Horizontal scan cycle Vertical sync position Vertical scan cycle Horizontal display end address Vertical display start address Horizontal display start address Display windows Vertical display end address Display off output Color detection L H L H H L HSWR HCR VSPR VCR DSWR DOOR CDER HDS HDE VDS VDE HSW HC VSP VC DOR DOG DOB CDR CDG CDB CSTH CSTL 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Regist...

Page 215: ...R CP255R CP002R R000 B000 R001 B001 B002 R002 R255 B255 G000 G001 G002 G255 000H 000L 001H 001L 002H 002L 255H 255L R W W R W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Register Address 021 022 023 024 025 R W R W Register Name Abbrevia tion R W CS1 0 Image data transfer start address Image data size Image data entry IDER A 10 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Data ISAH ISAL IDSX IDSY IDE H L X Y...

Page 216: ...wing Destination Rendering Attributes O POLYGON4A POLYGON4B POLYGON4C LINE RLINE PLINE RPLINE FTRAP RFTRAP CLRW LINEW RLINEW MOVE RMOVE LCOFS RLCOFS UCLIP SCLIP JUMP GOSUB RET NOP3 TRAP O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O O Can be used Can be used EOS reference specified color is binary EOS bit value Referenced depending on mo...

Page 217: ...INEW RLINEW LINE RLINE PLINE RPLINE MOVE RMOVE LCOFS RLCOFS CLRW UCLIP SCLIP JUMP GOSUB RET TRAP 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 CODE 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 0 0 0 1 1 0 0 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 0 1 1 1 0 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 0 1 1 1 0 NOP3 ...

Page 218: ...start lower address Given as lower 13 bits Source address is set as an even byte address 15 DXn or DYn Sign extension 0 Rendering work coordinates Vertex coordinates DXn DYn 1 n 4 Given as signed 11 bit data Use sign extension in upper vacant bits 15 COLOR0 0 16 bit pixel color specification Color data 0 given as 16 bit data 15 COLOR1 or COLOR 0 16 bit pixel color specification Color data 1 given ...

Page 219: ...ension in upper vacant bits DXn 15 0 Left hand side coordinate DXL Given as signed 11 bit data Use sign extension in upper vacant bits DXL Sign extension 15 0 Absolute coordinate Vertex coordinate DYn 2 n 65 535 Given as signed 11 bit data Use sign extension in upper vacant bits DYn 15 DYn DXn 0 Relative coordinates Vertex coordinates DXn DYn 1 n 65 535 Given as signed 8 bit data Sign extension Si...

Page 220: ...upper vacant bits DYn 15 DYn DXn 0 Relative coordinates Vertex coordinates DXn DYn 1 n 65 535 Given as signed 8 bit data 15 0 Number of vertices 2 n 65 535 absolute 1 n 65 535 relative Given as unsigned 16 bit data n Sign extension Sign extension CLRW 15 XMIN XMAX 0 Left and right X coordinates XMIN XMAX Given as signed 11 bit data Fixed at 0 15 YMIN YMAX 0 Upper and lower Y coordinates YMIN YMAX ...

Page 221: ... color specification Color data given as 16 bit data 15 0 Absolute coordinate Vertex coordinate DXn 2 n 65 535 Given as signed 11 bit data Use sign extension in upper vacant bits DXn 15 0 Absolute coordinate Vertex coordinate DYn 2 n 65 535 Given as signed 11 bit data Use sign extension in upper vacant bits DYn 15 DYn DXn 0 Relative coordinates Vertex coordinates DXn DYn 1 n 65 535 Given as signed...

Page 222: ... n 65 535 absolute 1 n 65 535 relative Given as unsigned 16 bit data n 15 LINE COLOR0 0 bit pixel color specification Color data given as 16 bit data 15 SOURCE ADDRESS H 0 1 bit pixel source start upper address Given as upper 10 bits 15 TDX 0 Source size TDX TDY Given as unsigned max 10 bit data TDX can only be set in 8 pixel units 15 0 1 bit pixel source start lower address Given as lower 13 bits...

Page 223: ... XC YC Given as signed 8 bit data Sign extension Sign extension LCOFS RLCOFS 15 0 Relative specification Local offset values XO YO Given as signed 11 bit data Use sign extension in upper vacant bits XO or YO 15 YO XO 0 Relative specification Local offset values XO YO Given as signed 8 bit data Sign extension UCLIP SCLIP 15 15 Fixed at 0 XMIN XMAX 0 Left and right X coordinates XMIN XMAX Given as u...

Page 224: ...wer address Given as lower 13 bits Jump destination address is set as a word address JUMP ADDRESS L GOSUB 15 SUBROUTINE ADDRESS H 0 Subroutine upper address Given as upper 10 bits 15 SUBROUTINE ADDRESS L 0 0 Subroutine lower address Given as lower 13 bits Subroutine destination address is set as a word address Fixed at 0 ...

Page 225: ...n dot by dot toward the top right corner With the method shown in figure C 1 a the next dot drawn is to the right or diagonally to the upper right of the current dot With the method shown in figure C 1 b on the other hand the next dot drawn is to the right of or directly above the current dot For the sake of convenience the method in figure C 1 a is here called 8 point drawing and that in figure C...

Page 226: ...imity to an actual straight line The same approach is also used in 4 point drawing figure C 3 b A comparison between 8 point drawing and 4 point drawing shows that closer approximation to a straight line can be achieved with 8 point drawing However the algorithm is correspondingly complex requiring longer processing time a A B C b A B C Actual straight line Figure C 3 Drawing Dot Determination Pro...

Page 227: ...gital Display of Digital Arcs Commun ACM Vol 20 No 2 February 1977 100 106 4 P E Danielsson Incremental Curve Generation IEEE Trans Comput Vol C 19 September 1970 783 793 5 W J Jr Bernard An Improved Algorithm for the Generation of Nonparametric Curves IEEE Trans Comput Vol C 22 No 12 December 1973 1052 1060 6 Jerry van Aken An Efficient Ellipse Drawing Algorithm IEEE Comput Graph Appl Vol 4 No 9 ...

Page 228: ...0 04 0 15 0 04 Unit mm Dimension including the plating thickness Base material dimension Figure D 1 Package Dimensions HD64411 Q2 User s Manual Publication Date 1st Edition December 1997 Published by Semiconductor and IC Div Hitachi Ltd Edited by Technical Documentation Center Hitachi Microcomputer System Ltd Copyright Hitachi Ltd 1997 All rights reserved Printed in Japan ...

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