2
1. CIRCUIT DESCRIPTION
1.1 OVERALL BLOCK DIAGRAM
Spindle Motor
TA
FA
Slider
HA
TE
GEN
OEIC
A/D
Sync
Demod
Spindle control
ECC &
ID Reg.
Sub-CPU
I/F
DRAM I/F
(bus arbitor)
CPU
I/F
DMA
CD-ROM Sync gen.
Sub-code Buffer
VBR Buffer
4M bit DRAM
SREO
Program Stream
XSACK
CD PCM
CD D. OUT
CD DSP
EFM
Decoder
Servo
DSP
CD PCM
CD Digital Out
Mechanism
Control
CPU
Loading
Motor
Mechanism
sense SW
Key-SW
& Display
System CPU
(32 bit RISC)
FLASH
ROM
RAM
SREO
XSACK
CPU
I/F
Y
C
Comp.
PCM D-Out
AC3 D-Out
Lt
Rt
Video Out
DVD/V-CD
AV Decoder
Display
CPU
SYSTEM
Decoder
(DMUX)
AV Sync
controller
MPEG2
Video
Decoder
Sub-
picture
Decoder
GUI
Memory Controller
16M bit SDRAM
CODE Buffer
(Video, Audio, Sub-picture,GUI)
MIX
D/A
AC3/MPEG1
Audio Decoder
Copy
Guard
NTSC
/PAL
encode
DAC
DAC
DAC
S/PDIF
LSI-11
IC802
MB811171622A-100FN
IC604
TC551001BFL-85
IC603
VYW1602
IC601
PD3381A
IC701
PD4833A
IC301
TLC5540INS
IC201
LC78650NE
IC702
HM514800CJ-7
IC501
PD4889A
IC101
PD4890A
IC801
MB86371
(MPEG2 Decoder)