K6602637
Rev.3
02.27.01
- 34 -
6.3.1.11 Alternate Status Register
The information in this register is a duplicate of that in the Status Register. Reading this register will not
clear the interrupt.
6.3.1.12 Device Control Register
This register includes the software reset bit and the interrupt enable bit.
Bit
7
6
5
4
3
2
1
0
Name
-
-
-
-
-
SRST
nIEN
'0'
a) nIEN(Interrupt Enable): If the device is selected when nIEN is 0, the INTRQ signal is enabled. When
nIEN is 1 or when the device is not selected, the INTRQ signal is in a high impedance state.
b) SRST (Software Reset): When this bit is set, the device is reset. When this bit is cleared, the device
exits from the reset state. When two devices are connected through one line in the daisy chain mode,
they are reset simultaneously.
