Hitachi 55293DLB, Service Manual

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Table: Recommended operating conditions
8. 2GB DDR3 SDRAM
HYN İ X H5TQ2G63DFR
Description
The H5TQ2G63DFR is a 2,147,483,648-bit CMOS Double Data Rate III (DDR3) Synchronos DRAM,
ideally suited fort he main memory applications which requires large memory density and high bandwidth. SK
Hynix 2Gb DDR3 SDRAMs offer fully synchronous operations referenced to both rising and falling edges of
the clock. While all addresses and control input are latched on the rising edges of the CK (falling edges of the
CK), Data, Data stobes and Write data masks inputs are sampled on both rising and falling edges of it. The data
paths are internally pipelined and 8-bit prefetched to achieve very high bandwidth.
Features

VDD & VDDQ = 1.5V +/- 0.075V

Fully differential clock inputs (CK, CK) operation

Differential Data Strobe (DQS, DQS)

On chip DLL align DQ, DQS and DQS transition with CK transition

DM masks write data-in at the both rising and falling edges of the data strobe

All addresses and control inputs except data, data strobes and data masks latched on the rising edges of
the clock

Programmable CAS latency 5,6, 7, 8, 9, 10, 11, 12, 13 and 14 supported

Programmable additive latency 0, CL-1, and CL-2 supported

Programmable CAS Write latency (CWL) = 5, 6, 7, 8

Programmable burst length 4/8 with both nibble sequential and interleave mode

BL switch on the fly

8banks

Average Refresh Cycle (Tcase 0C – 95C)
o
7.8 uS at 0C - 85C
o
3.9 uS at 85C – 95C
Commercial Temperature(0C – 85C)
Industrial Temperature(-40C- 95C)

Auto Self Refresh supported

JEDEC standard 78ball FBGA(x8), 96ball FBGA(x16)

Driver strength selected by EMRS

Dynamic On Die Termination supported

Asynchronous RESET pin supported

ZQ calibration supported