Harman Kardon DPR 1001, Service Manual

Page: 132 / 165

FEATURES
◆
High-performance, E
2
CMOS 3.3-V & 5-V CPLD families
◆ Flexible architecture for rapid logic designs
— Excellent First-Time-Fit
TM
and refit feature
— SpeedLocking
TM
performance for guaranteed fixed timing
— Central, input and output switch matrices for 100% routability and 100% pin-out retention
◆ High speed
— 5.0ns t
PD
Commercial and 7.5ns t
PD
Industrial
— 182MHz f
CNT
◆ 32 to 512 macrocells; 32 to 768 registers
◆ 44 to 388 pins in PLCC, PQFP, TQFP, BGA, fpBGA and caBGA packages
◆ Flexible architecture for a wide range of design styles
— D/T registers and latches
— Synchronous or asynchronous mode
— Dedicated input registers
— Programmable polarity
— Reset/ preset swapping
◆ Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— JTAG (IEEE 1149.1) compliant for boundary scan testing
— 3.3-V & 5-V JTAG in-system programming
— PCI compliant (-5/-55/-6/-65/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system designs
— Programmable pull-up or Bus-Friendly
TM
inputs and I/Os
— Hot-socketing
— Programmable security bit
— Individual output slew rate control
◆ Advanced E
2
CMOS process provides high-performance, cost-effective solutions
◆ Supported by ispDesignEXPERT
TM
software for rapid logic development
— Supports HDL design methodologies with results optimized for ispMACH 4A
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
M 4A 3-32/32
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DPR1001 harman/kardon