Harman Kardon AVR 254, Service Manual

Page: 112 / 189

Advance Information
8 Mbit SPI Serial Flash
SST25VF080
©2003 Silicon Storage Technology, Inc. S71250-01-000 12/03
PIN DESCRIPTION
FIGURE 1: P
IN
A
SSIGNMENTS FOR
8-
LEAD
SOIC
TABLE 1: P
IN
D
ESCRIPTION
Symbol Pin Name Functions
SCK Serial Clock To provide the timing of the serial interface.
Commands, addresses, or input data are latched on the rising edge of the clock input, while output
data is shifted out on the falling edge of the clock input.
SI Serial Data
Input To transfer commands, addresses, or data serially into the device.
Inputs are latched on the rising edge of the serial clock.
SO Serial Data
Output To transfer data serially out of the device.
Data is shifted out on the falling edge of the serial clock.
CE# Chip Enable The device is enabled by a high to low transition on CE#. CE# must remain low for the duration of
any command sequence.
WP# Write Protect The Write Protect (WP#) pin is used to enable/disable BPL bit in the status register.
HOLD# Hold To temporarily stop serial communication with SPI flash memory without resetting the device.
V
DD
Power Supply To provide power supply voltage: 2.7-3.6V for SST25VF080
V
SS
Ground
T1.0 1250
1
2
3
4
8
7
6
5
CE#
SO
WP#
VSS
VDD
HOLD#
SCK
SI
Top View
1250 08-soic P1.0
112
AVR254
harman/kardon