Harman Kardon AVR 1650, Service Manual

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ADV7511 ADI Confidential HARDWARE USER’S GUIDE
Rev. PrB
Rev. PrB | Page 18 of 55
Table 3
Complete Pinout List ADV7511
Pin No. Mnemonic Type
1
Description
57-74, 78, 80-
96 D[35:0] I Video Data Input. Digital input in RGB or YCbCr format. Supports typical CMOS logic
levels from1.8V up to 3.3V. See ▶ Figure 2 for timing details.
79 CLK I Video Clock Input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
97 DE I Data Enable signal input for Digital Video. Supports typical CMOS logic levels from
1.8V up to 3.3V.
98 HSYNC I Horizontal Sync Input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
2 VSYNC I Vertical Sync Input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
28 R_EXT I Sets internal reference currents. Place 887 Ω resistor (1% tolerance) between this
pin and ground.
51 HEAC- I HEAC- is one of a pair of differential lines for the ARC (Audio Return Channel)
52 HEAC+ I HEAC+ is one of a pair of differential lines for the ARC (Audio Return Channel)
30 HPD I
Hot Plug Detect signal input. This indicates to the interface whether the sink is
connected. 1.8V to 5.0 V CMOS logic level.
10 S/PDIF I S/PDIF (Sony/Philips Digital Interface) Audio Input. This pin is typically used as
the audio input from a Sony/Philips digital interface. Supports typical CMOS logic
levels from 1.8V up to 3.3V. See
▶ Figure 4 for timing details.
46 S/PDIF_OUT O S/PDIF Audio Output from ARC receiver.
11 MCLK I Audio Reference Clock input. 128 × N × f
S
with N = 1, 2, 3, or 4. Set to 128 ×
sampling frequency (f
S
), 256 × f
S
, 384 × f
S
, or 512 × f
S
. Supports typical CMOS logic
levels from 1.8V up to 3.3V.
15-12 I
2
S[3:0] I I
2
S Audio Data Inputs. These represent the eight channels of audio (two per
input) available through I
2
S. Supports typical CMOS logic levels from 1.8V up to
3.3V. See
Figure
3 for timing details.
16 SCLK I I
2
S Audio Clock input. Supports typical CMOS logic levels from 1.8V up to 3.3V.
17 LRCLK I Left/Right Channel signal input. Supports typical CMOS logic levels from1.8V up to
3.3V.
8-3 DSD[5:0] I
DSD audio data inputs. See
▶
Figure 5 for timing details.
9 DSD_CLK I DSD Clock input. This is a 2.8224MHz clock for the DSD audio inputs.
38 PD/AD I Power-Down Control and I 2 C Address Selection. The I 2 C address and the PD
polarity are set by the PD/AD pin state when the supplies are applied to the
ADV7511. Supports typical CMOS logic levels from 1.8V up to 3.3V.
32, 33 TxC−/TxC+ O Differential TMDS Clock Output. Differential clock output at pixel clock rate;
TMDS logic level.
42, 43 Tx2−/Tx2+ O Differential TMDS Output Channel 2. Differential output of the red data at 10×
the pixel clock rate; TMDS logic level.
39, 40 Tx1−/Tx1+ O
Differential TMDS Output Channel 1. Differential output of the green data at 10×
the pixel clock rate; TMDS logic level.
35, 36 Tx0−/Tx0+ O Differential TMDS Output Channel 0. Differential output of the blue data at 10×
the pixel clock rate; TMDS logic level.
45 INT O Interrupt signal output. CMOS logic level. A 2 kΩ pull-up resistor (10%) to
interrupt the microcontroller IO supply is recommended.
29, 34, 41 AVDD P 1.8V Power Supply for TMDS Outputs.
1, 19, 49, 76,
77 DVDD P 1.8V Power Supply for Digital and I/O Power Supply. These pins supply power to
the digital logic and I/Os. They should be filtered and as quiet as possible.
24, 25 PVDD P 1.8V PLL Power Supply. These pins provide power to the digital portion of the
clock PLL. The designer should provide quiet, noise-free power to these pins.
21 PLVDD P 1.8V PLL Power Supply. The most sensitive portion of the ADV7511 is the clock
generation circuitry. These pins provide power to the analog portion of the clock
PLL (VCO). The designer should provide quiet, noise-free power to these pins.
26 BGVDD P Band Gap Vdd.
AVR 1650 harman/kardon
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