Haier L37V6-A8K, Service Manual, Page: 57 / 67

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CVDD_1.8
RMADDR10
R78 4.7K
R93 10K_NC
DDC_SDA_DVI 1
Close to respective power Pins
LV_O3
RMADDR16
R87
10K
LV_E6
RMDATA6
R235
4.7K
C140
100nF_SC
DDC_SCL_VGA 3
3.3V_AVDD
LV_E1
RX1- 1
RMADDR5
JP4
CONN3_250MM
1
2
3
RMADDR10
RMDATA2
C66
220pF
3.3V_AVDD
MCSDA_EE 2
LV_O4
Scart_Signal_2 1
AS_3 1
VGAHS
C81
100nF
R337
0R
RX1+
RMADDR0
UART_DO
C96
220pF
10K_NC R111
R325
0R/OP
PBIAS
LBADC_IN1
Initial state of OCM ROM:
RMDATA5
C57
100nF
+5V_5221
C112
100nF
DVS 5
ENBKL 4
RMADDR7
RMADDR2
BLUE-
R236
4.7K
FB14
1 2
R313 100R
LV_E3
RMADDR8
RMADDR3
C78
22uF
PD23
BLUE-
DVS
R103 10K_NC
RMADDR[6:0]
AS_2 1
R89 10K_NC
R234
4.7K
DDC_SCL_DVI 1
SOCKET:
IC51-2084-1052
RX0-
RXC+
GREEN+
R85
470K
C70
100nF
RX1+ 1
SPI_EN: 0 = parallel ROM I/F. 1 = SPI
serial ROM and Cache control
LV_E[0..9] 4,5
RMADDR12
RMADDR12
XTAL
RMADDR16
RMDATA3
R96 10K_NC
C89
15pF
RMADDR11
C59
100nF
R360 100R
C105 10nF
RMDATA5
R48 100
LV_E5
PWM1
C109
47pF
R107 10K_NC
DDC_SDA_VGA_1 3
3.3V_AVDD
RED-
X1
14.318MHz
C82
100nF
C72
100nF
AS_1 1
G_UART_DI
DDC_SCL_DVI
RMADDR1
R94
33K
RMADDR4
C80
100nF
RESETn 1,8,9,11
LV_E9
C63
100nF
R70 0R/OP
R326 100R
DHS 5
MCSCL_EE 2
RMADDR8
For I2C address [6:0] to JTAG bridge
Host I/F, to determine device address.
SELECT ONE
AVDD_1.8
RMADDR2 LBADC_IN3
DDC_SCL_VGA
R105 10K_NC
Close to respective power Pins
RMDATA[0..7]
RMADDR17
C58
100nF
RMADDR15
+1.8V_AVDD
LV_O1
R79 4.7K
RMDATA0
C71
100nF
RX2- 1
Scart_Signal_1 1
RMADDR9
C77
220pF
C103
10nF
C92
100nF
FB15
1 2
R73
47R
3.3V_DVDD
BRI 4
STBY_AMP 1
R311 100R
R137
12K
C94
100nF
5221 V0.1
RS LCD TV
C
7 12 Friday, April 22, 2005
Title
Size Document Number Rev
Date: Sheet of
GREEN-
RMADDR7
VGACON 3
LV_E0
RMADDR2
C95
100nF
ADCIN:
2.53–3.2V = SCART 4 3
接口有 ： 信号
1.33–2.13V = SCART 16 9
接口有 ： 信号
0–0.54V = SCART
接口无信号
+1.8V_DVDD
C61
100nF
R69
10K
RMADDR13
PD20
SW1
SW PUSHBUTTON
SOG 10
11 = External parallel control bus using
ROM Addr/Data
RX0+
GREEN-
RMDATA2
C90
22uF
R92 100
C60
100nF
R71
0R
R138 0R
KEYBOARD INPUT
TO LBW ADC
ROM_OEn
C55
100nF
C67
22uF
R76 0R
+3.3V_DVDD
ADC_IN1 2
RMADDR13
R359 100R
DEN 5
RMADDR[12:7]
R88
10K
YUV_TV_SW 10
RMADDR0
R90 100R_SC
C87
220pF
C93
100nF
C79
100nF
3.3V_AVDD
SDA
PPWR
DEN
MCSDA
R86
470K_NC
R100 10K_NC
CN9
TJC3-10A
1
2
3
4
5
6
7
8
9
10
DDC_SDA_VGA_1
RMADDR5
RX2+ 1
5VAON 6
IR_IN 2,8
RMADDR9
LV_O5
ENBKL
RMADDR11
C74
100nF
C53
22uF
BOOTSTRAP OPTIONS SELECT
(NOT POPULATED SHOULD BE
HARD WIRED)
C73
100nF
C101
10nF
User_Bits[5:0] for configuration setting
CN8
1
2
3
4
C111
100nF
MUTE 1
DHS
UART_DI
R98 10K_NC
C110
100nF
00 = Normal. UART in 186 on system pins.
BRI
RMDATA7
R133
33K
C86
220pF
R97
12K
DCLK C102
10nF
R47 100R
RMDATA1
RMDATA7
C91
100nF
AVSYNC 3
RX1-
GPROBE
DEBUG
PORT
DHS 5
C83
100nF
R361 100R
10K_NC R101
VGA_TV_SW 3
RX2+
LV_E7
LV_E4
RMADDR6
U15
AT49F020-70JC
3
29
28
4
25
23
26
27
5
6
7
8
9
10
11
12
21
20
19
18
17
15
14
13
24
31
32
1
16
2
30
22
A15
A14
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
OE
WE
VCC
NC
GND
A16
NC/A17
CE
RXC- 1
RMADDR[14:13]
RMADDR15
DDC_SDA_DVI
C113
100nF
Close to respective power Pins
10 = JTAG port, 5 wires
RX2-
RMADDR3
AHSYNC 3
STBY 6
STBY_34XY 1
LV_O2
PD22
RED+
RMADDR15
R106 10K
C100
100nF
+5V_5221
R102
10K
R80 270
RAIN 3
RMDATA[0..7]
C98
100nF
R95 10K_NC
Close to respective power Pins
ROM_CSn
BootStrap Signals
RMADDR1
LB
A
DC_G
N
D
R104 10K_NC
CVDD_1.8
+5V
RMADDR1
C104 10nF
R312 0
01 = I2C to JTAG bridge.
SoftReset
R99 10K_NC
C84
100nF
+5V_5221
RMADDR11
C75
100nF
+3.3V_AVDD
AVDD_1.8
PWM0 4
ADC_IN2 2
RMADDR6
RMADDR10
R108 10K_NC
R109 10K_NC
C69
100nF
C68
100nF
R247
4.7K
R74
47R
0 = internal ROM on, and mapped to top
32K of OCM and OCM boot will be from
internal ROM codes.
WP 2
3.3V_AVDD
RMADDR14
R314 0
C64
100nF
RXC+ 1
OSC_SEL: 0 = Xtal and internal oscillator.
1 = TTL oscillator (on TCLK pin)
+5V
TCLK
RMDATA3
C54
100nF
C56
100nF
OP_MODE[1:0]:
3.3V_DVDD
C107 100pF
R110 10K_NC
PBIAS 4
3.3V_A
AGND
U14
gm5221
PQFP208
151
152
147
148
142
143
119
118
124
123
129
128
169
170
98
99
100
101
35
36
133
132
114
71
72
77
78
79
80
178
92
93
69
202
201
200
199
198
197
196
195
194
185
4
3
2
1
208
207
204
203
186
187
193
189
192
188
5
154
150
149
153
144
122
117
23
50 73 190 205 166 9 41 75 96 116
67
68
12
121
25
126
28
115
171
26
172
24
137
11
164
181
182
8
42
51
74
76
94
97
140
180
163
165
136
155
48
47
87
86
66
65
33
34
62
59
61
60
58
57
63
64
46
45
44
43
38
37
55
56
32
31
30
29
22
21
49
54
18
17
16
15
14
13
19
20
167
70
135
27
40
113
120
125
130
134
141
145
7
6
95
184
183
191
206
139 179
177
39
168
156
131
127
146
81
82
83
84
85
88
89
90
91
138
10
102 103 106 107 108 109 110 111 112 52 53 104 105 157 158 159 160 161 162
173
174
175
176
RED+
RED-
GREEN+
GREEN-
BLUE+
BLUE-
RX2-
RX2+
RX1-
RX1+
RX0-
RX0+
XTAL
TCLK
PWM0/GPIO11
PWM1/GPIO12
PWM2/GPIO13
PWM3/GPIO14
CH1P_LV_O(PD16/EB0)
CH1N_LV_O(PD17/EB1)
RXC-
RXC+
REXT
HOST_SCL/UART_DI
HOST_SDA/UART_DO
DDC_SCL_VGA
DDC_SDA_VGA
DDC_SCL_DVI
DDC_SDA_DVI
RESETn
GPIO9/SCL
GPIO10/SDA
STI_TM1/GPIO15
ROM_ADDR0
ROM_ADDR1
ROM_ADDR2
ROM_ADDR3
ROM_ADDR4
ROM_ADDR5
ROM_ADDR6
ROM_ADDR7
ROM_ADDR8
ROM_ADDR15
ROM_DATA0
ROM_DATA1
ROM_DATA2
ROM_DATA3
ROM_DATA4
ROM_DATA5
ROM_DATA6
ROM_DATA7
ROM_ADDR14
ROM_ADDR13
ROM_ADDR9
ROM_ADDR11
ROM_ADDR10
ROM_ADDR12
ROM_OEn
AVDD_ADC_33
AVDD_RED_33
AGND_GREEN
AGND_RED
AGND_BLUE
AGND_RX1
AGND_RX2
AVSS_OUT_LV_E
RV
DD_33
RV
DD_33
RV
DD_33
RV
DD_33
V
DD_RP
LL_18
CV
DD_18
CV
DD_18
CV
DD_18
CV
DD_18
V
DD_RX
2_18
PPWR
PBIAS
AVSS_OUT_LV_E
V
DD_RX
1_18
AVSS_LV
V
DD_RX
0_18
AVSS_OUT_LV_O
AGND_IMB
AVDD_RPLL_33
AVDD_LV_33
LBADC_VDD_33
AVDD_OUT_LV_E_33
V
DD_RX
P
LL_18
AVDD_OUT_LV_E_33
V
DD1_A
DC_18
HSYNC
VSYNC
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
CRVSS
GND1_ADC
GND_RPLL
GND_RXPLL
ADC_TEST
DHS
DEN
CRVSS
CV
DD_18
PD37/OG5
PD33/OG1
CH2P_LV_O(PD14/EG6)
CH2N_LV_O(PD15/EG7)
PD30/OR6
PD27/OR3
PD29/OR5
PD28/OR4
PD26/OR2
PD25/OR1
PD31/OR7
PD32/OG0
PD23/EB7
PD22/EB6
PD21/EB5
PD20/EB4
CH0N_LV_O(PD19/EB3)
CH0P_LV_O(PD18/EB2)
DCLK
PD24/OR0
CLKN_LV_O(PD13/EG5)
CLKP_LV_O(PD12/EG4)
CH3N_LV_O(PD11/EG3)
CH3P_LV_O(PD10/EG2)
CH0N_LV_E(PD9/EG1)
CH0P_LV_E(PD8/EG0)
DVS
NC
CH2N_LV_E(PD5/ER5)
CH2P_LV_E(PD4/ER4)
CLKN_LV_E(PD3/ER3)
CLKP_LV_E(PD2/ER2)
CH3N_LV_E(PD1/ER1)
CH3P_LV_E(PD0/ER0)
CH1P_LV_E(PD6/ER6)
CH1N_LV_E(PD7/ER7)
VBUFC_RPLL
STI_TM2
VBUFC_DVI
AVDD_OUT_LV_O_33
AVDD_OUT_LV_O_33
AVDD_IMB_33
AVDD_RX2_33
AVDD_RX1_33
AVDD_RX0_33
AVDD_RXC_33
AVDD_BLUE_33
AVDD_GREEN_33
ROM_CSn
ROM_WEn
RV
DD_33
ROM_ADDR16
ROM_ADDR17
CRVSS
CRVSS
CV
DD_18
CV
DD_18
LBADC_GND
AVSS_OUT_LV_O
AGND_RPLL
AGND_ADC
AGND_RXC
AGND_RX0
SOG_MCSS
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
GPIO6
GPIO7/IRQin
GPIO8/IRQout
CLKOUT
VCO_LV
VD
AT
A7
/G
PIO
1
6
VD
AT
A6
/G
PIO
1
7
VD
AT
A5
/G
PIO
1
8
VD
AT
A4
/G
PIO
1
9
VD
AT
A3
/G
PIO
2
0
VD
AT
A2
/G
PIO
2
1
VD
AT
A1
/G
PIO
2
2
VD
AT
A0
/G
PIO
2
3
VC
L
K
NC NC NC NC NC NC NC NC NC NC
LBADC_IN1
LBADC_IN2
LBADC_IN3
LBADC_RETURN
+5V_5221
DVS 5
GAIN 3
MCSDA 1,2,8,9,11
T_STATE 11
LV_O9
LV_O6
RMADDR5
R409
10K
R238 3.3K
LV_E2
G_UART_DO
R237
4.7K
FB28 FB/OP
1 2
C106 10nF
R91 10K_NC
FB16
FB0805
1 2
PD21
BLUE+
RMADDR4
R75
47R
RMADDR14
C97
220pF
RMDATA6
FB17
1 2
C88
15pF
+5V_5221
RMADDR6
FB27 FB
1 2
RMADDR17
TEMP_DETECT 6
RMADDR14
LV_O7
RMADDR16
RMADDR0
LBADC_IN2
R77 0R
R83 100R/OP
RaisingSun Co.Ltd
RMADDR8
RXC-
C65
100nF
R328 0R/OP
VGAVS
C108
47pF
R68
10K
RX0- 1
PPWR 4
RMADDR7
GPIO1
S
o
ft
R
es
et
RED-
C76
100nF
LED 2
RMADDR17
RMADDR9
RS232
+5V_5221
PD[20..23] 5
RMADDR12
SCL
R327 100R
BAIN 3
+5V
GPIO0
RMADDR15
RMDATA4
1 = Internal ROM off. The external ROM
mapped to entire upper 512K of OCM
address. OCM boot from external ROM
code.
RMDATA4
MCSCL
RX0+ 1
J5
JUMPER
1 2
3.3V_AVDD
MP3_GPIO 8
CVDD_1.8
C85
100nF
+5V_5221
MCSCL 1,2,8,9,11
LV_O0
RMADDR17
R336
4.7K/OP
C99 10nF
Close to respective power Pins
VBI_INTR 9
LV_E8
RMADDR3
R72 3.3K/OP
LV_O8
RMADDR4
Route (LBADC_IN1, LBADC_RET) and
(LBADC_IN2, LBADC_RET) as differential
tracks close to each other and ground the
return track of each pair very close to the
5221 and ground pin
ROM_WEn
RMADDR16
RMDATA0
C62
100nF
32-Pin PLCC Socket
+5V_5221
SOG_MCSS
RMADDR13
3.3V_DVDD
RMDATA1
DCLK 5
3.3V_DVDD
LV_O[0..9] 4,5
VS1 1
R84
470K