Grundig STR-622 TWIN Service Manual Download Page 17

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STR 622 TWIN

Schaltungsbeschreibung / Circuit Description

GRUNDIG Service

2 - 5

4. Audio Path

Note to the Audio Demodulator block circuit diagram:
Where two pin numbers are given two circuits exist, one for each stereo
channel. The first number is for the Right channel.

Audio Demodulator Block Diagram

The FM audio demodulator is of the Phase Locked Loop (PLL) type.

FM signals in the tuner Baseband Video signal are filtered by CC1014,
L1014, CC1016, L1016, L1019, CC1017, CR1017, L1017 which
removes unwanted Video components from FM in.

It is important that the drive level of the signals being demodulated is
fixed so that the output amplitude from the demodulator can be
predicted. To help achieve this the input signal passes through a gain
controlled amplifier G1, whose gain is set by one of two level detectors.
When a signal is first selected Level Detector 1, which senses the
combined FM signal amplitude, is used to set G1 to an approximately
correct gain. Once PLL lock has been reached Level Detector 2 is used
which accurately monitors the actual signal level within the working PLL.

When a new audio carrier is being selected the PLL must be tuned to the new
frequency. To do this S1 is closed and the Voltage Controlled Oscillator
(VCO) is adjusted by means of the Frequency Synthesiser. The VCO
frequency is read by the Frequency Counter. Once the VCO is on frequency
S1 is opened and the VCO locks onto the incoming carrier of the same
frequency. The control loop feedback signal at the input of G2 carries the FM
modulation. The gain of G2 can be controlled to handle different FM
deviations. Loop stability is maintained by the PLL filter.
Control of all functions in the Demodulator is via the I

C bus (SDA, SCL)

from IC1401.

Note to the block diagram Audio Processing:
Where two pin numbers are given two circuits exist, one for each stereo
channel. The first number is for the Right channel.

Audio Processing Block Diagram

AMPLOCK

V/I

VCO

Level

Detector 1

Level

Detector 2

Frequen cy

Counter

Frequen cy

Synt

hesizer

To Audio
Processing

AGC

FM in

C-PUMP

IC1100 STV0056A

SDA

SCL

{

C Bus

46 ,41

49,38

42,26

47,39

PLL

Filter

Pin 61:
Data output to the Remote Cinch socket, e. g. for data link transfer.
Pin 62:
VDR-output to the display unit.
Pin 63:
Switching voltage U

22kHz

switches the 22kHz frequency, IC1100-(29),

to IC1650-(1) and this voltage is superimposed on the "LNC Power"
supply to drive the LNC's. This 22kHz output signal can optionally also
be pulse-modulated with a DiSEqC protocol.
Pin 64:
Switching voltage U

14/18V A

to select horizontal or vertical polarity on

voltage-controlled polarotors; "High" = horizontal.
Pin1:
Switching voltage U

LNC OFF

to switch off the LNC supply.

Pin 2:
Switching voltage U

Standby

to switch off the +12V and +5V supplies.

Pin 13:
Data input from the Remote Cinch socket for remote control
(e. g. Timer operation) by a video recorder.
Pin 19:
Scans whether there is a sync signal fed out from the sync signal
detector circuit CIC1331. If the signal is too low or poor the

P switches

to the internal synchronising signal and the screen background be-
comes blue. With the "green" key on the remote control handset it is
possible to change the background to green.
Pin 21:
AV switching voltage input for evaluation of the switching voltage on pin
8 of the decoder socket. If "AV IN1" is at high level the video signal is
fed back to the receiver via the connected descrambler.
Pin 22:
AV switching voltage input for evaluation of the switching voltage on pin
8 of the VCR socket. At high level "AV IN 2" the VCR signal is looped
through to the TV receiver (matrix).
Pin 23:
Control voltage U

AFC VCR

for VCR Tuner frequency control, contact 1.

Pin 24:
Control voltage U

AFC TV

for TV Tuner frequency control, contact 1.

Pins 47, 48:
System data and clock lead (I

C-bus) to control the Tuner, Video

Processor-IC1100 or IC2100, OSD Processor CIC1331, Clock-
CIC1120, Memory-CIC1140.
Pin 49:
AV 2 switching voltage generation to pin 8 of the VCR-socket.
Pins 50...54:
LED drive on the display unit.
Pin 37:
Enable signal CS

OSD

(Chip Select OSD) for the OSD Controller IC1331.

Pin 38:
RGB/TV switching voltage for changing over the Scart sockets (ma-
trix). When the RGB/TV switching voltage is at "High", CT1270,
CT1276 switch the TV receiver to RGB mode.
Pin 39:
AV 3 switching voltage generation to pin 8 of the TV-socket.
Pin 40/41:
Serial clock and data lead to drive clock CIC1120
Pin 42:
For switching the decoder socket to VCR 2
Pin 43:
Like pin 64, U

14/18V B

but for VCR input stage.

Pin 44:
Like pin 63, U

22kHz B

but for VCR input stage.

2.2 Non Volatile Memory
NVM CIC1140 is a serial EEPROM and contains all factory and user
programmable data to configure the receiver (channel table, deviation,
polarity etc.).

3. Tuner

All functions within the tuner are controlled from CIC1401 via I

C Bus.

The IF signals from the LNC, in the range 950MHz to 2150MHz, are
supplied to the aerial inputs.
The LNC-inputs are AC-coupled into a variable amplifier whose gain
is adjusted automatically by the AGC to ensure a constant level at the
input to the FM Demodulator. At the output contact 4 of the tuner the
baseband signal is available together with the 25Hz energy dispersal
waveform signal.
To improve the picture quality resulting from a noisy transmitter signal
a "threshold" circuit can be activated in the tuner via the menu.

N RS

Passi v e
A udi o
D e-em phasi s

6dB

28,27

25,24

51,52

2,54

3,53

1,55

33,34

48,40

14,12