4 Configuration Process
4.2 Initialization
UG290-2.5.2E
11(98)
Series
Device
Power Rails
GW2AN-18X
GW2AN-55
VCC/VCCX/VCCO3
GW2ANR
GW2ANR-18
VCC/VCCX/VCCO3
4.2
Initialization
After the power on reset circuit drives the READY and DONE status
pins low, the FPGAs enter the memory initialization immediately. The
purpose of the initialization is to clear all the SRAM memory inside the
FPGA.
The FPGA remains in the initialization state until all of the following
conditions are met:
The T
INITL
time period has elapsed.
The RECONFIG_N pin is high.
The READY pin is not driven low by an external driver.
The READY pin provides two functions during the initialization phase:
To indicate that the FPGA is currently clearing its configuration SRAM
To act as an input preventing the FPGA transition from the initialization
state to the configuration state when it’s driven low by an eternal driver.
4.3
Configuration
The rising edge of the READY pin causes the FPGA to enter the
configuration state. The internal configuration SRAM of FPGA can be
configured via multiple modes according to the MODE pin values. During
the time the FPGA receives its configuration data, the READY pin can
indicate its internal state. When READY is high, configuration proceeds
without issue. If READY is low, an error has occurred and the FPGA does
not operate.
4.4
Wake-up
When all the configuration data is reveived correctly, the FPGA enters
the wake-up state and set the internal status bit of DONE to 1. In the
wake-up state, the FPGA will perform the following operations in sequence:
1.
Enable the Global output enable (GOE) signal, and then the FPGA I/O
exits a high-impedance state and take on its programmed function. The
input signals are prevented from performing any action on the FPGA
flip-flops by the assertion of the Global Set/Reset (GSR).
2.
Release the Global Set/Reset (GSR) signal and the Global Write
Disable (GWDISn) signal. Enabling the Global Write Disable (GWDISn)
signalp revents the FPGA from mistakenly overwriting the initialization
data in the internal RAM.
3.
Enable the external DONE pin. The external DONE is a bidirectional,
open-drain I/O when it’s enabled. Keep the FPGA wake-up by
externally driving the DONE pin low. When the DONE pin is driven high,
the FPGA wake-up pahse is complete and enters user mode.
