GOWIN GW1NSE Series, User Manual

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2 Overview 2.6 I/O BANK Introduction
UG874-1.0E 8(14)
Pin Name I/O Description
VCCPLL NA Power supply pins in PLL
USB Power supply pin
DM
NA USB data pin Data-
DP NA USB data pin Data+
REXT NA 12.7K high-accuracy resistance
XIN NA Crystal input signals
XOUT NA Crystal oscillator signals
IDPAD NA ID signal
VBUSPAD NA VBUS signal
VDDA NA
Analog power supply voltage,
VDDA=3.3V
VDDAUSB NA Analog power supply pin (3.3V)
VDDDUSB NA Analog power supply pin (3.3V)
VDDPL NA Power supply pin for driver (1.2V)
2.6 I/O BANK Introduction
There are four I/O Banks in the GW1NSE series of SecureFPGA
products. The I/O BANK Distribution of the GW1NSE series of
SecureFPGA products is as shown in Figure 2-1.
Figure 2-1 GW1NSE series of SecureFPGA Products I/O Bank Distribution
GW1NS
I/O BANK0
I/O BANK2
I/O
B
A
N
K
1
I/O
B
A
N
K
3
This manual provides an overview of the distribution view of the pins in
the GW1NSE series of SecureFPGA products. The eight I/O Banks that
form the GW1NSE series of SecureFPGA products are marked with eight
different colors.
Various symbols are used for the user I/O, power, and ground. The
various symbols and colors used for the various pins are defined as
follows:

" " denotes the I/O in BANK0. The filling color changes with the