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3 Development Board Circuit

3.4 Clock, Reset

DBUG359-1.2E

14(27)

Signal Name Pin No.

BANK

Description

I/O

VCCPLLL0

8

-

PLLL0 power

1.0V

VCCPLLR0

104

-

PLLR0 power

1.0V

VCCPLLR1

81

-

PLLR1 power

1.0V

VCCPLL1

36

-

PLLL1 power
is internally short-circuited.

1.0V

VCCX

31, 55

-

Auxiliary voltage
The auxiliary voltage and
VCCO4, VCCO6 are
internally short-circuited.

3.3V

VCC

1, 36, 73, 108 -

Core voltage

1.0V

VSS

2, 17, 53, 74,
89, 107

-

GND

-

3.4

Clock, Reset

3.4.1

Overview

A 50MHz crystal oscillator is provided in the development board that

connects to the PLL input pin. This can be employed as the input clock for
the the PLL in FPGA, and the output clock as needed via multiplication and
division of the PLL frequency.

For easier debugging, one reset signal is added on the development

board. It's low active.

3.4.2

Clock, Reset

Figure 3-5 Clock, Reset

6

135

KEY3

50MHz

ADM811

3.3V

FPGA_RST_N

FPGA_CLK

U9

U7

X4

GW2AR18_V1.1

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Summary of Contents for DK START GW2AR18 V1.1

Page 1: ...DK_START_GW2AR18_V1 1 User Guide DBUG359 1 2E 09 03 2021 ...

Page 2: ... mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions ...

Page 3: ...tory Date Version Description 01 15 2019 1 0E Initial version published 09 12 2019 1 1E One precaution added 09 03 2021 1 2E The Quick Start in 2 2 A Development Board Suite removed The chapter 6 Quick Start added ...

Page 4: ...cription 3 2 1 Overview 3 2 2 A Development Board Suite 4 2 3 PCB Components 5 2 4 System Architecture 5 2 5 Features 6 2 6 Development Board Specification 7 3 Development Board Circuit 9 3 1 FPGA Module 9 3 1 1 Overview 9 3 1 2 I O BANK Introduction 10 3 2 Download 11 3 2 1 Overview 11 3 2 2 USB Download Circuit 11 3 2 3 Download Flow 12 3 2 4 Pinout 12 3 3 Power Supply 12 3 3 1 Overview 12 3 3 2...

Page 5: ... 3 6 1 Overview 16 3 6 2 Switch Circuit 16 3 6 3 Pins Distribution 16 3 7 Key 16 3 7 1 Overview 16 3 7 2 Key Circuit 17 3 7 3 Pinout 17 3 8 GPIO 17 3 8 1 Overview 17 3 8 2 GPIO Circuit 18 3 8 3 Pinout 18 3 9 LVDS 21 3 9 1 Overview 21 3 9 2 LVDS Circuit 21 3 9 3 Pinout 21 3 10 Ethernet 23 3 10 1 Overview 23 3 10 2 Ethernet Circuit 23 3 10 3 Pinout 23 4 Considerations 25 5 Gowin Software 26 6 Quick ...

Page 6: ... 5 Figure 3 1 GW2AR I O Bank Distribution 10 Figure 3 2 View of GW2AR 18 EQ144 Pinout Top View 10 Figure 3 3 Connection Diagram for FPGA USB Downloading 11 Figure 3 4 Power System Distribution 13 Figure 3 5 Clock Reset 14 Figure 3 6 LED Circuit 15 Figure 3 7 Switch Circuit 16 Figure 3 8 Key Circuit 17 Figure 3 9 GPIO Circuit 18 Figure 3 10 LVDS Circuit 21 Figure 3 11 Ethernet Download Connection 2...

Page 7: ...GA Download and Pinout 12 Table 3 4 FPGA Power Pinout 13 Table 3 5 FPGA Clock and Reset Pinout 15 Table 3 6 LED Pinout 15 Table 3 7 Clock Circuit Pinout 16 Table 3 8 Key Pinout 17 Table 3 9 J5 GPIO Pinout 18 Table 3 10 J14 GPIO Pinout 19 Table 3 11 J2 GPIO Pinout 20 Table 3 12 J15 GPIO Pinout 20 Table 3 13 J3 FPGA Pinout 21 Table 3 14 J4 FPGA Pinout 22 Table 3 15 Ethernet1 Pinout 23 Table 3 16 Eth...

Page 8: ...development board 4 Introduction to the use of the FPGA development software 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS226 GW2AR series of FPGA Products Data Sheet 2 UG229 GW2AR series of FPGA Products Package and Pinout 3 U115 GW2AR 18 Pinout 4 UG290 Gowin FPGA Products Programming and Configurat...

Page 9: ... 8 input Look up Table REG Register ALU Arithmetic Logic Unit IOB Input Output Block S SRAM Shadow SRAM B SRAM Block SRAM SP Single Port SDP Semi Dual Port DP Dual Port DSP Digital Signal Processing TDM Time Division Multiplexing DQCE Dynamic Quadrant Clock Enable DCS Dynamic Clock Selector PLL Phase locked Loop DLL Delay locked Loop EQ144 EQFP144 1 4 Support and Feedback Gowin Semiconductor provi...

Page 10: ...n difference between the GW2A series and the GW2AR series is that the GW2AR series integrates abundant memories The GW2AR series also provides high performance DSP resources a high speed LVDS interface and abundant BSRAM resources These embedded resources in combination with a streamlined FPGA architecture with 55nm process make the GW2AR series of FPGA products suitable for high speed and low cos...

Page 11: ...oard Suite DBUG359 1 2E 4 27 2 2 A Development Board Suite A development board suite includes the following items DK_START_GW2AR18_V1 1 development board USB cable Figure 2 2 A Development Board Suite 1 2 DK_START_GW2AR18_V1 1 development board USB Cale ...

Page 12: ...V OSC LED Switch Reset Mode Control FPGA Download 5V IN FLASH FPGA GPIO LVDS Power ON OFF Ethernet 1 8V 2 4 System Architecture Figure 2 4 System Architecture 4 LED 2 SWITCH OSC 50MHz MINI USB 5Pairs LVDS INPUT 2 BUTTON 5Pairs LVDS OUTPUT 2 10PIN GPIO 2 Ethernet FPGA USB Download Interface 1 26PIN GPIO GW2AR18_V1 1 DC5V IN MINI USB 3 3V 1 8V 1 0V 1 20PIN GPIO ...

Page 13: ...onfiguration Mode JTAG MSPI Multi BOOT 3 Clock resource 50MHz Clock Crystal Oscillator 4 Key switch and slide switch One reset button Two key switches Two slide switches 5 LED One power indicator green One DONE indicator green Four LEDs green 6 Memory 64Mbit built in PSRAM 7 LVDS 5 pairs of LVDS differential input 5 pairs of LVDS differential output 8 GPIO 50 I O expansion resources 9 Ethernet 2 E...

Page 14: ... via 5V 1 0V circuit 4 Slide Switches Available for testing 2 5 Key Switches Available for testing 2 6 Reset button Reset for FPGA 1 7 LED Test indicator DONE indicator Power indicator Four Test indicators green One DONE indicator green One Power indicator green 8 Crystal Oscillator Provide 50MHz clock for FPGA Package5032 9 Memory Offers PSRAM 64Mbit built in PSRAM 10 GPIO I O convenient for user...

Page 15: ...ecification DBUG359 1 2E 8 27 No Item Functions Technical Conditions Note between positive and negative anodes of power outlet 2A self recovery fuses are connected at power inlet 14 Voltage Input Voltage 5V 15 Humidity 95 16 Temperature Operating range 20 70 ...

Page 16: ...t in Table 3 1 Table 3 1 GW2AR 18 FPGA Resources List Device GW2AR 18 LUT4 20 736 Flip Flop FF 15 552 Shadow SRAM S SRAM bits 41 472 Block SRAM B SRAM bits 828K B SRAM quantity 46 PSRAM bits 64M 18 x 18 Multiplier 48 Maximum1 PLLs DLLs 4 4 Total number of I O banks 8 Max user I O2 140 Core voltage 1 0V Note See DS226 GW2AR series of FPGA Products Data Sheet for further details ...

Page 17: ... O BANK Introduction There are four I O Banks in the GW2AR series of FPGA products as shown in Figure 3 1 Figure 3 1 GW2AR I O Bank Distribution GW2AR IO Bank0 IO Bank1 IO Bank2 IO Bank3 IO Bank4 IO Bank5 IO Bank6 IO Bank7 Figure 3 2 View of GW2AR 18 EQ144 Pinout Top View ...

Page 18: ... clock input GPIO 3 2 Download 3 2 1 Overview The development board provides an USB download interface The data stream file can be downloaded to the internal SRAM or the external flash as needed Note When downloaded to SRAM the data stream file will be lost if the device is power down and it will need to be downloaded again after power on If downloaded to flash the data stream file will not be los...

Page 19: ...downloading Set J13 J9 and J10 to 0 power on and then the device will import the bitstream file to SRAM from the external Flash 3 2 4 Pinout Table 3 3 FPGA Download and Pinout Signal Name Pin No BANK Description I O TMS 13 2 JTAG Signal 1 8V TCK 14 2 JTAG Signal 1 8V TDI 16 2 JTAG Signal 1 8V TDO 18 2 JTAG Signal 1 8V MODE0 144 0 One Mode selection pin 3 3V MODE1 142 0 One Mode selection pin 3 3V ...

Page 20: ...O3 VCCO4 VCCO5 VCCO6 VCCX Ethernet LED SWTICH BUTTON FPGA VCCO2 VCCO7 PSRAM FPGA VCC 3 3 3 FPGA Power Pinout Table 3 4 FPGA Power Pinout Signal Name Pin No BANK Description I O VCCO0 127 0 I O Bank Power 3 3V VCCO1 109 1 I O Bank Power 3 3V VCCO2 103 2 I O Bank Power 1 8V VCCO3 77 91 3 I O Bank Power 3 3V VCCO4 55 4 I O Bank Power 3 3V VCCO5 37 5 I O Bank Power 3 3V VCCO6 31 6 I O Bank Power 3 3V ...

Page 21: ...ed 3 3V VCC 1 36 73 108 Core voltage 1 0V VSS 2 17 53 74 89 107 GND 3 4 Clock Reset 3 4 1 Overview A 50MHz crystal oscillator is provided in the development board that connects to the PLL input pin This can be employed as the input clock for the the PLL in FPGA and the output clock as needed via multiplication and division of the PLL frequency For easier debugging one reset signal is added on the ...

Page 22: ...isplay the required status In addition two LEDs are reserved to signify power supply and FPGA loading status Users can test the LEDs in the following ways If the output signal of related pins is logic low LED is on If the logic is high LED is off 3 5 2 LED Circuit Figure 3 6 LED Circuit LED1 124 LED2 125 LED3 126 LED4 128 VCC3P3 F_LED1 F_LED2 F_LED3 F_LED4 U9 GW2AR18_V1 1 3 5 3 Pinout Table 3 6 LE...

Page 23: ... 7 Switch Circuit SW1 141 SW2 136 VCC3P3 U9 F_SW1 F_SW2 GW2AR18_V1 1 3 6 3 Pinout Table 3 7 Clock Circuit Pinout Signal Name Pin No BANK Description I O F_SW1 141 0 Slide Switch1 3 3V F_SW2 136 0 Slide Switch2 3 3V 3 7 Key 3 7 1 Overview Two key switches are embedded in the development board Users can manually input the 0 1 signal to the corresponding FPGA pins for testing purposes Press the key t...

Page 24: ...VCC3P3 GW2AR18_V1 1 3 7 3 Pinout Table 3 8 Key Pinout Signal Name Pin No BANK Description I O F_KEY1 129 0 KEY1 3 3V F_KEY2 130 0 KEY2 3 3V 3 8 GPIO 3 8 1 Overview Two 2 54mm DC3 10P sockets one 2 54mm DC3 20P socket and one 2 54mm DC3 26P socket are reserved on the development board for user function extension and testing purposes ...

Page 25: ...9 H_A_IO11 H_A_IO13 H_A_IO15 H_A_IO8 H_A_IO10 H_A_IO12 H_A_IO14 H_A_IO16 J14 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 VCC3P3 H_B_IO11 H_B_IO13 H_B_IO15 H_B_IO10 H_B_IO12 H_B_IO14 H_B_IO16 J15 H_A_IO17 H_A_IO18 H_B_IO17 H_B_IO18 H_A_IO6 21 23 25 22 24 26 H_A_IO20 H_A_IO22 H_A_IO24 H_A_IO26 H_A_IO19 H_A_IO21 H_A_IO23 H_A_IO25 H_B_IO8 H_B_IO9 H_B_IO20 H_B_IO22 H_B_IO19 H_B_IO21 3 8 3 Pinout...

Page 26: ...put 5V H_A_IO8 24 7 6 General I O 3 3V H_A_IO7 12 8 7 General I O 1 8V H_A_IO10 26 9 6 General I O 3 3V H_A_IO9 23 10 6 General I O 3 3V H_A_IO12 28 11 6 General I O 3 3V H_A_IO11 25 12 6 General I O 3 3V H_A_IO14 30 13 6 General I O 3 3V H_A_IO13 27 14 6 General I O 3 3V H_A_IO16 33 15 6 General I O 3 3V H_A_IO15 29 16 6 General I O 3 3V H_A_IO18 35 17 6 General I O 3 3V H_A_IO17 32 18 6 General ...

Page 27: ...Pinout Signal Name Pin No Socket Pin No BANK Description I O GND 1 GND VCC3P3 2 3 3V Output 3 3V GND 3 GND VCC3P3 4 3 3V Output 3 3V H_B_IO8 122 5 0 General I O 3 3V 6 H_B_IO10 90 7 3 General I O 3 3V H_B_IO9 123 8 0 General I O 3 3V H_B_IO12 87 9 3 General I O 3 3V H_B_IO11 92 10 3 General I O 3 3V H_B_IO14 85 11 3 General I O 3 3V H_B_IO13 88 12 3 General I O 3 3V H_B_IO16 83 13 3 General I O 3 ...

Page 28: ...LVDS_A2_N F_LVDS_A3_N F_LVDS_A4_N F_LVDS_A5_N J3 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_B1_P F_LVDS_B2_P F_LVDS_B3_P F_LVDS_B4_P F_LVDS_B5_P F_LVDS_B1_N F_LVDS_B2_N F_LVDS_B3_N F_LVDS_B4_N F_LVDS_B5_N J4 3 9 3 Pinout Table 3 13 J3 FPGA Pinout Signal Name Pin No Socket Pin No BANK Description I O F_LVDS_A1_P 140 1 0 A Channel 1 3 3V F_LVDS_A1_N 139 2 0 A Channel 1 3 3V GND 3 GND ...

Page 29: ...J4 FPGA Pinout Signal Name Pin No Socket Pin No BANK Description I O F_LVDS_B1_P 119 1 1 B Channel 1 3 3V F_LVDS_B1_N 118 2 1 B Channel 1 3 3V GND 3 GND 4 F_LVDS_B2_P 117 5 1 B Channel 2 3 3V F_LVDS_B2_N 116 6 1 B Channel 2 3 3V GND 7 GND 8 F_LVDS_B3_P 115 9 1 B Channel 3 3 3V F_LVDS_B3_N 114 10 1 B Channel 3 3 3V GND 11 GND 12 F_LVDS_B4_P 113 13 1 B Channel 4 3 3V F_LVDS_B4_N 112 14 1 B Channel 4...

Page 30: ..._GTCLK PHY1_TXD0 PHY1_RXDV PHY_MDC PHY_MDIO 62 63 64 46 61 45 68 69 70 71 72 GW2AR18_V1 1 PHY2_TXD3 Ethernet PHY 51 52 U9 J8 RJ45 PHY2_TXEN 54 PHY2_RXC U6 PHY2_RXD0 PHY2_RXD1 PHY2_RXD2 PHY2_RXD3 PHY2_TXD1 PHY2_TXD2 PHY2_GTCLK PHY2_TXD0 PHY2_RXDV PHY_MDC PHY_MDIO 48 49 50 46 47 45 56 57 58 59 60 GW2AR18_V1 1 3 10 3 Pinout Table 3 15 Ethernet1 Pinout Signal Name Pin No BANK Description I O PHY_MDC 4...

Page 31: ...receive enable 3 3V Table 3 16 Ethernet2 Pinout Signal Name Pin No BANK Description I O PHY_MDC 45 5 PHY2 management interface clock 3 3V PHY_MDIO 46 5 PHY2 management interface data 3 3V PHY2_GTCLK 47 5 RGMII MII transmitter clock 3 3V PHY2_TXD0 48 5 RGMII MII transmitter data 3 3V PHY2_TXD1 49 5 RGMII MII transmitter data 3 3V PHY2_TXD2 50 5 RGMII MII transmitter data 3 3V PHY2_TXD3 51 5 RGMII M...

Page 32: ... 1 Handle with care and pay attention to electrostatic protection 2 When you program the external FLASH please refer to the MODE value in Gowin FPGA products programming and configuration Guide 3 When the LVDS differential signal is used as input the built in 100Ω terminating resistor needs to be enabled ...

Page 33: ...5 Gowin Software DBUG359 1 2E 26 27 5 Gowin Software Please refer to SUG100 Gowin Software User Guide for details ...

Page 34: ...6 Quick Start DBUG359 1 2E 27 27 6 Quick Start See TN431 DK_START_GW2AR18_V1 1 Development Board Quick Start User Guide for details ...

Page 35: ......

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