3 Development Board Circuit
3.5 LED
DBUG388-1.0E
13(22)
3.4.1
Overview
The development board provides a 50MHz crystal oscillator connected
to the PLL input pin. This can be employed as the input clock for the PLL in
FPGA. Frequency division and multiplication of PLL can output the clock
required by the user.
3.4.2
Clock, Reset
Figure 3-4 Clock, Reset
22
23
KEY2
50MHz
ADM811
3.3V
F_RST_N
F_CLK
U1
U2
X2
GW1NS4/GW1NSR4/GW1NSER4
SN74
AVC4
T245
U26
3.4.3
Pins Distribution
Table 3-3 FPGA Clock and Reset Pins Distribution
Signal Name
Pin No.
BANK
Description
I/O Level
FPGA_CLK
22
3
50MHz crystal oscillator
Input
1.8V
FPGA_RST_N
23
3
Reset Signal, Active Low 1.8V
3.5
LED
3.5.1
Overview
There is one green LED in the development board and users can
display the required status through the LED. There are two LEDs left to
facilitate the observation of power supply and FPGA loading status.
Users can test the LEDs in the following ways:
When the FPGA corresponding pin output signal is logic low , the LED
is lit;
If the signal is high, LED is off.
