GOWIN DK START GW1NS-LV4CQN48C7I6 V1.1, Schematic Manual, Page: 6 / 16

GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA
Products Schematic Manual
UG292-1.0E
www.gowinsemi.com.en 6
(
15
)
I/O output standard Single/Differ Bank V
CCO
(V) Output Driver Strength (mA)
SSTL25D_I Differential 2.5 8
SSTL25D_II Differential 2.5 8
SSTL33D_I Differential 3.3 8
SSTL33D_II Differential 3.3 8
SSTL18D_I Differential 1.8 8
SSTL18D_II Differential 1.8 8
HSTL18D_I Differential 1.8 8
HSTL18D_II Differential 1.8 8
HSTL15D_I Differential 1.5 8
 Note!
 See pinout manuals for specific differential pin positions.
READY, RECONFIG_N, DONE
Overview
RECONFIG_N, equivalent to the reset function of FPGA programming
configuration, FPGA cannot perform any configuration operation when
RECONFIG_N is pulled down.
As a configuration pin, a low level with a pulse width of not less than
25ns is required for GowinCONFIG configuration mode to enable the
device to reload the bitstream. You can control the pin by writing logic to
trigger the device to reconfigure as required.
You can configure FPGA only when the READY signal is high. The
device should be restored by power on or triggering RECONFIG_N when
the READY signal is low.
As an output configuration pin, it can indicate whether the FPGA can
be configured currently. If the device is ready, READY signal is high. If the
device fails to configure, the READY signal changes to low. As an input
configuration pin, you can delay the configuration by its own logic or pulling
down the READY signal.
DONE signal indicates that the FPGA is configured successfully. The
signal is high after successful configuration.
As an output configuration pin, it can indicate whether FPGA
configuration is successful. If configured successfully, DONE is high, and
the device enters into an operating state. If the device failed to configure,
the DONE signal remains low. As the input, you can delay the entry into
user mode by manually pulling down the DONE signal via the logic.
When RECONFIG_N or READY signals are low, DONE signal is also
low. When configuring SRAM using JTAG circuit, it does not need to take
DONE signal into account.