GW1NS & GW1NSR & GW1NSE & GW1NSER Series of FPGA
Products Schematic Manual
UG292-1.0E
www.gowinsemi.com.en
5
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15
)
Signal Description
Table 4 Signal Description
Name
I/O
Description
GCLKT_[x]
I/O
Pins in global clock input, T(True), [x]: global clock
No.
GCLKC_[x]
I/O
Pins for Global clock input, C(Comp), [x]: global
clock No.
LPLL_T_fb/RPLL_T_fb
I
Left/Right PLL feedback input pins, T(True)
LPLL_C_fb/RPLL_C_fb I
Left/Right PLL feedback input pins, C(Comp)
LPLL_T_in/RPLL_T_in
I
Left/Right PLL clock input pin, T(True)
LPLL_C_in/RPLL_C_in I
Left/Right PLL clock input pin, C(Comp)
Clock Input Selection
If the external clock as PLL clock, it is recommended to input from
PLL_T.
GCLK is the global clock and is connected to all resources in the
device. It is recommended to input from GCLK_T.
Differential Pins
Overview
Differential transmission is a kind of signal transmission, which is
different from the traditional signal line and ground line. Differential
transmission signals are transmitted on these two lines. These two signals
are with same amplitudeAmplitude, phase and opposite polarity.
Differential Type
Figure 5 Differential Type
I/O output standard
Single/Differ
Bank V
CCO
(V)
Output Driver Strength (mA)
LVPECL33E
Differential
3.3
16
MVLDS25E
Differential
2.5
16
BLVDS25E
Differential
2.5
16
RSDS25E
Differential
2.5
8
LVDS25E
Differential
2.5
8
LVDS25
Differential
2.5/3.3
3.5/2.5/2/6
RSDS
Differential
2.5/3.3
2
MINILVDS
Differential
2.5/3.3
2
PPLVDS
Differential
2.5/3.3
3.5
SSTL15D
Differential
1.5
8