GOWIN DK-START-GW1NR9 User Manual Download | Manualshive

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List of Tables

DBUG361-1.2E

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List of Tables

Table 1-1 Abbreviation and Terminology ............................................................................................ 2

Table 2-1 Development Board Specification ...................................................................................... 9

Table 3-1 GW1NR-9 FPGA Resources List ....................................................................................... 11

Table 3-2 FPGA I/O Pins Distribution ................................................................................................. 13

Table 3-3 FPGA Download Pins Distribution ..................................................................................... 14

Table 3-4 FPGA Power Pins Distribution ........................................................................................... 16

Table 3-5 FPGA Clock and Reset Pins Distribution ........................................................................... 17

Table 3-6 LED Pins Distribution ......................................................................................................... 18

Table 3-7 Switch Circuit Pins Distribution .......................................................................................... 19

Table 3-8 Key Circut Pins Distribution ............................................................................................... 20

Table 3-9 J14 GPIO Pins Distribution ................................................................................................ 22

Table3-10 J13 GPIO Pins Distribution ............................................................................................... 22

Table 3-11 J15 FPGA Pin Distribution (IDES16:1 Supported) ........................................................... 25

Table 3-12 J17 FPGA Pin Distribution ............................................................................................... 25

Table 3-13 J16 FPGA Pin Distribution (IDES16:1 Supported) ........................................................... 27

Table 3-14 J18 FPGA Pin Distribution (IDES16:1 Supported) ........................................................... 28

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Summary of Contents for DK-START-GW1NR9

Page 1: ...DK START GW1NR9 V1 1 User Guide DBUG361 1 2E 2019 12 19 ...

Page 2: ... identified as trademarks or service marks are the property of their respective holders as described at www gowinsemi com GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms...

Page 3: ...Revision History Date Version Description 03 19 2019 1 0E Initial version published 11 29 2019 1 1E MIPI input function removed 12 19 2019 1 2E The version of DK START GW1NR9 added ...

Page 4: ...3 2 Development Board Introduction 4 2 1 Overview 4 2 2 A Development Board Suite 5 2 3 PCB Components 6 2 4 System Diagram 7 2 5 Feature 8 2 6 Development Board Specification 9 3 Development Board Circuit 11 3 1 FPGA Module 11 3 1 1 Overview 11 3 1 2 I O BANK Introduction 12 3 2 Download 14 3 2 1 Overview 14 3 2 2 USB Download Circuit 14 3 2 3 Download Flow 14 3 2 4 Pins Distribution 14 3 3 Power...

Page 5: ...Circuit 18 3 5 3 Pins Distribution 18 3 6 Switches 19 3 6 1 Overview 19 3 6 2 Switch Circuit 19 3 6 3 Pins Distribution 19 3 7 Key 20 3 7 1 Overview 20 3 7 2 Key Circuit 20 3 7 3 Pins Distribution 20 3 8 GPIO 21 3 8 1 Overview 21 3 8 2 GPIO Circuit 21 3 8 3 Pins Distribution 22 3 9 MIPI LVDS 24 3 9 1 Overview 24 3 9 2 MIPI LVDS Circuit 24 3 9 3 Pins Distribution 25 4 Precautions 29 5 Gowin YunYuan...

Page 6: ...m 7 Figure 3 1 GW1NR series FPGA Products I O Bank Distribution 12 Figure 3 2 GW1N 9 LQ144 Package Pins Distribution Top View 13 Figure 3 3 Connection Diagram for FPGA USB Download 14 Figure 3 4 Power System Distribution 16 Figure 3 5 Clock Reset 17 Figure 3 6 LED Circuit 18 Figure 3 7 Switch Circuit 19 Figure 3 8 Key Circuit Diagram 20 Figure 3 9 GPIO Circuit 21 Figure 3 10 LVDS Circuit 24 ...

Page 7: ...istribution 16 Table 3 5 FPGA Clock and Reset Pins Distribution 17 Table 3 6 LED Pins Distribution 18 Table 3 7 Switch Circuit Pins Distribution 19 Table 3 8 Key Circut Pins Distribution 20 Table 3 9 J14 GPIO Pins Distribution 22 Table3 10 J13 GPIO Pins Distribution 22 Table 3 11 J15 FPGA Pin Distribution IDES16 1 Supported 25 Table 3 12 J17 FPGA Pin Distribution 25 Table 3 13 J16 FPGA Pin Distrib...

Page 8: ...oard 4 An introduction to the usage of the FPGA development software 1 2 Supported Products The information in the guide applies to GW1NR series of FPGA products GW1NR 9 1 3 Related Documents The user manuals are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS117 GW1NR Series FPGA Products Data Sheet 2 UG119 GW1NR Series of FPGA Products Package and ...

Page 9: ...ess memory CFU Configurable Function Unit CLS Configurable Logic Slice CRU Configurable Routing Unit LUT4 Four input Look up Tables LUT5 Five input Look up Tables LUT6 Six input Look up Tables LUT7 Seven input Look up Tables LUT8 Eight input Look up Tables REG Register ALU Arithmetic Logic Unit IOB Input Output Block S SRAM Shadow SRAM B SRAM Block Static Random Access Memory SP Single Port SDP Se...

Page 10: ...and Feedback Gowin Semiconductor provides customers with comprehensive technical support If you have any questions comments or suggestions please feel free to contact us directly by the following ways Website www gowinsemi com E mail support gowinsemi com Tel 86 755 8262 0391 ...

Page 11: ...the Gowin LittleBee family and it is a SIP chip Based on GW1N GW1NR series integrates abundant PSRAM At the same time it has the characteristics of low power consumption instant start low cost non volatility high security rich packages convenient and flexible usage etc which can effectively reduce the learning cost and help users quickly enter the design and development field of programmable logic...

Page 12: ...to learn to use 2 2 A Development Board Suite A development board suite includes the following items DK START GW1NR9 V1 1 Development Board USB Cable Quick Start Guide Figure2 2A Development Board Suite11 1 2 3 3 Gowin DK START GW1NR9 Development Board USB Cable 1 2 3 3 Quick Start Guide DK START GW1NR9 V1 1 Development Board USB Cable Quick Start Guide ...

Page 13: ...lopment Board Introduction 2 3 PCB Components DBUG361 1 2E 6 30 2 3 PCB Components Figure2 3 PCB Components GPIO 1 2V 3 3V OSC LED RESET FPGA Download 5V IN FPGA 1 8V LVDS LVDS 2 5V LVDS LVDS GPIO SWITCH KEY ...

Page 14: ...m Diagram DBUG361 1 2E 7 30 2 4 System Diagram Figure2 4 System Diagram 4 LED 4 SWITCH OSC 50MHz 10Pairs LVDS MIPI INPUT 4 BUTTON 10Pairs LVDS MIPI OUTPUT 20PIN GPIO FPGA Mini USB Interface 40PIN GPIO GW1NR LV9LQ144P 5V LDO 1 2V 1 8V 2 5V 3 3V ...

Page 15: ...cities of B SRAM 2 FPGA Configuration Mode JTAG AUTO BOOT 3 Clock resource 50MHz Clock Crystal Oscillator 4 Key switch and slide switch One reset button Four key switches Four Slide switch 5 LED One power indicator green One DONE indicator green Four LEDs green 6 Memory 1Mbit embedded Flash 64Mbit embedded PSRAM 7 MIPI LVDS 10 pairs of LVDS differential input 10 pairs of MIPI LVDS differential out...

Page 16: ...s Available for testing 4 6 Reset button Reset for FPGA 1 7 LED Test indicator DONE indicator Power indicator Four Test indicators green One DONE indicator green One Power indicator green 8 Crystal Oscillator Provide 50MHz clock for FPGA Package5032 9 Memory Provides abundant Flash and PSRAM for design 1Mbit embedded Flash 64Mbit embedded PSRAM 10 GPIO I O convenient for user extension and test 36...

Page 17: ...2 Development Board Introduction 2 6 Development Board Specification DBUG361 1 2E 10 30 No Item Functional Description Technical Condition Remarks 15 Temperatur e Operating range 20 70 ...

Page 18: ...3 1 GW1NR 9 FPGA Resources List Device GW1NR 9 LUT4 8 640 Flip Flop FF 6 480 Shadow SRAM S SRAM bits 17 280 Block Static Random Access Memory B SRAM bits 468K B SRAM quantity B SRAM 26 User Flash bits 608K PSRAM bits 64M 18 x 18 Multiplier 20 PLLs DLLs 2 4 Total number of I O banks 4 Max user I O1 120 Core Voltage LV 1 2V Note See DS117 GW1NR series of FPGA Products Data Sheet for further details ...

Page 19: ...ule DBUG361 1 2E 12 30 3 1 2 I O BANK Introduction There are four I O Banks in the GW1NR series of FPGA products as shown in Figure 3 1 Figure 3 1 GW1NR series FPGA Products I O Bank Distribution GW1NR I O BANK0 I O BANK2 I O BANK1 I O BANK3 ...

Page 20: ...ution Top View Table 3 2 FPGA I O Pins Distribution I O BANK No Modules Connected I O BANK0 Pins selection for download mode LVDS differential input GPIO I O BANK1 GPIO 50MHz clock input LED Slide Switches Key Switches Reset I O BANK2 MIPI LVDS differential output GPIO I O BANK3 GPIO Interface JTAG download ...

Page 21: ...ata stream file will not be lost if the device is powered down 3 2 2 USB Download Circuit Figure3 3 Connection Diagram for FPGA USB Download TMS_FTDI TCK_FTDI TDI_FTDI TDO_FTDI USB to JTAG Chip USB_D USB_D 14 13 16 18 U1 U17 GW1NR LV9LQ144P 3 2 3 Download Flow Please plug USB download cable into the USB interface J6 of the development board to download FPGA and then open Programmer click SRAM mode...

Page 22: ... JTAG Signal 1 8V MODE0 144 0 Mode selection pin 2 5V MODE1 143 0 Mode selection pin 2 5V RECONFIG_N 20 3 RECONFIG_N 1 8V DONE 21 3 One DONE indicator 1 8V READY 22 3 READY 1 8V 3 3 Power Supply 3 3 1 Overview DC5V is input by USB interface The TI LDO power supply chip is used to step down voltage from 5V to 3 3V 2 5V 1 8V and 1 2V which can meet the power demand of the development board ...

Page 23: ...LDO 1 2V TPS7A7001 LDO 3 3V TPS7A7001 LDO 2 5V USB to JTAG FT2232 Key LED Reset switch FPGA VCCO2 LVDS FPGA VCCX VCCO0 VCCO1 FPGA VCC FPGA VCCO2 MIPI TPS7A7001 LDO 1 8V FPGA VCCO3 PSRAM 3 3 3 Pins Distribution Table 3 4 FPGA Power Pins Distribution Signal Name Pin No BANK Description I O Level VCCO0 109 127 0 I O Bank Voltage 2 5V VCCO1 91 103 1 I O Bank Voltage 2 5V ...

Page 24: ...rd provides a 50MHz crystal oscillator connected to the PLL input pin This can be employed as the input clock for the PLL in FPGA Frequency division and multiplication of PLL can output the clock required by the user 3 4 2 Clock Reset Figure3 5 Clock Reset 106 90 KEY5 ADM811 3 3V FPGA_RST_N FPGA_CLK U1 U2 X2 GW1NR LV9LQ144P 3 4 3 Pins Distribution Table 3 5 FPGA Clock and Reset Pins Distribution S...

Page 25: ...s Users can test the LEDs in the following ways When the FPGA corresponding pin output signal is logic low the LED is lit If the signal is high LED is off 3 5 2 LED Circuit Figure3 6 LED Circuit LED1 100 LED2 101 LED3 102 LED4 104 VCC3P3 F_LED1 F_LED2 F_LED3 F_LED4 U1 GW1NR LV9LQ144P 3 5 3 Pins Distribution Table 3 6 LED Pins Distribution Signal Name Pin No BANK Description I O Level F_LED1 100 1 ...

Page 26: ...g testing 3 6 2 Switch Circuit Figure3 7 Switch Circuit SW1 95 SW4 92 VCC3P3 U1 F_SW1 F_SW4 GW1NR LV9LQ144P SW2 94 F_SW2 SW3 93 F_SW3 3 6 3 Pins Distribution Table 3 7 Switch Circuit Pins Distribution Signal Name Pin No BANK Description I O Level F_SW1 95 1 Slide Switch1 2 5V F_SW2 94 1 Slide Switch2 2 5V F_SW3 93 1 Slide Switch3 2 5V F_SW4 92 1 Slide Switch2 2 5V ...

Page 27: ...corresponding FPGA pins for testing purposes 3 7 2 Key Circuit Figure3 8 Key Circuit Diagram 99 98 97 96 KEY1 KEY2 KEY3 KEY4 U1 F_KEY1 F_KEY2 F_KEY3 F_KEY4 GW1NR LV9LQ144P VCC3P3 3 7 3 Pins Distribution Table 3 8 Key Circut Pins Distribution Signal Name Pin No BANK Description I O Level F_KEY1 99 1 KEY1 2 5V F_KEY2 98 1 KEY2 2 5V F_KEY3 97 1 KEY3 2 5V F_KEY4 96 1 KEY4 2 5V ...

Page 28: ..._A_IO9 H_A_IO11 H_A_IO13 H_A_IO15 H_A_IO2 H_A_IO4 H_A_IO6 H_A_IO8 H_A_IO10 H_A_IO12 H_A_IO14 H_A_IO16 J14 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 H_B_IO1 3 3V H_B_IO3 H_B_IO5 H_B_IO7 H_B_IO9 H_B_IO11 H_B_IO13 H_B_IO15 H_B_IO2 H_B_IO4 H_B_IO6 H_B_IO8 H_B_IO10 H_B_IO12 H_B_IO14 H_B_IO16 J13 H_A_IO17 H_A_IO18 H_B_IO17 H_B_IO18 H_A_IO19 21 23 25 27 29 31 33 35 37 H_B_IO19 H_B_IO21 H_B_IO23 ...

Page 29: ...IO11 11 11 3 General I O 1 8V H_A_IO12 12 12 3 General I O 1 8V H_A_IO13 15 13 3 General I O 1 8V H_A_IO14 23 14 3 General I O 1 8V H_A_IO15 24 15 3 General I O 1 8V H_A_IO16 25 16 3 General I O 1 8V H_A_IO17 26 17 3 General I O 1 8V H_A_IO18 27 18 3 General I O 1 8V H_A_IO19 28 19 3 General I O 1 8V GND 20 GND Table3 10 J13 GPIO Pins Distribution Signal Name Pin No Socket Pin No BANK Description ...

Page 30: ... VCCO2 H_B_IO20 78 20 2 General I O VCCO2 H_B_IO21 44 21 2 General I O VCCO2 H_B_IO22 45 22 2 General I O VCCO2 H_B_IO23 48 23 2 General I O VCCO2 H_B_IO24 49 24 2 General I O VCCO2 H_B_IO25 65 25 2 General I O VCCO2 H_B_IO26 64 26 2 General I O VCCO2 H_B_IO27 61 27 2 General I O VCCO2 H_B_IO28 60 28 2 General I O VCCO2 H_B_IO29 57 29 2 General I O VCCO2 H_B_IO30 56 30 2 General I O VCCO2 H_B_IO31...

Page 31: ...LVDS_A2_P F_LVDS_A3_P F_LVDS_A4_P F_LVDS_A5_P F_LVDS_A1_N F_LVDS_A2_N F_LVDS_A3_N F_LVDS_A4_N F_LVDS_A5_N J15 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_B1_P F_LVDS_B2_P F_LVDS_B3_P F_LVDS_B4_P F_LVDS_B5_P F_LVDS_B1_N F_LVDS_B2_N F_LVDS_B3_N F_LVDS_B4_N F_LVDS_B5_N J16 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_A6_P F_LVDS_A7_P F_LVDS_A8_P F_LVDS_A9_P F_LVDS_A10_P F_L...

Page 32: ...nnel 2 2 5V LVDS GND 7 GND 8 F_LVDS_A3_P 125 9 0 Differential input channel 3 2 5V LVDS F_LVDS_A3_N 124 10 0 Differential input channel 3 2 5V LVDS GND 11 GND 12 F_LVDS_A4_P 123 13 0 Differential input channel 4 2 5V LVDS F_LVDS_A4_N 122 14 0 Differential input channel 4 2 5V LVDS GND 15 GND 16 F_LVDS_A5_P 115 17 1 Differential input channel 5 2 5V LVDS F_LVDS_A5_N 114 18 1 Differential input chan...

Page 33: ...ut channel 7 2 5V LVDS GND 7 GND 8 F_LVDS_A8_P 117 9 1 Differential input channel 8 2 5V LVDS F_LVDS_A8_N 116 10 1 Differential input channel 8 2 5V LVDS GND 11 GND 12 F_LVDS_A9_P 113 13 1 Differential input channel 9 2 5V LVDS F_LVDS_A9_N 112 14 1 Differential input channel 9 2 5V LVDS GND 15 GND 16 F_LVDS_A10_P 111 17 1 Differential input channel 10 2 5V LVDS F_LVDS_A10_N 110 18 1 Differential i...

Page 34: ...t channel 2 2 5V LVDS 1 2V MIPI F_LVDS_B2_N 39 6 2 Differential output channel 2 2 5V LVDS 1 2V MIPI GND 7 GND 8 F_LVDS_B3_P 42 9 2 Differential output channel 3 2 5V LVDS 1 2V MIPI F_LVDS_B3_N 43 10 2 Differential output channel 3 2 5V LVDS 1 2V MIPI GND 11 GND 12 F_LVDS_B4_P 46 13 2 Differential output channel 4 2 5V LVDS 1 2V MIPI F_LVDS_B4_N 47 14 2 Differential output channel 4 2 5V LVDS 1 2V...

Page 35: ..._P 62 5 2 Differential output channel 7 2 5V LVDS 1 2V MIPI F_LVDS_B7_N 63 6 2 Differential output channel 7 2 5V LVDS 1 2V MIPI GND 7 GND 8 F_LVDS_B8_P 66 9 2 Differential output channel 8 2 5V LVDS 1 2V MIPI F_LVDS_B8_N 67 10 2 Differential output channel 8 2 5V LVDS 1 2V MIPI GND 11 GND 12 F_LVDS_B9_P 70 13 2 Differential output channel 9 2 5V LVDS 1 2V MIPI F_LVDS_B9_N 71 14 2 Differential out...

Page 36: ... and pay attention to electrostatic protection 2 VCCO2 Bank voltage needs to be set as 2 5V when the Bank2 output differential pairs serve as LVDS output VCCO2 Bank voltage needs to be set as 1 2V when the Bank2 output differential pairs serve as MIPI output 3 DK START GWS1NR9 V1 1 does not support MIPI input ...

Page 37: ...5 Gowin YunYuan Software DBUG361 1 2E 30 30 5 Gowin YunYuan Software Please refer to SUG100 Gowin Software User Guide for details ...

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