GOWIN DK START GW1N-LV9EQ144C6I5 V2.1 User Manual Download Page 9

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1 About This Guide

1.4 Support and Feedback

DBUG392-1.0E

2(23)

Terminology and Abbreviations

Meaning

SIP

System in Package

SDRAM

Synchronous Dynamic RAM

PSRAM

Pseudo static random access memory

CFU

Configurable Function Unit

CLS

Configurable Logic Slice

CRU

Configurable Routing Unit

LUT4

4-input Look-up Tables

LUT5

5-input Look-up Tables

LUT6

6-input Look-up Tables

LUT7

7-input Look-up Tables

LUT8

8-input Look-up Tables

REG

ALU

Arithmetic Logic Unit

IOB

Input/Output Block

SSRAM

Shadow Static Random Access Memory

BSRAM

Block Static Random Access Memory

Single Port

SDP

Semi Dual Port

Dual Port

DSP

Digital Signal Processing

DQCE

Dynamic Quadrant Clock Enable

DCS

Dynamic Clock Selector

PLL

Phase-locked Loop

DLL

Delay-locked Loop

EQ144

EQFP144 package

1.4

Support and Feedback

Gowin Semiconductor provides customers with comprehensive

technical support. If you have any questions, comments, or suggestions,
please feel free to contact us directly by the following ways.

Website:

www.gowinsemi.com

E-mail:

[email protected]

Summary of Contents for DK START GW1N-LV9EQ144C6I5 V2.1

Page 1: ...DK_START_GW1N LV9EQ144C6I5_V2 1 User Guide DBUG392 1 0E 07 21 2021 ...

Page 2: ... mechanical photocopying recording or otherwise without the prior written consent of GOWINSEMI Disclaimer GOWINSEMI assumes no liability and provides no warranty either expressed or implied and is not responsible for any damage incurred to your hardware software data or property resulting from usage of the materials or intellectual property except as outlined in the GOWINSEMI Terms and Conditions ...

Page 3: ...Revision History Date Version Description 07 21 2021 1 0E Initial version published ...

Page 4: ...Introduction 3 2 1 Overview 3 2 2 Development Kit 4 2 3 PCB Components 5 2 4 System Block Diagram 5 2 5 Features 6 2 6 Development Board Description 7 3 Development Board Circuit 9 3 1 FPGA Module 9 Overview 9 I O BANK Introduction 9 3 2 Download 9 3 2 1 Overview 9 3 2 2 USB Download Circuit 10 3 2 3 Download Flow 10 3 2 4 Pinout 10 3 3 Power Supply 10 3 3 1 Overview 10 3 3 2 Power System Distribu...

Page 5: ...D Circuit 13 3 5 3 Pinout 13 3 6 Switches 13 3 6 1 Overview 13 3 6 2 Switch Circuit 13 3 6 3 Pinout 14 3 7 Key 14 3 7 1 Overview 14 3 7 2 Key Circuit 14 3 7 3 Pinout 14 3 8 GPIO 15 3 8 1 Overview 15 3 8 2 GPIO Circuit 15 3 8 3 Pinout 16 3 9 MIPI LVDS 18 3 9 1 Overview 18 3 9 2 MIPI LVDS Circuit 18 3 9 3 Pinout 19 4 Consideration 22 5 Gowin Software 23 ...

Page 6: ...lopment Kit 4 Figure 2 3 PCB Components 5 Figure 2 4 System Block Diagram 5 Figure 3 1 FPGA USB Download Diagram 10 Figure 3 2 Power System Distribution 11 Figure 3 3 Clock Circuit 12 Figure 3 4 LED Circuit 13 Figure 3 5 Switch Circuit 13 Figure 3 6 Key Circuit Diagram 14 Figure 3 7 GPIO Circuit 15 Figure 3 8 MIPI LVDS Circuit 18 ...

Page 7: ...10 Table 3 2 FPGA Power Pinout 11 Table 3 3 FPGA Clock Pinout 12 Table 3 4 LED Pinout 13 Table 3 5 Switch Circuit Pinout 14 Table 3 6 Key Circuit Pinout 14 Table 3 7 J14 GPIO Pinout 16 Table 3 8 J13 GPIO Pinout 16 Table 3 9 J15 FPGA Pinout IDES 16 1 Supported 19 Table 3 10 J16 FPGA Pinout IDES 16 1 Supported 20 Table 3 11 J18 FPGA Pinout IDES 16 1 Supported 21 ...

Page 8: ...velopment software 1 2 Related Documents The latest user guides are available on the GOWINSEMI Website You can find the related documents at www gowinsemi com 1 DS100 GW1N series of FPGA Products Data Sheet 2 UG103 GW1N series of FPGA Products Package and Pinout Manual 3 UG801 GW1N 9 Pinout 4 UG290 Gowin FPGA Products Programming and Configuration Guide 5 SUG100 Gowin Software User Guide 1 3 Termi...

Page 9: ...bles REG Register ALU Arithmetic Logic Unit IOB Input Output Block SSRAM Shadow Static Random Access Memory BSRAM Block Static Random Access Memory SP Single Port SDP Semi Dual Port DP Dual Port DSP Digital Signal Processing DQCE Dynamic Quadrant Clock Enable DCS Dynamic Clock Selector PLL Phase locked Loop DLL Delay locked Loop EQ144 EQFP144 package 1 4 Support and Feedback Gowin Semiconductor pr...

Page 10: ...e characteristics of low power consumption instant start low cost non volatility high security rich packages convenient and flexible usage etc which can effectively reduce the learning cost and help users quickly enter the design and development field of programmable logic devices The development board offers abundant external interfaces including MIPI LVDS interfaces GPIO interfaces etc There are...

Page 11: ...1 0E 4 23 2 2 Development Kit A development board suite includes the following items DK_START_GW1N LV9EQ144C6I5_V2 1 development board USB Data Line Figure 2 2 A Development Kit 2 1 DK_START_GW1N LV9EQ144C6I5_V2 1 development board USB Data Line ...

Page 12: ...Components Figure 2 3 PCB Components 2 4 System Block Diagram Figure 2 4 System Block Diagram 4 LED 2 SWITCH OSC 50MHz 5Pairs LVDS MIPI INPUT 2 BUTTON 10Pairs LVDS MIPI OUTPUT 20PIN GPIO FPGA Mini USB Interface 40PIN GPIO GW1N LV9EQ144C6 I5 5V LDO 1 2V 2 5V 3 3V ...

Page 13: ...es and capacities of B SRAM 2 FPGA Configuration Modes JTAG AUTO BOOT 3 Clock resource 50MHz Clock Crystal Oscillator 4 Key switch and slide switch Two key switches Two slide switches 5 LED One power indicator green One DONE indicator green Four LEDs green 6 Memory 1Mbit embedded Flash 7 MIPI LVDS 5 pairs of MIPI LVDS differential input 10 pairs of MIPI LVDS differential output 8 GPIO 55 I O expan...

Page 14: ... FPGA via 5V to 2 5V circuit Provide power for FPGA via 5 V 1 2 V circuit 4 Switches Available for testing 2 5 Key Switches Available for testing 2 6 LED Test indicator DONE indicator Power indicator Four Test indicators green One DONE indicator green One Power indicator green 7 Crystal Oscillator Provide 50MHz clock for FPGA Package5032 8 Memory Provides abundant Flash for design 1Mbit embedded F...

Page 15: ...2 Introduction 2 6 Development Board Description DBUG392 1 0E 8 23 No Name Functional Description Technical Condition Note 13 Humidity 95 14 Temperature Operating range 20 70 ...

Page 16: ...ation see UG103 GW1N Series of FPGA Products Package and Pinout User Guide 3 2 Download 3 2 1 Overview The development board provides an USB download interface The bitstream file can be downloaded to the internal SRAM or internal flash as needed Note When downloaded to SRAM the bitstream file will be lost if the device is powered down and it will need to be downloaded again after power on If downl...

Page 17: ... download bit stream file to SRAM or flash 3 2 4 Pinout Table 3 1 FPGA Download Pinout Name Pin No BANK Description I O Level TMS_FTDI 13 3 JTAG Signal 3 3V TCK_ FTDI 14 3 JTAG Signal 3 3V TDI_ FTDI 16 3 JTAG Signal 3 3V TDO_ FTDI 18 3 JTAG Signal 3 3V MODE0 144 3 Mode selection pin 3 3V MODE1 143 3 Mode selection pin 3 3V RECONFIG_N 20 3 RECONFIG_N 3 3V DONE 21 3 DONE indicator 3 3V READY 22 3 RE...

Page 18: ...set Switch VCCO3 FPGA VCCO2 LVDS FPGA VCCX VCCO0 VCCO1 FPGA VCC FPGA VCCO2 VCCO0 VCCO1 MIPI 3 3 3 Pins Distribution Table 3 2 FPGA Power Pinout Name Pin No BANK Description I O Level VCCO0 109 127 0 I O Bank Voltage 2 5V 1 2V VCCO1 91 103 1 I O Bank Voltage 2 5V 1 2V VCCO2 37 55 2 I O Bank Voltage 2 5V 1 2V VCCO3 5 19 3 I O Bank Voltage 3 3V VCCX 31 77 Auxiliary voltage 2 5V VCC 1 36 73 108 Core v...

Page 19: ...cuit 106 FPGA_CLK U1 X2 GW1N LV9EQ144C6I5 3 4 3 Pinout Table 3 3 FPGA Clock Pinout Name Pin No BANK Description I O Level FPGA_CLK 106 1 50MHz crystal oscillator input 2 5V 1 2V 3 5 LED 3 5 1 Overview There are four green LEDs in the development board and users can display the required status through the LED In addition two LEDs are reserved to signify the power supply and FPGA loading status You ...

Page 20: ... 3 4 LED Pinout Name Pin No BANK Description I O Level F_LED1 100 1 LED1 2 5V 1 2V F_LED2 101 1 LED2 2 5V 1 2V F_LED3 102 1 LED3 2 5V 1 2V F_LED4 104 1 LED 4 2 5V 1 2V 3 6 Switches 3 6 1 Overview Two Slide switches are incorporated into the development board These are used to control input during testing 3 6 2 Switch Circuit Figure 3 5 Switch Circuit SW1 95 VCC2P5 VCC1P2 U1 F_SW1 GW1N LV9EQ144C6I5...

Page 21: ... 3 7 Key 3 7 1 Overview Two key switches are embedded in the development board Users can manually input a low level to the corresponding FPGA pins for testing purposes 3 7 2 Key Circuit Figure 3 6 Key Circuit Diagram 99 98 KEY1 KEY2 U1 F_KEY1 F_KEY2 GW1N LV9EQ144C6I5 VCC3P3 3 7 3 Pinout Table 3 6 Key Circuit Pinout Name Pin No BANK Description I O Level F_KEY1 99 1 KEY1 2 5V 1 2V F_KEY2 98 1 KEY2 ...

Page 22: ..._A_IO9 H_A_IO11 H_A_IO13 H_A_IO15 H_A_IO2 H_A_IO4 H_A_IO6 H_A_IO8 H_A_IO10 H_A_IO12 H_A_IO14 H_A_IO16 J14 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 H_B_IO1 3 3V H_B_IO3 H_B_IO5 H_B_IO7 H_B_IO9 H_B_IO11 H_B_IO13 H_B_IO15 H_B_IO2 H_B_IO4 H_B_IO6 H_B_IO8 H_B_IO10 H_B_IO12 H_B_IO14 H_B_IO16 J13 H_A_IO17 H_A_IO18 H_B_IO17 H_B_IO18 H_A_IO19 21 23 25 27 29 31 33 35 37 H_B_IO19 H_B_IO21 H_B_IO23 ...

Page 23: ...General I O 3 3V H_A_IO13 15 13 3 General I O 3 3V H_A_IO14 23 14 3 General I O 3 3V H_A_IO15 24 15 3 General I O 3 3V H_A_IO16 25 16 3 General I O 3 3V H_A_IO17 26 17 3 General I O 3 3V H_A_IO18 27 18 3 General I O 3 3V H_A_IO19 28 19 3 General I O 3 3V GND 20 GND Table 3 8 J13 GPIO Pinout Name Pin No Socket Pin No BANK Description I O Level H_B_IO1 132 1 0 General I O 2 5V 1 2V H_B_IO2 131 2 0 G...

Page 24: ... O 2 5V 1 2V H_B_IO21 44 21 2 General I O 2 5V 1 2V H_B_IO22 45 22 2 General I O 2 5V 1 2V H_B_IO23 48 23 2 General I O 2 5V 1 2V H_B_IO24 49 24 2 General I O 2 5V 1 2V H_B_IO25 65 25 2 General I O 2 5V 1 2V H_B_IO26 64 26 2 General I O 2 5V 1 2V H_B_IO27 61 27 2 General I O 2 5V 1 2V H_B_IO28 60 28 2 General I O 2 5V 1 2V H_B_IO29 57 29 2 General I O 2 5V 1 2V H_B_IO30 56 30 2 General I O 2 5V 1 ...

Page 25: ...ure 3 8 MIPI LVDS Circuit 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_A1_P F_LVDS_A2_P F_LVDS_A3_P F_LVDS_A4_P F_LVDS_A5_P F_LVDS_A1_N F_LVDS_A2_N F_LVDS_A3_N F_LVDS_A4_N F_LVDS_A5_N J15 1 3 5 7 9 2 4 6 8 10 11 13 15 17 19 12 14 16 18 20 F_LVDS_B1_P F_LVDS_B2_P F_LVDS_B3_P F_LVDS_B4_P F_LVDS_B5_P F_LVDS_B1_N F_LVDS_B2_N F_LVDS_B3_N F_LVDS_B4_N F_LVDS_B5_N J16 1 3 5 7 9 2 4 6 8 10 11 ...

Page 26: ...hannel 2 2 5V LVDS 1 2V MIPI F_LVDS_A2_N 133 6 0 Differential input channel 2 2 5V LVDS 1 2V MIPI GND 7 GND 8 F_LVDS_A3_P 125 9 0 Differential input channel 3 2 5V LVDS 1 2V MIPI F_LVDS_A3_N 124 10 0 Differential input channel 3 2 5V LVDS 1 2V MIPI GND 11 GND 12 F_LVDS_A4_P 123 13 0 Differential input channel 4 2 5V LVDS 1 2V MIPI F_LVDS_A4_N 122 14 0 Differential input channel 4 2 5V LVDS 1 2V MI...

Page 27: ... 2 2 5V LVDS 1 2V MIPI F_LVDS_B2_N 39 6 2 Differential output channel 2 2 5V LVDS 1 2V MIPI GND 7 GND 8 F_LVDS_B3_P 42 9 2 Differential output channel 3 2 5V LVDS 1 2V MIPI F_LVDS_B3_N 43 10 2 Differential output channel 3 2 5V LVDS 1 2V MIPI GND 11 GND 12 F_LVDS_B4_P 46 13 2 Differential output channel 4 2 5V LVDS 1 2V MIPI F_LVDS_B4_N 47 14 2 Differential output channel 4 2 5V LVDS 1 2V MIPI GND...

Page 28: ...7 2 5V LVDS 1 2V MIPI F_LVDS_B7_N 63 6 2 Differential output channel 7 2 5V LVDS 1 2V MIPI GND 7 GND 8 F_LVDS_B8_P 66 9 2 Differential output channel 8 2 5V LVDS 1 2V MIPI F_LVDS_B8_N 67 10 2 Differential output channel 8 2 5V LVDS 1 2V MIPI GND 11 GND 12 F_LVDS_B9_P 70 13 2 Differential output channel 9 2 5V LVDS 1 2V MIPI F_LVDS_B9_N 71 14 2 Differential output channel 9 2 5V LVDS 1 2V MIPI GND ...

Page 29: ...to be set as 2 5V when the Bank2 output differential pairs serve as LVDS output VCCO2 Bank voltage needs to be set as 1 2V when the Bank2 output differential pairs serve as MIPI output 3 VCCO0 Bank voltage needs to be set as 2 5V when the Bank0 Input differential pairs serve as LVDS Input VCCO0 Bank voltage needs to be set as 1 2V when the Bank0 Input differential pairs serve as MIPI Input ...

Page 30: ...5 Gowin Software DBUG392 1 0E 23 23 5 Gowin Software See SUG100 Gowin Software User Guide for details ...

Page 31: ......

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