2 Introduction
2.6 Development Board Description
DBUG392-1.0E
7(23)
2.6
Development Board Description
Table 2-1 Development Board Description
No. Name
Functional Description
Technical Condition
Note
1
FPGA
Core chip
–
–
2
Download
Support an USB
interface; Support
JTAG, AUTOBOOT
USB to JTAG chip integrated
on board
–
3
Power
Supply
3.3 V, 2.5V, and 1.2 V
output via LDO circuit
Input power: 5V
Provide power for FPGA,
download circuit and
other circuits via 5V to
3.3 V circuit;
Provide power for FPGA
via 5V to 2.5V circuit;
Provide power for FPGA
via 5 V–1.2 V circuit.
–
4
Switches
Available for testing
2
–
5
Key
Switches
Available for testing
2
–
6
LED
Test indicator, DONE
indicator, Power
indicator
Four Test indicators,
green
One DONE indicator,
green
One Power indicator,
green
–
7
Crystal
Oscillator
Provide 50MHz clock
for FPGA
Package5032
–
8
Memory
Provides abundant
Flash for design
1Mbit embedded Flash
–
9
GPIO
I/O for user to extend
and test
55
–
10
MIPI/LVDS
MIPI/LVDS, used for
testing
Five pairs of input, Ten pairs
of output
–
11
Protection
USB interface: ESD
protection
USB interface with ESD
protection: ±15kV
non-contact discharge and ±
8kV contact discharge;
–
12
Voltage
–
Input Voltage: 5V
–
