3 Development Board Circuit
3.5 LED
DBUG377-1.0E
14(21)
3.4.2
Clock, Reset Circuit
Figure 3-3 Clock, Reset Circuit
51
56
KEY1
27MHz
ADM811
3.3V
F_RST_N
F_CLK
U1
U4
X2
GW2AR-
LV18QN88P
3.4.3
Pinout
Table 3-3 FPGA Clock and Reset Pinout
Name
Pin No.
BANK
Description
I/O Level
F_CLK
51
3
27MHz crystal oscillator
input
3.3V
F_RST_N
56
3
Reset Signal, active-low
3.3V
3.5
LED
3.5.1
Overview
There are six green LEDs on the development board and users can
display the required status. There is one or two LEDs left to observe the
power supply and HDMI hot plug.
Users can test the LEDs in the following ways:
When the FPGA corresponding pin output signal is logic low , the LED
is lit;
If the signal is high, LED is off.
